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2016-03-17x86: link: Add pin configuration to the device treeSimon Glass1-0/+155
2016-03-17x86: Update microcode for secondary CPUsSimon Glass5-2/+12
2016-03-17x86: ivybridge: Show microcode version for each coreSimon Glass1-1/+2
2016-03-17x86: Record the CPU details when starting each coreSimon Glass3-1/+20
2016-03-17x86: Move common MRC Kconfig options to the common fileSimon Glass2-26/+62
2016-03-17x86: Allow I/O functions to use pointersSimon Glass1-2/+10
2016-03-17x86: Add macros to clear and set I/O bitsSimon Glass1-0/+22
2016-03-17x86: ivybridge: Drop sandybridge_early_init()Simon Glass1-2/+0
2016-03-17x86: Move Intel Management Engine code to a common placeSimon Glass10-369/+418
2016-03-17x86: Rename PORT_RESET to IO_PORT_RESETSimon Glass3-5/+5
2016-03-17x86: Move common CPU code to its own placeSimon Glass6-76/+162
2016-03-17x86: Move common LPC code to its own placeSimon Glass6-85/+166
2016-03-17x86: Add the root-complex block to common intel registersSimon Glass4-7/+9
2016-03-17x86: Create a common header for Intel register accessSimon Glass6-6/+22
2016-03-17x86: Move microcode code to a common locationSimon Glass6-4/+8
2016-03-17x86: Move cache-as-RAM code into a common locationSimon Glass4-1/+8
2016-03-17x86: cpu: Add functions to return the family and steppingSimon Glass2-0/+24
2016-03-17x86: broadwell: Add a few microcode filesSimon Glass2-0/+2272
2016-03-17x86: Add comments to the SIPI vectorSimon Glass2-0/+2
2016-03-17x86: Tidy up mp_init to reduce duplicationSimon Glass1-53/+26
2016-03-17x86: Correct duplicate POST valuesSimon Glass1-2/+2
2016-03-17x86: gpio: Correct GPIO setup orderingSimon Glass1-0/+5
2016-03-17x86: dts: link: Add board ID GPIOsSimon Glass1-0/+2
2016-03-17x86: dts: link: Move SPD info into the memory controllerSimon Glass1-111/+110
2016-03-17x86: link: Add required GPIO propertiesSimon Glass1-3/+9
2016-03-17x86: Add some more common MSR indexesSimon Glass3-20/+43
2016-03-17x86: cpu: Make the vendor table constSimon Glass1-1/+1
2016-03-17x86: Support booting SeaBIOSBin Meng3-0/+28
2016-03-17x86: Implement functions for writing coreboot tableBin Meng3-0/+147
2016-03-17x86: Support writing configuration tables in high areaBin Meng1-0/+11
2016-03-17x86: Simplify codes in write_tables()Bin Meng1-27/+34
2016-03-17x86: Change write_acpi_tables() signature a little bitBin Meng3-6/+5
2016-03-17x86: Use a macro for ROM table alignmentBin Meng2-5/+7
2016-03-17x86: Change to use start/end address pair in write_tables()Bin Meng1-6/+12
2016-03-17x86: Clean up coreboot_tables.hBin Meng1-73/+80
2016-03-17x86: Move sysinfo related to sysinfo.hBin Meng2-4/+2
2016-03-17x86: Move asm/arch-coreboot/tables.h to a common placeBin Meng4-3/+1
2016-03-16spl: arm: Make sure to include all of the u_boot_list entriesTom Rini5-15/+9
2016-03-16arm: omap-common: Guard some parts of the code with CONFIG_OMAP44XX/OMAP54XXTom Rini1-1/+7
2016-03-16ARM: keystone2: Only link cmd_ddr3.o on non-SPL buildsTom Rini1-1/+2
2016-03-16ARM: keystone2: Switch to using the poweroff commandTom Rini4-29/+30
2016-03-16ARM: keystone2: Split monitor code / command codeTom Rini4-52/+71
2016-03-15ARM: DRA7: DDR: Enable SR in Power Management ControlNishanth Menon1-3/+3
2016-03-15arm: Allow EFI payload code to take exceptionsAlexander Graf1-0/+8
2016-03-15arm64: Allow EFI payload code to take exceptionsAlexander Graf1-0/+9
2016-03-15arm64: Allow exceptions to returnAlexander Graf1-0/+34
2016-03-15efi_loader: Add runtime servicesAlexander Graf4-0/+54
2016-03-15arm64: Only allow dcache disabled in SPL buildsAlexander Graf1-0/+9
2016-03-15arm64: Remove non-full-va map codeAlexander Graf6-216/+85
2016-03-15tegra: Replace home grown mmu code with generic table approachAlexander Graf1-115/+17
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