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2022-11-14Merge tag 'u-boot-imx-20221114' of ↵Tom Rini67-1269/+2857
https://gitlab.denx.de/u-boot/custodians/u-boot-imx For 2022.01 ----------- CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/14083 - Fix UART - moved to binman (MX8 boards) - Toradex: sync DTS with Linux - Gateworks: fixes - New boards : MSC SM2S iMX8MP
2022-11-12imx8-u-boot: Fix SPL guard optionFabio Estevam2-2/+2
We should guard the SPL nodes against CONFIG_SPL_BUILD to fix the following build error when the blobs are absent: binman: Fail open first container file mx8qm-ahab-container.img Signed-off-by: Fabio Estevam <festevam@denx.de>
2022-11-10global: Migrate CONFIG_HPS* symbols to the CFG namespaceTom Rini4-132/+132
Migrate all of CONFIG_HPS* to the CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-10global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespaceTom Rini52-488/+487
Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-10global: Migrate CONFIG_SYS_MPC8* symbols to the CFG_SYS namespaceTom Rini29-197/+197
Migrate all of COFIG_SYS_MPC* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-11-10Convert CONFIG_SYS_NONCACHED_MEMORY to KconfigTom Rini1-0/+24
This converts the following to Kconfig: CONFIG_SYS_NONCACHED_MEMORY To do this we introduce CONFIG_SYS_HAS_NONCACHED_MEMORY as a bool to gate if we are going to have noncached_... functions available and then continue to use CONFIG_SYS_NONCACHED_MEMORY to store the size of said cache. We make this new option depend on both the architectures which implement support and the drivers which make use of it. Cc: Tom Warren <twarren@nvidia.com> Cc: Mingming lee <mingming.lee@mediatek.com> Cc: "Ying-Chun Liu (PaulLiu)" <paul.liu@linaro.org> Cc: Alban Bedel <alban.bedel@avionic-design.de> Cc: Stephen Warren <swarren@nvidia.com> Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Cc: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-10mediatek: Include <linux/sizes.h> where neededTom Rini3-0/+3
These files reference SZ_ macros without including <linux/sizes.h>, correct this. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-10powerpc: Migrate SYS_L3_SIZE to KconfigTom Rini1-0/+24
Introduce three options, one for each observed L3 cache size, and have the size select'd as needed. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-10powerpc: Migrate SYS_L2_SIZE to KconfigTom Rini1-0/+16
Introduce two options, one for each observed L2 cache size, and have the size select'd as needed. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-10Convert CONFIG_SYS_INIT_RAM_LOCK to KconfigTom Rini2-2/+4
This converts the following to Kconfig: CONFIG_SYS_INIT_RAM_LOCK Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-09Convert mx8 u-boot.dtsi to CONFIG_TEXT_BASEStefano Babic2-2/+2
Signed-off-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Fabio Estevam <festevam@denx.de>
2022-11-09imx: imx8: apalis: switch to binmanOliver Graute3-0/+5
Switch to use binman to pack images Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com>
2022-11-09imx: imx8x: colibri: switch to binmanOliver Graute2-0/+3
Switch to use binman to pack images Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com>
2022-11-09imx: imx8qxp: deneb switch to binmanOliver Graute1-0/+1
Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-11-09imx: imx8qxp: giedi switch to binmanOliver Graute2-0/+3
Switch to use binman to pack images Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com>
2022-11-09imx: imx8qm: imx8qm_mek switch to binmanOliver Graute2-0/+3
Switch to use binman to pack images Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com>
2022-11-09imx: imx8qxp: imx8qxp_mek switch to binmanOliver Graute3-0/+136
Switch to use binman pack images Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-11-09imx: imx8qm: cgtqmx8: switch to binmanOliver Graute2-0/+2
Switch to use binman to pack images Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com> Reviewed-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-11-09imx: imx8qm-rom7720: switch to binmanOliver Graute3-0/+135
Switch to use binman to pack images Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com>
2022-11-09wandboard: Pass mmc aliasesFabio Estevam4-0/+12
Originally, the mmc aliases node was present in imx6qdl-wandboard.dtsi. After the sync with Linux in commit d0399a46e7cd ("imx6dl/imx6qdl: synchronise device trees with linux"), the aliases node is gone as the upstream version does not have it. This causes a regression in which the SD card cannot be found anymore: Since commit the aliases node has been removed U-Boot 2022.10-00999-gcca41ed3d63f-dirty (Nov 03 2022 - 22:07:38 -0300) CPU: Freescale i.MX6QP rev1.0 at 792 MHz Reset cause: POR DRAM: 2 GiB Core: 62 devices, 17 uclasses, devicetree: separate PMIC: PFUZE100 ID=0x10 MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... MMC: no card present *** Warning - No block device, using default environment Fix it by passing the alias node in the u-boot.dtsi file to restore the original behaviour where the SD card (esdhc3) was mapped to mmc0. Fixes: d0399a46e7cd ("imx6dl/imx6qdl: synchronise device trees with linux") Signed-off-by: Fabio Estevam <festevam@denx.de>
2022-11-08imx8mm: synchronise device tree with linuxMarcel Ziswiler11-58/+129
Synchronise device tree with linux v6.1-rc3. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-By: Tim Harvey <tharvey@gateworks.com> #imx8m{m,n,p}-venice-*
2022-11-08imx8mn: synchronise device tree with linuxMarcel Ziswiler5-18/+60
Synchronise device tree with linux v6.1-rc3. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-By: Tim Harvey <tharvey@gateworks.com> #imx8m{m,n,p}-venice-*
2022-11-08imx8mp: synchronise device tree with linuxMarcel Ziswiler10-196/+549
Synchronise device tree with linux v6.1-rc3. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-By: Tim Harvey <tharvey@gateworks.com> #imx8m{m,n,p}-venice-*
2022-11-08imx8mq: synchronise device tree with linuxMarcel Ziswiler6-41/+249
Synchronise device tree with linux v6.1-rc3. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-11-08imx8ulp: synchronise device tree with linuxMarcel Ziswiler4-601/+252
Synchronise device tree with linux v6.1-rc3. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-11-08imxrt1050: synchronise device tree with linuxMarcel Ziswiler4-342/+359
Synchronise device tree with linux v6.1-rc3. Note: Nowadays, the intent is for them regular device trees to just be synchronised from them Linux kernel device trees and any and all U-Boot specific changes need to go into the -u-boot.dtsi device tree include files which BTW get included automatically by the U-Boot build system. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-11-08imxrt1020: migrate to build system included -u-boot.dtsiMarcel Ziswiler2-4/+4
Migrate to using automatic build system included -u-boot.dtsi device tree include files. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Tested-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2022-11-08vf610: synchronise device tree with linuxMarcel Ziswiler1-1/+1
Synchronise device tree with linux v6.1-rc3. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-11-08mx6cuboxi: migrate to DM_SERIALBaruch Siach1-0/+16
Add the needed DT overrides to enable UART in SPL. Cc: Fabio Estevam <festevam@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Tested-by: Tom Rini <trini@konsulko.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-11-08arm: imx8mp: Initial MSC SM2S iMX8MP supportMartyn Welch4-0/+894
Add support for the MSC SM2S-IMX8PLUS SMARC Module. Tested in conjunction with the MSC SM2-MB-EP1 Mini-ITX Carrier Board. Signed-off-by: Martyn Welch <martyn.welch@collabora.com> Signed-off-by: Fabio Estevam <festevam@denx.de>
2022-11-07dm: sandbox: Switch over to using the new host uclassSimon Glass1-4/+0
Update the sandbox implementation to use UCLASS_HOST and adjust all the pieces to continue to work: - Update the 'host' command to use the new API - Replace various uses of UCLASS_ROOT with UCLASS_HOST - Disable test_eficonfig since it doesn't work (this should have a unit test to allow this to be debugged) - Update the blk test to use the new API - Drop the old header file Unfortunately it does not seem to be possible to split this change up further. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-11-07test: Add a way to detect a test that breaks anotherSimon Glass1-1/+1
When running unit tests, some may have side effects which cause a subsequent test to break. This can sometimes be seen when using 'ut dm' or similar. Add a new argument which allows a particular (failing) test to be run immediately after a certain number of tests have run. This allows the test causing the failure to be determined. Update the documentation also. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-11-07ARM: imx: imx8mp: Enable support for i2c5 and i2c6 on i.MX8MPMartyn Welch3-3/+19
The i.MX8MP SoC contains 2 more i2c buses. Add support for the configuration of these buses. Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
2022-11-07imx8m: USDHC3 base address definition for i.MX8MPMartyn Welch1-1/+1
The i.MX8MP also has USDHC3, allow access to the relvant base address definition. Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
2022-11-07imx: imx8mm-beacon: Enable USB booting via SDPAdam Ford1-1/+17
In order to boot over USB, the device tree needs to enable a few extra nodes in SPL. Since the USB driver has the ability to detect host/device, the dr_mode can be removed from the device tree since it needs to act as a device when booting and OTG is the default mode. Add USB boot support to spl_board_boot_device and enable the corresponding config options. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-11-07ARM: mx7: psci: fix suspend/resume e10133 workaroundMatthias Schiffer1-3/+6
The e10133 workaround was broken in two places: - The code intended to temporarily mask all interrupts in GPC_IMRx_CORE0. While the old register values were saved, the actual masking was missing. - imx_udelay() expects the system counter to run at its base frequency, but the system counter is switched to a lower frequency earlier in psci_system_suspend(), leading to a much longer delay than intended. Replace the call with an equivalent loop (linux-imx 5.15 does the same) This fixes the SoC hanging forever when there was already a wakeup IRQ pending while suspending. Fixes: 57b620255e ("imx: mx7: add system suspend/resume support") Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
2022-11-07configs: imx8m: Enable CONFIG_ARMV8_CRYPTO supportLoic Poulain1-0/+1
This enables armv8 crypto extension usage for SHA1/SHA256. Which speed up sha1/sha256 operations, about 10x faster with a imx8mm evk for a 20MiB kernel hash verification (12ms vs 165ms). Signed-off-by: Loic Poulain <loic.poulain@linaro.org> Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-11-07arm: mvebu: Add RD-AC5X boardChris Packham3-2/+139
The RD-AC5X-32G16HVG6HLG-A0 development board main components and features include: * Main 12V/54V power supply * 270 Gbps throughput packet processor on the main board * DDR4: * SR1: 2GB DDR4 2400MT/S(1GB x 2 pcs ) with ECC(1GB x 1 pcs) * SR2: 4GB DDR4 2400MT/S(2GB x 2 pcs ) with ECC(2GB x 1 pcs) * PCB co-layout with 4GB device to support 8GB (Dual CS) requirement * 16GB eMMC (Samsung KLMAG1JETD-B041006) * 16MB SPI NOR(GD25Q127C) * 32 x 1000 Base-T interfaces * 16 x 2500 Base-T interfaces * SR1: 88E2540*4 * SR2: 88E2580*1+88E2540*2 * Six (6) x 25G Base-R SFP28 interfaces * One (1) x RJ-45 console connector, interfacing to the on board UART * One (1) x USB Type-A connector, interfacing to the USB 2.0 port (0) * One (1) x USB Type-mini B connector, interfacing to the USB 2.0 port (1) * One (1) x RJ-45 1G Base-T Management port, interfacing to the host port (shared with PCIe) Connected to 88E1512 Gigabit Ethernet Phy * One (1) x Oculink port, interfacing to the PCIe port for external CPU connection * POE 802.3AT support on Port 1 ~ Port 32, 802.3BT support on Port 33 ~ Port 48 (Microsemi PD69208T4, PD69208M or TI TPS2388,TPS23881 solution) * POE total power budget 780W * LED interfaces per network port/POE * LED interfaces (common) showing system status * PTP TC mode Supported (Reserved M.2 connector to support BC mode) Signed-off-by: Chris Packham <judge.packham@gmail.com>
2022-11-07arm: mvebu: Support for 98DX25xx/98DX35xx SoCChris Packham10-0/+745
Add support for the Allecat5/Alleycat5X SoC. These are L3 switches with an integrated CPU (referred to as the CnM block in Marvell's documentation). These have dual ARMv8.2 CPUs (Cortex-A55). This support has been ported from Marvell's SDK which is based on a much older version of U-Boot. Signed-off-by: Chris Packham <judge.packham@gmail.com>
2022-11-07arm: mvebu: Don't use CONFIG_TIMER on ARM64Chris Packham1-1/+1
The 64-bit mvebu SoCs don't have a suitable timer driver so add a !ARM64 condition to the select. Fixes: 7b530bb19e ("arm: mvebu: Use CONFIG_TIMER on all MVEBU & KIRKWOOD platforms") Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2022-11-07arm: armada: dts: Add clock to armada-ap80x uart1Hamish Martin1-1/+1
The uart1 node was missing the 'clock-frequency' property. This meant the driver for this device would fail at probe. The clock for uart1 is fed from the same source as uart0 and is a fixed 200MHz clock. This is confirmed via documentation for the CN9130 SoC and from the equivalent code in Linux at: <linux>/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi where uart0 and uart1 share a common 'clocks' definition. Signed-off-by: Hamish Martin <hamish.martin@alliedtelesis.co.nz> Reviewed-by: Stefan Roese <sr@denx.de>
2022-11-03Merge tag 'mips-pull-2022-11-03' of ↵WIP/03Nov2022Tom Rini3-14/+20
https://source.denx.de/u-boot/custodians/u-boot-mips - MIPS: convert CONFIG_SYS_MIPS_TIMER_FREQ to Kconfig - MIPS: mtmips: fix incorrectly converted default value for CONFIG_SPL_PAD_TO
2022-11-03Merge branch '2022-11-02-assorted-updates'Tom Rini14-30/+70
- Improve arm semihosting, NPCM8xx pinctrl driver, SP804 uclass timer driver (and enable on relevant platforms), pvblock cleanup, eeprom cmd bugfix, add RTI watchdog nodes to k3-am64-main, evb-ast2500 config updates.
2022-11-03riscv: dts: Add QSPI NAND device nodePadmarao Begari1-0/+16
Add QSPI NAND device node to the Microchip PolarFire SoC Icicle kit device tree. The Winbond NAND flash memory can be connected to the Icicle Kit by using the Mikroe Flash 5 click board and the Pi 3 Click shield. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Rick Chen <rick@andestech.com>
2022-11-03riscv: dts: Update memory configurationPadmarao Begari1-58/+17
In the v2022.10 Icicle reference design, the seg registers have been changed, resulting in a required change to the memory map. A small 4MB reservation is made at the end of 32-bit DDR to provide some memory for the HSS to use, so that it can cache its payload between reboots of a specific context. Co-developed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Rick Chen <rick@andestech.com>
2022-11-03riscv: Rename Andes PLIC to PLICSWYu Chien Peter Lin9-28/+28
As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2022-11-02MIPS: convert CONFIG_SYS_MIPS_TIMER_FREQ to KconfigDaniel Schwierzeck1-0/+18
This converts the following to Kconfig: CONFIG_SYS_MIPS_TIMER_REQ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2022-11-02MIPS: remove CONFIG_SYS_MHZDaniel Schwierzeck2-6/+2
Resolve all uses of CONFIG_SYS_MHZ with the currently defined value. Remove code which depends on CONFIG_SYS_MHZ but where no board configs actually use that code. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2022-11-02MIPS: remove deprecated TARGET_VCT optionDaniel Schwierzeck1-8/+0
This board has been removed a long time ago. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2022-11-02arm: dts: ti: k3-am64-main: Add RTI watchdog nodesChristian Gmeiner2-0/+20
Add the needed bus mappings for the two main RTI memory ranges and the required device tree nodes in the main domain. Same as kernel commit 6dd8457dc20693e2ba9054c171499b22664fd4e7 Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
generated by cgit v1.1 at 2024-09-16 17:19:04 +0000