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2022-03-03Merge tag 'u-boot-at91-fixes-2022.04-a' of ↵WIP/03Mar2022Tom Rini1-6/+19
https://source.denx.de/u-boot/custodians/u-boot-at91 First set of u-boot-atmel fixes for the 2022.04 cycle: This fixes set includes only a single fix for the Ethernet on sama7g5ek board which is broken at the moment.
2022-03-03Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini1-119/+9
Update and fixes for sl28, lx2, pblimage generation for some powerpc products
2022-02-28arm: apple: Switch to fully dynamic mem layoutJanne Grunau1-0/+33
Support for Apple M1 Pro and Max will allow using a single binary for all M1 SoCs. The M1 Pro/Max have a different memory layout. The RAM start address is 0x100_0000_0000 instead of 0x8_0000_0000. Replace the hardcoded memory layout with dynamic initialized environment variables in board_late_init(). Tested on Mac Mini (2020) and Macbook Pro 14-inch (2021). Signed-off-by: Janne Grunau <j@jannau.net> Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
2022-02-28board: sl28: use fit image generatorMichael Walle1-119/+9
Simplify the binman config and fdt nodes by using the "@..-SEQ" substitutions and CONFIG_OF_LIST. Signed-off-by: Michael Walle <michael@walle.cc> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2022-02-23Merge https://gitlab.denx.de/u-boot/custodians/u-boot-usbTom Rini1-13/+0
- OMAP EHCI updates
2022-02-23usb: ehci-omap: Drop dead codeAdam Ford1-13/+0
omap_ehci_hcd_stop appears to be dead code, and omap_ehci_hcd_init is only called by the probe function, so it can be static to that function. Remove both from the header along with some additional checking for DM_USB. Signed-off-by: Adam Ford <aford173@gmail.com>
2022-02-22spl: x86: Correct the binman symbols for SPLSimon Glass1-1/+1
These symbols are incorrect, meaning that binman cannot find the associated entry. This leads to errors like: binman: Section '/binman/simple-bin': Symbol '_binman_spl_prop_size' in entry '/binman/simple-bin/u-boot-spl/u-boot-spl-nodtb': Entry 'spl' not found in list (mkimage,u-boot-spl-nodtb, u-boot-spl-bss-pad,u-boot-spl-dtb,u-boot-spl,u-boot-img,main-section) Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-02-21Merge branch '2022-02-21-platform-updates'WIP/21Feb2022Tom Rini8-105/+198
- Assorted updates / fixes for Apple, TI and Aspeed platforms
2022-02-21arm: dts: k3-j7200: Fix up MAIN R5FSS cluster mode back to Split-modeSuman Anna1-0/+4
The default U-Boot environment variables and design are all set up for the MAIN R5FSS cluster to be in Split-mode. This is the setting used when the dts nodes were originally added in v2021.01 U-Boot and the dt nodes are synched with the kernel binding property names in commit 468ec2f3ef8f ("remoteproc: k3_r5: Sync to upstreamed kernel DT property names") merged in v2021.04-rc2. The modes for the MAIN R5FSS cluster got switched back to LockStep mode by mistake in commit fa09b12dc5f6 ("arm: ti: k3: Resync dts files and bindings with Linux Kernel v5.14") in v2022.01-rc1. This throws the following warning messages when early-booting the cores using default env variables, k3_r5f_rproc r5f@5d00000: Invalid op: Trying to start secondary core 7 in lockstep mode Load Remote Processor 3 with data@addr=0x82000000 83148 bytes: Failed! Fix this by switching back both the clusters to the expected Split-mode. Make this mode change in the u-boot specific dtsi file to avoid such sync overrides in the future until the kernel dts is also switched to Split-mode by default. Fixes: fa09b12dc5f6 ("arm: ti: k3: Resync dts files and bindings with Linux Kernel v5.14") Signed-off-by: Suman Anna <s-anna@ti.com>
2022-02-21arm: omap3: Make some memory functions static and clean headersAdam Ford4-25/+18
There are a few memory functions for both the emif4 (AM3517) and sdrc (OMAP35/DM37) code that can be defined as static, because those functions are not used externally. Make them static and clean up some of the corresponding headers. Signed-off-by: Adam Ford <aford173@gmail.com>
2022-02-21arm: omap3: Cleanup sys_info to fit OMAP3 booting with LTOAdam Ford2-38/+5
With LTO enabled, some functions appear to be optimized in a way that causes hanging on some OMAP3 boards after some unrelated patches were applied. The solution appears to make several functions __used. There also appears be to be some dead code, so remove it while cleaning this up. This has been tested on a general purpose OMAP3530, DM3730, and AM3517. Signed-off-by: Adam Ford <aford173@gmail.com>
2022-02-21arm: dts: k3-j721e-r5-common-proc-board: tps659413: Correct the min/max ↵Keerthy1-3/+3
voltages of VDD_CPU Correct the min/max voltages of VDD_CPU. As per data sheet the VDD_CPU minimum voltage is .6V & maximum voltage is .9V. Correct the same. While at it fix the comment to reflect VDD_CPU instead of VDD_MPU. Data Sheet Link: https://www.ti.com/lit/gpn/dra829v Signed-off-by: Keerthy <j-keerthy@ti.com>
2022-02-21arm: apple: Add M1 Pro/Max supportMark Kettenis1-39/+168
Choose the memory map based on the compatible property from the device tree passed to us by m1n1. Since DRAM on the M1 Pro/Max starts at a different address avoid hardcoding the top of usable memory. Also make sure that the addresses entered into the memory map are page aligned such that we don't crash in dcache_enable(). Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Tested on: Macbook M1 Max Tested-by: Janne Grunau <j@jannau.net>
2022-02-21Merge tag 'xilinx-for-v2022.04-rc3' of ↵Tom Rini14-92/+48
https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2022.04-rc3 microblaze: - Fix exception handler zynqmp: - Show information about secure images - DT changes (som u-boot file removal) - Fix zynqmp_pm_cfg_obj_convert.py - Fix platform boot xilinx: - Fix bootm_size calculation - Remove GPIO_EXTRA_HEADER selection power: - Add zynqmp power management driver scsi: - Add phy support to ceva driver zynq qspi: - Fix unaligned accesses and check baudrate setup - Add support for spi memory operations net: - Fix 64bit calculation in axi_emac video: - Add missing gpio dependency for seps driver
2022-02-21arm64: zynqmp: Remove additional gpio header from dlc21Michal Simek1-1/+0
This header shouldn't be in this file and there is already pointer to dt-bindings/gpio/gpio.h. Fixes: d2d14383bae4 ("arm64: zynqmp: Add support for DLC21 (Smartlynq+) board") Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/266bc91073f1149f3f60b1c9c0ba509c48470e2e.1644911870.git.michal.simek@xilinx.com
2022-02-21arm64: zynqmp: Fix debug uart initializationMichal Simek3-1/+13
The commit 0dba45864b2a ("arm: Init the debug UART") calls debug_uart_init() from crt0.S but it won't work because SOC is not configured yet. That's why create board_debug_uart_init() which calls psu_init() via new psu_uboot_init() earlier before the first access to UART in SPL. In full U-Boot call psu_uboot_init() only when CONFIG_ZYNQMP_PSU_INIT_ENABLED is enabled. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/878dc2daaa8685346f889989fbfb98b2e44da7fb.1645104518.git.michal.simek@xilinx.com
2022-02-21ARM: zynq: Fix debug uart initializationMichal Simek2-6/+10
The commit 0dba45864b2a ("arm: Init the debug UART") calls debug_uart_init() from crt0.S but it won't work because SOC is not configured yet. That's why create board_debug_uart_init() which calls ps7_init() earlier before the first access to UART. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/18e67e02a0c7190839a1ef3a11f3fd6babcf34cc.1645104518.git.michal.simek@xilinx.com
2022-02-21arm64: zynqmp: Fix dependencies around ZYNQMP_PSU_INIT_ENABLEDMichal Simek1-0/+1
ZYNQMP_PSU_INIT_ENABLED is called only when BOARD_EARLY_INIT_F is defined that's why cover this dependency in Kconfig. board_early_init_f() is only part related to CONFIG_ZYNQMP_PSU_INIT_ENABLED which is disabled now that's why disable BOARD_EARLY_INIT_F and also build board_early_init_f() only when CONFIG_BOARD_EARLY_INIT_F is enabled. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/d89253ec1590cd513dcd4bfbedebae618bd6d605.1645104518.git.michal.simek@xilinx.com
2022-02-21arm64: zynqmp: Build psu_spl_init for SPL all the timeMichal Simek1-1/+1
ZYNQMP_PSU_INIT_ENABLED specifically saying that has connection to full U-Boot not SPL that's why build psu_spl_init for SPL all the time. Also disable ZYNQMP_PSU_INIT_ENABLED because it ends up in situation that psu_init() is called twice which is wrong. By default only SPL should call it. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/bf1e5d9a163f8853c7d951ad42965114ab0b1f50.1645104518.git.michal.simek@xilinx.com
2022-02-19ARM: imx: imx8mn-ddr4-evk: Add ethernet supportMarek Vasut1-0/+1
Add support for ethernet on the imx8mn-ddr4-evk. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
2022-02-19imx8m: Drop unused function env_get_offsetMichael Trimarchi1-15/+0
This function is used in nxp u-boot tree. Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-19board: gateworks: venice: add imx8mn-gw7902 supportTim Harvey6-0/+1321
The GW7902 is based on the i.MX 8M Mini / Nano SoC featuring: - LPDDR4 DRAM - eMMC FLASH - Gateworks System Controller - LTE CAT M1 modem - USB 2.0 HUB - M.2 Socket with USB2.0, PCIe, and dual-SIM - IMX8M FEC - PCIe based GbE - RS232/RS485/RS422 serial transceiver - GPS - CAN bus - WiFi / Bluetooth - MIPI header (DSI/CSI/GPIO/PWM/I2S) - PMIC To add support for the i.MX8M Nano GW7902: - Add imx8mn-venice dts/defconfig/include - Add imx8mn-gw7902 dts - Add imx8mn-2gb lpddr4 dram configs - Add misc support for IMX8M Nano SoC - rename imx8mm-venice.c to venice.c as it is no longer imx8mm specific - update README with differences for IMX8MN vs IMX8MM Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-19arm: imx8m: add support for Advantech RSB-3720Ying-Chun Liu (PaulLiu)2-0/+19
Add initial support for Advantech RSB-3720 board. The initial support includes: - MMC - eMMC - I2C - FEC - Serial console Signed-off-by: Darren Huang <darren.huang@advantech.com.tw> Signed-off-by: Kevin12.Chen <Kevin12.Chen@advantech.com.tw> Signed-off-by: Phill.Liu <Phill.Liu@advantech.com.tw> Signed-off-by: Tim Liang <tim.liang@advantech.com.tw> Signed-off-by: wei.zeng <wei.zeng@advantech.com.cn> Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> Cc: uboot-imx <uboot-imx@nxp.com> Cc: Peng Fan (OSS) <peng.fan@oss.nxp.com>
2022-02-18arm: dts: imx8mq: add MNT Reform 2Patrick Wildt3-0/+490
Device tree taken from Linux v5.16-rc5. Signed-off-by: Patrick Wildt <patrick@blueri.se> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-18imx: spl: Fix typo BMODE_EMI -> BMODE_EIMHarald Seiler2-7/+7
The interface for NOR/OneNAND is called "EIM" not "EMI". Fix this. Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-17Merge https://source.denx.de/u-boot/custodians/u-boot-marvellWIP/17Feb2022Tom Rini13-663/+1575
- a37xx: pci: Cleanup and minor fix for root port check (Pali) - pci: mvebu: Ensure that root port is always on root zero bus (Pali) - kwbimage: Fix dumping DATA registers for v0 images (Pali) - kwbimage: Support for parsing extended v0 format (Pali) - a37xx: Fix code and update DTS files to upstream version (Pali) - a37xx: Fix and extend building memory map (Pali) - ddr: marvell: a38x: fix BYTE_HOMOGENEOUS_SPLIT_OUT decision (Marek) - mvebu: Optionally reset board on DDR training failure (Marek)
2022-02-17arm: mvebu: spl: Add option to reset the board on DDR training failureMarek Behún2-1/+19
Some boards may occacionally fail DDR training. Currently we hang() in this case. Add an option that makes the board do an immediate reset in such a case, so that a new training is tried as soon as possible, instead of hanging and possibly waiting for watchdog to reset the board. (If the DDR training fails while booting the image via UART, we will still hang - it doesn't make sense to reset in such a case, because after reset the board will try booting from another medium, and the UART booting utility does not expect that.) Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-17arm: mvebu: a37xx: Fix comment with name of the functionPali Rohár1-1/+1
Function is named build_mem_map, not a3700_build_mem_map. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Marek Behún <marek.behun@nic.cz>
2022-02-17arm: mvebu: a37xx: Map CCI-400 and AP BootROM address spacePali Rohár1-1/+22
In function build_mem_map() prepare also mapping for CCI-400 and BootROM windows. BootROM window is 1 MB long and by default starts at address 0xfff00000. A53 AP BootROM is 16 kB long and repeats in this BootROM window 64 times. RVBAR_EL3 register is set to value 0xffff0000, so by default A53 AP BootROM is accessed via range 0xffff0000-0xffff3fff. CCI-400 window when new TF-A version is used, starts at address 0xfe000000 and when old TF-A version is used, starts at address 0xd8000000. Physical addresses are read directly from mvebu registers, so if TF-A remaps it in future (again) then it would not cause any issue for U-Boot. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-17arm: mvebu: a37xx: Fix calling build_mem_map()Pali Rohár1-2/+2
Function build_mem_map() modifies global variable mem_map. This variable is used by the get_page_table_size() function which is called by function arm_reserve_mmu() (as aliased macro PGTABLE_SIZE). Function arm_reserve_mmu() is called earlier than enable_caches() which calls build_mem_map(). So arm_reserve_mmu() does not calculate reserved memory correctly. Fix this issue by calling build_mem_map() from a3700_dram_init() which is called before arm_reserve_mmu(). Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Marek Behún <marek.behun@nic.cz>
2022-02-17arm: a37xx: Update DTS files to version from upstream Linux kernelPali Rohár8-633/+1494
This change updates all Armada 37xx DTS files to version which is used by Linux kernel v5.18. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-17arm: a37xx: espressobin: Explicitly enable eMMC node in -u-boot.dtsiPali Rohár1-0/+8
Official DT bindings for Espressobin have disabled eMMC node. As U-Boot requires to have this node enabled by default, do it in armada-3720-espressobin-u-boot.dtsi DTS file. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-17arm: a37xx: espressobin: Move U-Boot specific partitions node to -u-boot.dtsiPali Rohár2-18/+23
U-Boot specific changes should be in armada-3720-espressobin-u-boot.dtsi DTS file. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-17arm: a37xx: Update sdhci pointers to official DT bindingsPali Rohár6-9/+9
In Linux kernel version of armada-37xx.dtsi file sdhci1 pointer refers to sdhci@d0000 node and sdhci0 pointer to sdhci@d8000 node. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-17watchdog: armada_37xx: Convert to official DT bindingsPali Rohár1-2/+1
Official DT bindings have only one reg property: watchdog address space. Convert armada-37xx-wdt.c driver to offical DT bindings and access sel_reg register via MVEBU_REGISTER() macro, as its value (required by U-Boot driver) is not in DT yet. In later stage can be driver cleaned to not use it. This change would allow U-Boot to use A3720 watchdog DTS structure from Linux kernel. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-17usb: ehci: ehci-marvell: Update compatible string to official DT bindingsPali Rohár1-1/+1
Official DT bindings use compatible string marvell,armada-3700-ehci. Update drivers and DTS files. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-17phy: marvell: a3700: Update compatible string to official DT bindingsPali Rohár1-1/+1
In commit d368e1070514 ("phy: marvell: a3700: Convert to official DT bindings in COMPHY driver") was done update to official DT bindings but compatible string of official DT bindings was not updated. Fix it now. Fixes: d368e1070514 ("phy: marvell: a3700: Convert to official DT bindings in COMPHY driver") Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-16arm: dts: k3-j721e-r5-sk: Update R5 DT to pick the new DDR configSinthu Raja1-1/+1
A new lpddr4 configuration is introduced for J7 SK with 4266 MTs data rate. Therefore, update the R5 DTS file to point to the new DDR config file. Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
2022-02-16arm: dts: k3-j721e-sk: EMIF tool update to 0.6.1 with 4266MTs for lpddr4Sinthu Raja1-0/+2196
EMIF tool for J721E SK is now updated to 0.6.1 that includes * Updated write DQ training pattern to enable user pattern and clock pattern (from 0x7 to 0x6). * Updated IO drive strength to 40-80-80 Ohms. J721E SK uses the lpddr4 configuration of 4266 MTs data rate which is the same as J721E EVM but facing random failures. As the tool update is specific to the SK board, add a new lpddr4 config of 4266 MTs. Signed-off-by: Kevin Scholz <k-scholz@ti.com> Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
2022-02-16arm: dts: k3-j721e-r5-sk: Add initial R5 specific dts support for j721e-skSinthu Raja3-1/+679
Add R5 specific dts for J721E-SK Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
2022-02-16arm: dts: k3-j721e-sk: Add initial A72 specific dts supportSinthu Raja3-1/+1073
J721E Starter Kit (SK)[1] is a low cost, small form factor board designed for TI’s J721E SoC. TI’s J721E SoC comprises of dual core A72, high performance vision accelerators, video codec accelerators, latest C71x and C66x DSP, high bandwidth real-time IPs for capture and display, GPU, dedicated safety island and security accelerators. The SoC is power optimized to provide best in class performance for industrial and automotive applications. J721E SK supports the following interfaces: * 4 GB LPDDR4 RAM * x1 Gigabit Ethernet interface * x1 USB 3.0 Type-C port * x3 USB 3.0 Type-A ports * x1 PCIe M.2 E Key * x1 PCIe M.2 M Key * 512 Mbit OSPI flash * x2 CSI2 Camera interface (RPi and TI Camera connector) * 40-pin Raspberry Pi GPIO header Add A72 specific dts for J721E-SK. [1] https://www.ti.com/tool/SK-TDA4VM Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
2022-02-16arm: dts: k3-j721e-r5-common-proc-board: Do not use power-domains for I2CSinthu Raja1-0/+5
Board ID I2C EEPROM will be probed before SYSFW is available. So drop the power-domains property for wakup_i2c0 on which board ID EEPROM is connected. Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
2022-02-16arm: j721e: Add support for selecting DT based on board nameSinthu Raja1-0/+59
Enable support for selecting DTB from FIT within SPL based on the board name read from EEPROM. This will help to use single defconfig for both EVM and SK. Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
2022-02-15microblaze: exception: fix unaligned data access register maskOvidiu Panait1-1/+1
The correct mask for getting the source/destination register from ESR in the case of an unaligned access exception is 0x3E0. With this change, a dummy unaligned store produces the expected info: """ >> swi r5, r0, 0x111 ... Hardware exception at 0x111 address Unaligned data access exception Unaligned word access Unaligned store access Register R5 Return address from exception 0x7f99dfc ### ERROR ### Please RESET the board ### """ Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com> Link: https://lore.kernel.org/r/20220213080925.1548411-6-ovidiu.panait@windriver.com Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-02-15microblaze: exception: move unaligned access printfs inside switch caseOvidiu Panait1-3/+4
The unaligned access messages are only valid in the case of an unaligned data access exception. Do not print them for other types of hw exceptions. Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com> Link: https://lore.kernel.org/r/20220213080925.1548411-5-ovidiu.panait@windriver.com Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-02-15microblaze: exception: fix return address for delay slot exceptionsOvidiu Panait1-2/+10
According to the MicroBlaze reference manual (xilinx2021.2/ug984/page-37): """ If an exception is caused by an instruction in a delay slot (that is, ESR[DS]=1), the exception handler should return execution to the address stored in BTR instead of the normal exception return address stored in R17. """ Adjust the code to print the proper return address for delay slot exceptions. Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com> Link: https://lore.kernel.org/r/20220213080925.1548411-4-ovidiu.panait@windriver.com Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-02-15microblaze: exception: fix delay slot exception handlingOvidiu Panait1-5/+5
The switch statement in _hw_exception_handler() only covers the rightmost 5 bits that encode the exception cause: switch (state & 0x1f) { ... } For this reason, the "0x1000" case will never be reached, because the 13th bit was zeroed out. To fix this, move delay slot exception handling before the switch statement (delay slot (DS) bit in Exception Status Register is independent of the exception cause (EC)). Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com> Link: https://lore.kernel.org/r/20220213080925.1548411-3-ovidiu.panait@windriver.com Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-02-15microblaze: exception: migrate MICROBLAZE_V5 to KconfigOvidiu Panait1-1/+1
Also, rename it to XILINX_MICROBLAZE0_DELAY_SLOT_EXCEP, since it only covers delay slot exception support. Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com> Link: https://lore.kernel.org/r/20220213080925.1548411-2-ovidiu.panait@windriver.com Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-02-15microblaze: exception: move privileged instruction exception out of v5 ifdefOvidiu Panait1-1/+1
The privileged instruction exception seems to have been introduced in microblaze v7.00 along with MMU support, so having it wrapped in MICROBLAZE_v5 ifdefs seems incorrect. Move it out of the ifdef, since all recent microblaze versions support it. Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com> Link: https://lore.kernel.org/r/20220213080925.1548411-1-ovidiu.panait@windriver.com Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-02-15xilinx: Remove GPIO_EXTRA_HEADER selectionMichal Simek4-31/+0
Platform specific headers are empty that's why there is no need to include them. That's why remove them for Zynq/ZynqMP and Versal. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/625b1be0b813e2b9a5323c0529f9c567bfe13e75.1643960446.git.michal.simek@xilinx.com
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