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2022-02-14arm: pdu001: Fix dt to work with the current am33xx dtsi filesWIP/2022-02-14-assorted-fixesFelix Brack1-6/+14
The changes introduced with commit 6337d53fdf45 ("arm: dts: sync am33xx with Linux 5.9-rc7") prevent the PDU001 from operating correctly. This patch fixes the configuration of the pin multiplexer and uart3. Signed-off-by: Felix Brack <fb@ltec.ch>
2022-02-11acpi: Move acpi_write_tables() to a generic headerSimon Glass2-3/+1
This function is used by both x86 and sandbox. Put it in a common header file. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-02-10arm:dts:k3-am64-sk: EMIF tool update to 0.8.0 with 1333MTs for lpddr4Sinthu Raja1-14/+14
EMIF tool for AM64 SK is now updated to 0.8.0 that includes * disabled Write DQ training * improve CA ODT to 60 ohms The lpddr4 enabled with periodic WDQ training is causing periodic 26us stall. This makes the SoC stall without doing anything which leads to R5 interrupt latency in TCM memory. Due to this periodic training there are some outstanding CPU transactions waiting for the lpddr4 to complete. Hence, disable the periodic write DQ training during the non-initialization stage of lpddr4 which results in an approximate 1us stall. Also, update the lpddr4 config to improve CA ODT by 60 ohms The rationales are as follows: - PI_WDQLVL_EN: 2 Bits register field to support write DQ leveling, disable bit 1 that supports Write DQ during non-initialization to avoid ~26us stall during code execution. - MR11_DATA_F1/F2_x register fields value changed to 0x66 that changes the CA ODT from 48ohm to 60ohm to improve the eye margin on CA bus by increasing the signal swing. Signed-off-by: James Doublesin <doublesin@ti.com> Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
2022-02-10powerpc: mpc8xx: drop CONFIG_SYS_RESET_ADDRESSOvidiu Panait1-9/+2
There are no boards that define CONFIG_SYS_RESET_ADDRESS, so drop the associated mpc8xx code that checks for it. Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2022-02-10spi: apple: Add driver for Apple SPI controllerMark Kettenis1-0/+2
Add a driver for the SPI controller integrated on Apple SoCs. This is necessary to support the keyboard on Apple Silicon laopts since their keyboard uses an Apple-specific HID over SPI protocol. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested on: Macbook Air M1 Tested-by: Simon Glass <sjg@chromium.org>
2022-02-10power: domain: apple: Add reset supportMark Kettenis1-0/+1
The power management controller found on Apple SoCs als provides a way to reset all devices within a power domain. This is needed to cleanly shutdown the NVMe controller before we hand over control to the OS. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested on: Macbook Air M1 Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-02-10arm: apple: Add RTKit supportMark Kettenis3-0/+243
Most Apple IOPs run a firmware that is based on what Apple calls RTKit. RTKit implements a common mailbox protocol. This code provides an implementation of the AP side of this protocol, providing a function to initialize RTKit-based firmwares as well as a function to do a clean shutdown of this firmware. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested on: Macbook Air M1 Tested-by: Simon Glass <sjg@chromium.org>
2022-02-10arm: apple: Change SoC name from "m1" into "apple"Mark Kettenis2-1/+1
U-Boot is expected to support multiple generations of Apple SoCs in a single binary with a single defconfig. Therefore it makes more sense to set SYS_SOC to "apple". Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-02-10mailbox: apple: Add driver for Apple IOP mailboxMark Kettenis1-0/+1
This mailbox driver provides a communication channel with the Apple IOP controllers found on Apple SoCs. These IOP controllers are used to implement various functions such as the System Manegement Controller (SMC) and NVMe storage. It allows sending and receiving a 96-bit message over a single channel. The header file with the struct used for mailbox messages is taken straight from Linux. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Signed-off-by: Sven Peter <sven@svenpeter.dev> Reviewed-by: Simon Glass <sjg@chromium.org> Tested on: Macbook Air M1 Tested-by: Simon Glass <sjg@chromium.org>
2022-02-09acpi: Move MCFG implementation to common libMoritz Fischer4-65/+16
MCFG tables are used on multiple arches. Move to common ACPI lib. Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Moritz Fischer <moritzf@google.com> Reviewed-by: Simon Glass <sjg@chromium.org> Use sizeof(*mcfg) instead of sizeof(*header) Signed-off-by: Simon Glass <sjg@chromium.org>
2022-02-09arch: x86: lib: acpi_table: Fix MCFG entriesMoritz Fischer1-0/+2
Commit d953137526cc ("x86: Move SSDT table to a writer function") introduced a bug where the actual MCFG entries are no longer generated. Cc: Simon Glass <sjg@chromium.org> Fixes: d953137526cc ("x86: Move SSDT table to a writer function") Signed-off-by: Moritz Fischer <moritzf@google.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2022-02-09sandbox: fix build failure with musl and SDLHeinrich Schuchardt2-3/+15
sdl.c is compiled against the SDL library. Trying to redefine wchar_t with -fshort-wchar is not necessary and leads to build failures when compiling against musl. Cc: Milan P. Stanić <mps@arvanta.net> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-02-09dts: automatically build necessary .dtb filesRasmus Villemoes13-0/+26
When building for a custom board, it is quite common to maintain a private branch which include some defconfig and .dts files. But to hook up those .dts files requires modifying a file "belonging" to upstream U-Boot, the arch/*/dts/Makefile. Forward-porting that branch to a newer upstream then often results in a conflict which, while it is trivial to resolve by hand, makes it harder to have a CI do "try to build our board against latest upstream". The .config usually includes information on precisely what .dtb(s) are needed, so to avoid having to modify the Makefile, simply add the files in (SPL_)OF_LIST to dtb-y. A technicality is that (SPL_)OF_LIST is not always defined, so rework the Kconfig symbols so that (SPL_)OF_LIST is always defined (when (SPL_)OF_CONTROL), but only prompted for in the cases which used to be their "depends on". nios2 and microblaze already have something like this in their dts/Makefile, and the rationale in commit 41f59f68539 is similar to the above. So this simply generalizes existing practice. Followup patches could remove the logic in those two makefiles, just as there's potential for moving some common boilerplate from all the arch/*/dts/Makefile files to the new scripts/Makefile.dts. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-02-09Convert CONFIG_SCSI_AHCI_PLAT et al to KconfigSimon Glass2-4/+0
This converts the following to Kconfig: CONFIG_SCSI_AHCI_PLAT CONFIG_SYS_SCSI_MAX_SCSI_ID CONFIG_SYS_SCSI_MAX_LUN CONFIG_SYS_SATA_MAX_DEVICE Drop CONFIG_SCSI for everything except the sandbox build. We only need one build for tests. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-09scsi: Drop CONFIG_SYS_SCSI_MAX_DEVICESimon Glass1-2/+0
This is defined based on two other CONFIGs for all boards except sandbox and durian. For sandbox the value does not matter. For durian the value seems excessive. Drop the option completely, to simplify configuration and reduce the number of things we need to convert to Kconfig. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-09Convert CONFIG_SYS_IDE_MAXBUS et al to KconfigSimon Glass1-7/+0
This converts the following to Kconfig: CONFIG_SYS_IDE_MAXBUS CONFIG_SYS_IDE_MAXDEVICE CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ATA_STRIDE CONFIG_SYS_ATA_DATA_OFFSET CONFIG_SYS_ATA_REG_OFFSET CONFIG_SYS_ATA_ALT_OFFSET CONFIG_SYS_ATA_IDE0_OFFSET CONFIG_SYS_ATA_IDE1_OFFSET CONFIG_ATAPI CONFIG_IDE_RESET Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-08mips: Avoid using config_enabled() directlySimon Glass1-1/+1
Use IS_ENABLED() instead, which is the correct macro for checking a CONFIG option. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-02-08imx: Don't define __ASSEMBLY__ in source filesSimon Glass8-8/+1
This is supposed to be a build-system flag. Move it there so we can define it before linux/kconfig.h is included. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-02-08arm: dts: k3-j721e: Add support for multilink PCIe + QSGMIIAswath Govindraju3-5/+26
Add support for QSGMII multilink configuration. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08arm: dts: k3-j721e: Add support for PLL_CMNLC clocks in SerDes0Aswath Govindraju2-0/+34
The PLL_CMNLC clocks are modelled as a child clock device of seirra. In the function device_probe, the corresponding clocks are probed before calling the device's probe. The PLL_CMNLC mux clock can only be created after the device's probe. Therefore, move assigned-clocks and assigned-clock-parents to the link nodes in U-Boot device tree file. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08dts: am57xx*: Add ipu early boot DT changesKeerthy5-0/+35
Add support for ipu early boot. Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
2022-02-08arm: dts: dra7*/am57xx-idk-evm-u-boot: Add ipu early boot DT changesKeerthy5-0/+5
Add support for ipu early boot. Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
2022-02-08arm: dts: dra7: Add ipu and related nodesKeerthy1-1/+44
Add ipu and the associated nodes. Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
2022-02-08dts: dra7-ipu-common-early-boot.dtsi: Add all the ipu early boot related nodesKeerthy1-0/+113
Add all the ipu early boot related nodes Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
2022-02-08drivers: misc: Makefile: Enable fs_loader compilation at SPL LevelKeerthy1-7/+3
Enable fs_loader compilation at SPL Level. Signed-off-by: Keerthy <j-keerthy@ti.com> [Amjad: fix compilation failures for J721e platform] Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
2022-02-08arm: mach-omap2: load/start remoteproc IPU1/IPU2Keerthy6-7/+235
First check the presence of the ipu firmware in the boot partition. If present enable the ipu and the related clocks & then move on to load the firmware and eventually start remoteproc IPU1/IPU2. do_enable_clocks by default puts the clock domains into auto which does not work well with reset. Hence adding do_enable_ipu_clocks function. Signed-off-by: Keerthy <j-keerthy@ti.com> [Amjad: fix IPU1_LOAD_ADDR and compile warnings] Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
2022-02-08arm: dts: k3-j721s2-ddr: Add DDR supportAswath Govindraju3-0/+8829
J721S2 can support two instances for DDR. Therefore, add the device support for the same and use 4266MT/s as DDR frequency. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08arm: dts: k3-j721s2: Add r5 specific dt supportAswath Govindraju2-1/+198
Add initial support for device tree that runs on R5. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08arm: dts: Add support for A72 specific J721S2 Common Processor BoardAswath Govindraju3-0/+580
The EVM architecture for J721S2 is similar to that of J721E and J7200. It is as follows, +------------------------------------------------------+ | +-------------------------------------------+ | | | | | | | Add-on Card 1 Options | | | | | | | +-------------------------------------------+ | | | | | | +-------------------+ | | | | | | | SOM | | | +--------------+ | | | | | | | | | | | Add-on | +-------------------+ | | | Card 2 | | Power Supply | | Options | | | | | | | | | +--------------+ | <--- +------------------------------------------------------+ Common Processor Board Common Processor board is the baseboard that contains most of the actual connectors, power supply etc. The System on Module (SoM) is plugged on to the common processor baord. Therefore, add support for peripherals brought out in the common processor board. Link to Common Processor Board: https://www.ti.com/lit/zip/sprr439 Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08arm: dts: Add initial support for J721S2 System on ModuleAswath Govindraju1-0/+173
A System on Module (SoM) contains the SoC, PMIC, DDR and basic high speed components necessary for functionality. Therefore, add support for the components present on the SoM. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08arm: dts: Add initial support for J721S2 SoCAswath Govindraju3-0/+1406
The J721S2 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration in automotive ADAS applications and industrial applications requiring AI at the network edge. This SoC extends the Jacinto 7 family of SoCs with focus on lowering system costs and power while providing interfaces, memory architecture and compute performance for single and multi-sensor applications. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, three clusters of lockstep capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x floating point Vector DSP. * 3D GPU: Automotive grade IMG BXS-4-64 * Vision Processing Accelerator (VPAC) with image signal processor and Depth and Motion Processing Accelerator (DMPAC) * Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface. * Two Ethernet ports with RGMII support. * Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems, * Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller, QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. * Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL management. See J721S2 Technical Reference Manual (SPRUJ28 – NOVEMBER 2021) for further details: http://www.ti.com/lit/pdf/spruj28 Introduce basic support for the J721S2 SoC. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
2022-02-08arm: K3: Add basic support for J721S2 SoC definitionDavid Huang11-5/+971
Add basic support for J721S2 SoC definition Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Hari Nagalla <hnagalla@ti.com>
2022-02-07board: toradex: add verdin imx8m plus supportMarcel Ziswiler4-0/+780
This adds initial support for the Toradex Verdin iMX8M Plus Quad 4GB WB IT V1.0B module. They are strapped to boot from eFuses which are factory fused to properly boot from their on-module eMMC. U-Boot supports booting from the on-module eMMC only, SDP support is disabled for now due to missing i.MX 8M Plus USB support. Functionality wise the following is known to be working: - eMMC, 8-bit and 4-bit MMC/SD card slots - Ethernet both on-module eQoS and FEC (requires PHY on carrier board) - GPIOs - I2C Boot sequence is: SPL ---> ATF (TF-A) ---> U-boot proper ATF, U-boot proper and u-boot.dtb images are packed into a FIT image, loaded by SPL. Boot: U-Boot SPL 2022.04-rc1-00164-g21a0312611-dirty (Feb 07 2022 - 11:34:04 +0100) Quad die, dual rank failed, attempting dual die, single rank configuration. Normal Boot WDT: Started watchdog@30280000 with servicing (60s timeout) Trying to boot from BOOTROM Find img info 0x&48025a00, size 872 Need continue download 1024 Download 779264, Total size 780424 NOTICE: BL31: v2.2(release):rel_imx_5.4.70_2.3.2_rc1-5-g835a8f67b NOTICE: BL31: Built : 16:52:37, Aug 26 2021 U-Boot 2022.04-rc1-00164-g21a0312611-dirty (Feb 07 2022 - 11:34:04 +0100) CPU: Freescale i.MX8MP[8] rev1.1 at 1200 MHz Reset cause: POR DRAM: 8 GiB Core: 78 devices, 18 uclasses, devicetree: separate WDT: Started watchdog@30280000 with servicing (60s timeout) MMC: FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... OK In: serial Out: serial Err: serial Model: Toradex Verdin iMX8M Plus Quad 4GB Wi-Fi / BT IT V1.0B, Serial# 06817281 Carrier: Toradex Verdin Development Board V1.1A, Serial# 10807609 Setting variant to wifi Net: Hard-coding pdata->enetaddr eth1: ethernet@30be0000, eth0: ethernet@30bf0000 [PRIME] Hit any key to stop autoboot: 0 Verdin iMX8MP # Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-07arm64: zynqmp: Remove SOM *u-boot.dtsiMichal Simek2-42/+0
Disable mmc from u-boot.dtsi file because it was there only for kv260 board. With kr260 this is not needed because we will switch to full DT per board with SD/EMMC there too. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/3440d9f94361b4800658f313a5785f43ee84ecf3.1642590109.git.michal.simek@xilinx.com
2022-02-05board: kontron: pitx-imx8m: Add Kontron pitx-imx8m board supportHeiko Thiery4-1/+633
The Kontron pitx-imx8m is an NXP i.MX8MQ based board in the pITX form factor. Signed-off-by: Heiko Thiery <heiko.thiery@gmail.com>
2022-02-05mach-imx: iomux-v3: add a define for the SION bitAngus Ainslie1-0/+1
SION (Software Input On Field) - force the select mode input path Signed-off-by: Angus Ainslie <angus@akkea.ca>
2022-02-05arm: dts: imx8mq kernel dts updatesAngus Ainslie1-13/+190
Update to the 5.16 imx8mq dts files and dt bindings Changes since v1: Dropped rfkill.h that is not in linux mainline yet. Signed-off-by: Angus Ainslie <angus@akkea.ca> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-05mx6: crm_regs: drop BM_ANADIG_ANA_MISC0_REFTOP_VBGADJDario Binacchi1-1/+0
Commit 97c16dc8bf098 ("imx: mx6ull: update the REFTOP_VBGADJ setting") made this macro unused. Then remove it. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-05imx: mx6ull: fix REFTOP_VBGADJ settingDario Binacchi1-1/+3
The previous code wrote the contents of the fuse as is in the REFTOP_VBGADJ[2:0], but this was wrong if you consider the contents of the table in the code comment. This table is also different from the table in the commit description. But then, which of the two is correct? If it is assumed that an unprogrammed fuse has a value of 0 then for backward compatibility of the code REFTOP_VBGADJ[2:0] must be set to 6 (b'110). Therefore, the table in the code comment can be considered correct as well as this patch. Fixes: 97c16dc8bf098 ("imx: mx6ull: update the REFTOP_VBGADJ setting") Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-02-05arm64: dts: imx8mm: Add the pcie supportRichard Zhu1-1/+32
Add the PCIe support on i.MX8MM platforms. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Tim Harvey <tharvey@gateworks.com> Tested-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Marek Vasut <marex@denx.de> # Pick from Linux 854a4766ac12 ("arm64: dts: imx8mm: Add the pcie support")
2022-02-05arm64: dts: imx8mm: Add the pcie phy supportRichard Zhu1-0/+13
Add the PCIe PHY support on iMX8MM platforms. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Tim Harvey <tharvey@gateworks.com> Tested-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Marek Vasut <marex@denx.de> # Pick from Linux b9ec888f636f ("arm64: dts: imx8mm: Add the pcie phy support")
2022-02-05arm: dts: add imx8mp-rsb3720-a1 dts fileYing-Chun Liu (PaulLiu)2-0/+966
Add board dts for Advantech's imx8mp-rsb3720-a1 Signed-off-by: Darren Huang <darren.huang@advantech.com.tw> Signed-off-by: Kevin12.Chen <Kevin12.Chen@advantech.com.tw> Signed-off-by: Phill.Liu <Phill.Liu@advantech.com.tw> Signed-off-by: Tim Liang <tim.liang@advantech.com.tw> Signed-off-by: wei.zeng <wei.zeng@advantech.com.cn> Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> Cc: uboot-imx <uboot-imx@nxp.com>
2022-02-05arm64: dts: imx8mm: Add missing MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_BMarek Vasut1-0/+1
The i.MX8M Mini Application Processor Reference Manual, Rev. 3, 11/2020 documents AF MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B , add it into the pinmux tables. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-05arm64: dts: imx8mm/q: Fix pad control of SD1_DATA0Oliver Stäbler2-2/+2
Fix address of the pad control register (IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0) for SD1_DATA0_GPIO2_IO2. This seems to be a typo but it leads to an exception when pinctrl is applied due to wrong memory address access. Signed-off-by: Oliver Stäbler <oliver.staebler@bytesatwork.ch> Reviewed-by: Fabio Estevam <festevam@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Fixes: c1c9d41319c3 ("dt-bindings: imx: Add pinctrl binding doc for imx8mm") Fixes: 748f908cc882 ("arm64: add basic DTS for i.MX8MQ") Signed-off-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Marek Vasut <marex@denx.de> # Picked from Linux 5cfad4f45806f ("arm64: dts: imx8mm/q: Fix pad control of SD1_DATA0")
2022-02-05ARM: imx: imx8m: Add PLL 1.4 GHz, 1.5 GHz, 1.6 GHz, 1.8 GHz optionsMarek Vasut1-0/+20
Add PLL 1.4 GHz, 1.5 GHz, 1.6 GHz, 1.8 GHz options for iMX8M SoCs in case they should be operated faster, e.g. to improve boot time. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
2022-02-05ARM: imx: imx8m: Align PLL 1.2 GHz option with LinuxMarek Vasut1-3/+3
Linux uses slightly different divider settings for the 1.2 GHz PLL configuration, adjust the coefficients to match Linux. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
2022-02-05imx8m: lock id_swap_bypass bit in tzc380 enableAndrey Zhizhikin2-3/+18
According to TRM for i.MX8M Nano and Plus, GPR10 register contains lock bit for TZASC_ID_SWAP_BYPASS bit. This bit is required to be set in order to avoid AXI bus errors when GPU is enabled on the platform. TZASC_ID_SWAP_BYPASS bit is alread set for all imx8m applicable derivatives, but is missing a lock settings to be applied. Set the TZASC_ID_SWAP_BYPASS_LOCK bit for those derivatives which have it implemented. Since we're here, provide also names to bits from TRM instead of using BIT() macro in the code. Fixes: deca6cfbf5d7 ("imx8mn: set BYPASS ID SWAP to avoid AXI bus errors") Fixes: a07c7181296f ("imx8mp: set BYPASS ID SWAP to avoid AXI bus errors") Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> Cc: Peng Fan <peng.fan@nxp.com>
2022-02-05imx: imx8mm_beacon: Enable USBAdam Ford1-0/+4
With the updated device tree's having USB support, enable in U-Boot. This also requires the addition of the imx8m power domain, since the USB is gated by the power domain controller. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-05arm: dts: imx8mm-beacon: Resync dtsi with Kernel 5.17-rc1Adam Ford2-4/+39
Resync the SOM and baseboar files with the device trees that will be included in 5.17-RC1 when it's cut. This will improve pinmuxing for USDHC1 and add USB functionality. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-05imx8mn-ddr4-evk: generate single bootable imageAndrey Zhizhikin1-1/+18
As suggested in commit 028abfd9b157 ("imx8mm-evk: Generate a single bootable flash.bin again") for imx8mm_evk, it is possible to produce single bootable image via binman. This restores the original behavior in distros, where only one boot container is used to create target image. Perform similar adaptions in order to provide single bootable image for imx8mn-ddr4-evk derivate. Update documentation to drop additional step of copying u-boot.itb Fixes: 353dfe4b4359 ("imx8mn-ddr4-evk: switch to use binman") Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>