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2023-02-02Merge commit 'refs/pipelines/15015' of ↵WIP/02Feb2023Tom Rini10-64/+99
https://source.denx.de/u-boot/custodians/u-boot-tegra
2023-02-02ARM: tegra: include timer as default optionSvyatoslav Ryhel2-0/+5
Enable TIMER and TEGRA_TIMER for TEGRA_ARMV7_COMMON and TEGRA210. Additionally enable SPL_TIMER if build as SPL part and drop deprecated configs from common header. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-02ARM: tegra: remap clock_osc_freq for all Tegra familySvyatoslav Ryhel8-64/+94
Enum clock_osc_freq was designed to use only with T20. This patch remaps it to use additional frequencies, added in T30+ SoC while maintaining backwards compatibility with T20. Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30 Tested-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> # Surface RT T30 Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20 Tested-by: Agneli <poczt@protonmail.ch> # Toshiba AC100 T20 Tested-by: Thierry Reding <treding@nvidia.com> # T30, T124, T210 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-02Merge https://source.denx.de/u-boot/custodians/u-boot-riscvTom Rini5-15/+49
2023-02-02clk: renesas: Add and enable CPG reset driverMarek Vasut1-0/+3
Add trivial reset driver extension to the CPG clock driver. The change turns current CPG UCLASS_CLK driver instance into an UCLASS_NOP proxy driver, which in turn binds both generic rcar3_clk UCLASS_CLK clock driver as well as generic rcar_rst UCLASS_RESET reset driver to the CPG DT node. This way, any other drivers which use the 'reset' DT property can now obtain valid reset handle backed by a reset driver. The clock tables have been updated to represent the CPG driver and only implement the generic CPG proxy driver bind call, which binds the clock and reset drivers. The DM_RESET is now enabled for all R-Car Gen3 platforms. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02clk: renesas: r8a7796: Add R8A77961 CPG/MSSR supportHai Pham1-0/+1
Add support for the R-Car M3-W+ (R8A77961) SoC. R-Car M3-W+ is very similar to R-Car M3-W (R8A77960), which allows for both SoCs to share a driver. Based on Linux commit 2ba738d56db4 ("clk: renesas: r8a7796: Add R8A77961 CPG/MSSR support") Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02clk: renesas: Rename CLK_R8A7796 to CLK_R8A77960Hai Pham1-1/+1
Rename CONFIG_CLK_R8A7796 for R-Car M3-W (R8A77960) to CONFIG_CLK_R8A77960, to avoid confusion with R-Car M3-W+ (R8A77961), which will use CONFIG_CLK_R8A77961. Based on Linux commit 92d1ebae9abf ("clk: renesas: Rename CLK_R8A7796 to CLK_R8A77960") Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02pinctrl: renesas: r8a7796: Add R8A77961 PFC supportHai Pham1-0/+1
R-Car M3-W+ (R8A77961) is pin compatible with R-Car M3-W (R8A77960), which allows for both SoCs to share a driver. Based on Linux commit 708c69e9eacc ("pinctrl: sh-pfc: r8a7796: Add R8A77961 PFC support") and 74ce7a8044b0 ("pinctrl: renesas: r8a7796: Optimize pinctrl image size for R8A774A1") Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
2023-02-02pinctrl: renesas: Synchronize R8A77960 M3-W and R8A77961 M3-W+ PFC tables ↵Marek Vasut1-1/+1
with Linux 6.1.7 Synchronize R-Car R8A77960 M3-W and R8A77961 M3-W+ PFC tables with Linux 6.1.7, commit 21e996306a6afaae88295858de0ffb8955173a15 . Note that the Kconfig option name has been updated to match the Linux kernel Kconfig option name, from PINCTRL_PFC_R8A7796 to PINCTRL_PFC_R8A77960 . Also note that a new Kconfig option has been added to enable support for R8A77961 M3-W+ , the Kconfig option name is PINCTRL_PFC_R8A77961 . Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02pinctrl: renesas: Synchronize R8A7795 H3 PFC tables with Linux 6.1.7Marek Vasut1-1/+1
Synchronize R-Car R8A7795 H3 PFC tables with Linux 6.1.7, commit 21e996306a6afaae88295858de0ffb8955173a15 . Note that the Kconfig option name has been updated to match the Linux kernel Kconfig option name, from PINCTRL_PFC_R8A7795 to PINCTRL_PFC_R8A77951 . Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-02-02ARM: dts: rmobile: Synchronize DTs with Linux 6.1.7Marek Vasut58-2384/+6850
Synchronize R-Car device trees with Linux 6.1.7, commit 21e996306a6afaae88295858de0ffb8955173a15 . The following script has been used for the synchronization: $ for i in $(cd arch/arm/dts/ ; ls -1 r8a* | grep -v 'u-boot.dts' ; sed -n '/#include/ s@.*"\(.*\)"@\1@p' $(ls -1 r8a* | grep -v 'u-boot.dts')) ; do if [ -e /linux-2.6/arch/arm64/boot/dts/renesas/$i ] ; then cp /linux-2.6/arch/arm64/boot/dts/renesas/$i arch/arm/dts/ ; elif [ -e /linux-2.6/arch/arm/boot/dts/$i ] ; then cp /linux-2.6/arch/arm/boot/dts/$i arch/arm/dts/ else echo "NOT FOUND: $i" fi done $ git add $( ( cd arch/arm/dts/ ; ls -1 r8a* | grep -v 'u-boot.dts' ; sed -n '/#include/ s@.*"\(.*\)"@\1@p' $(ls -1 r8a* | grep -v 'u-boot.dts')) | tr " " "\n" | sed 's@^@arch/arm/dts/@g' ) Move the include/dt-bindings/{clk,clock}/versaclock.h header used by the renesas boards to match Linux 6.1.y as well. Keep arch/arm/dts/r8a774c0-u-boot.dtsi sdhi3 node as it is now used by the arch/arm/dts/r8a774c0-cat874.dts board. Pick s@spi-flash@flash@ change in arch/arm/dts/r8a779a0-falcon-u-boot.dts from "ARM: dts: Synchronize R-Car V3U DTs with Linux 5.18.3" . Adjust R8A77990 Ebisu CONFIG_SYS_MMC_ENV_DEV from 2 to 0 to reflect the card enumeration in ebisu.dtsi /aliases DT node . Adjust R8A7795 and R8A7796 ULCB CONFIG_SYS_MMC_ENV_DEV from 1 to 0 to reflect the card enumeration in ulcb.dtsi /aliases DT node . Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com> # r8a779a0-falcon-u-boot.dts Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> # r8a779a0-falcon-u-boot.dts
2023-02-01Merge tag 'fsl-qoriq-2023-2-1' of ↵Tom Rini2-1/+10
https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq make QSPI clock selection optional during SoC init for ls102xa Fix regulator name for ls2_sfp Update NXP RCW github repo
2023-02-01Merge tag 'u-boot-imx-20230201' of ↵Tom Rini54-98/+1624
https://gitlab.denx.de/u-boot/custodians/u-boot-imx For 2023.04 ----------- - several conversion to DM_SERIAL and DM_I2C - fixes for Toradex boards - PSCI CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/14965
2023-02-01riscv: memcpy: check src and dst before copyRick Chen1-0/+2
Add src and dst address checking, if they are the same address, just return and don't copy data anymore. Signed-off-by: Rick Chen <rick@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-02-01riscv: ax25: bypass malloc when spl fit boots from ramRick Chen2-0/+28
When fit image boots from ram, the payload will be prepared in the address of SPL_LOAD_FIT_ADDRESS. In spl fit generic flow, it will malloc another memory address and copy whole fit image to this malloc address. But it is un-necessary for booting from RAM. This patch improves this flow by declare the board_spl_fit_buffer_addr() to replace the original one. The larger image size (eq: Kernel Image 10~20MB), it can save more booting time. Signed-off-by: Rick Chen <rick@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-02-01riscv: ae350: Enable CCTL_SUENRick Chen1-7/+11
CCTL operations are available to Supervisor/User-mode software under the control of the mcache_ctl.CCTL_SUEN control bit. Enable it to support Supervisor(and User) CCTL operations. Signed-off-by: Rick Chen <rick@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-02-01riscv: cpu: check U-Mode before counteren writeNikita Shubin1-8/+8
The Priv ISA states: "In systems without U-mode, the mcounteren register should not exist." Check U-Mode is present in MISA before writing to counteren, otherwise we endup with Illegal Instruction exception on systems without U-Mode. Also make checking MISA default for M-Mode. Signed-off-by: Nikita Shubin <n.shubin@yadro.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-02-01armv7: ls102xa: make QSPI clock selection optional during SoC initMario Kicherer2-1/+10
To improve startup times when booting from QSPI flash, the QSPI frequency can be configured very early in the boot process [1] to reduce loading times of U-Boot itself. This patch adds an option to disable setting the frequency to a default value during SoC initialization. [1] https://www.nxp.com/docs/en/application-note/AN12279.pdf Signed-off-by: Mario Kicherer <dev@kicherer.org> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-01-31arm: dts: imx8mn-u-boot: use versioned ddr4 firmwareOleksandr Suvorov1-4/+4
NXP tested imx8mn-ddr4 with firmware version 201810 only. Use this version for all imx8mn targets with DRAM DDR4. Fixes: 93c4c0e4dd1 ("arm: dts: imx8mn-u-boot: Create common imx8mn-u-boot.dtsi") Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io> Reviewed-by: Fabio Estevam <festevam@denx.de>
2023-01-31imx8mq_pins: fix configuration for UART4 on ECSPI2 padsArnaud Ferraris1-1/+1
When routing UART4 using the ECSPI2 pads, register IOMUXC_UART4_RXD_SELECT_INPUT (offset 0x050C) should be changed only when dealing with RX, as its name suggests. Signed-off-by: Arnaud Ferraris <arnaud.ferraris@collabora.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
2023-01-31imx8: scu_api: sync sc_rm_is_pad_owned api changeYe Li1-1/+1
SCFW has fixed a overflow issue in sc_rm_is_pad_owned API. This requires u-boot to update API implementation, since it will cause compatible issue. Otherwise all pad checking will have problem and cause pad setting not continue. Due to the compatible issue, the new u-boot only works with new SCFW (API version: 1.21 and later). old scfw + old u-boot: API overflow issue old scfw + new u-boot, or new scfw + old u-boot: API compatible issue new scfw + new u-boot: Working Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by : Jason Liu <Jason.hui.liu@nxp.com> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2023-01-31engicam: imx6: migrate to DM_SERIALMichael Trimarchi2-0/+32
Add the needed DT overrides and configs to enable UART in SPL. Cc: Fabio Estevam <festevam@gmail.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
2023-01-31configs: imx8m: Prepare imx8m-beacon boards for HAB supportAdam Ford1-0/+6
In order to enable HAB, FSL_CAAM, ARCH_MISC_INIT and SPL_CRYPTO should be enabled in Kconfig like other i.MX8M boards. Signed-off-by: Adam Ford <aford173@gmail.com>
2023-01-31board: gateworks: venice: poll I2C lines to wait for GSC firmwareTim Harvey6-3/+45
In some situations the GSC firmware where the EEPROM containing the model and DRAM configuration may not be ready by the time the SoC is ready to talk to it over I2C. Instead of a hard delay, poll the I2C lines to wait until they are released to avoid the I2C drivers 'Arbitation lost' error message. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
2023-01-31arm: dts: imx8m*-venice-*: add I2C GPIO bus recovery supportTim Harvey7-25/+275
Add I2C GPIO bus recovery support by adding scl-gpios and sda-gpios for the various I2C busses on Gateworks Venice boards. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
2023-01-31arm64: dts: imx8m{m, n}-venice-gw7902: add gpio pins for new board revisionTim Harvey4-8/+40
Add gpio pins present on new board revision: * LTE modem support (imx8mm-gw7902 only) - lte_pwr# - lte_rst - lte_int * M2 power enable - m2_pwr_en * off-board 4.0V supply - vdd_4p0_en Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2023-01-31Merge tag 'u-boot-amlogic-20230131' of ↵Tom Rini16-1011/+1510
https://source.denx.de/u-boot/custodians/u-boot-amlogic - jethub j100: add rescue boot from microSD - move meson sm command to cmd/meson and add efusedump sub-command - switch dwc2 otg to DM for G12A, GXL & AXG - Add new boards: - Odroid Go Ultra - Odroid-N2L
2023-01-31ARM: arm: colibri-imx6ull-emmc: fix emmc accessMax Krummenacher1-1/+0
Synchronizing the device tree with linux introduced a regression. The U-Boot specific dtsi mustn't override the alias settings for the eMMC/SD interfaces. Without this U-Boot cannot access the eMMC and boot the kernel. Fixes: c21b61bff15 ("colibri-imx6ull/-emmc: synchronise device tree with linux") Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
2023-01-31arm: imx: imx8m: Add basic PSCI provider implementationMarek Vasut3-0/+297
Implement basic PSCI provider to let OS turn CPU cores off and on, power off and restart the system and determine PSCI version. This is sufficient to remove the need for the ATF BL31 blob altogether. To make use of this functionality, active the following Kconfig options: # CONFIG_PSCI_RESET is not set CONFIG_ARMV8_MULTIENTRY=y CONFIG_ARMV8_SET_SMPEN=y CONFIG_ARMV8_SPL_EXCEPTION_VECTORS=y CONFIG_ARMV8_EA_EL3_FIRST=y CONFIG_ARMV8_PSCI=y CONFIG_ARMV8_PSCI_CPUS_PER_CLUSTER=4 CONFIG_ARMV8_SECURE_BASE=0x970000 CONFIG_ARM_SMCCC=y CONFIG_SYS_HAS_ARMV8_SECURE_BASE=y Signed-off-by: Marek Vasut <marex@denx.de>
2023-01-31arm: imx: imx8m: Program CSU and TZASC if PSCI providerMarek Vasut2-0/+26
In case U-Boot is the PSCI provider, it is necessary to correctly program CSU and TZASC registers. Those are poorly documented, so push in the correct values. Signed-off-by: Marek Vasut <marex@denx.de>
2023-01-31arm: imx: imx8m: Define trampoline location if PSCI providerMarek Vasut1-0/+4
The common code used to bring up secondary cores requires a final jump location to be stored in some sort of memory location, define this memory location to be the start of OCRAM, since it is available. Signed-off-by: Marek Vasut <marex@denx.de>
2023-01-31arm: imx: imx8m: Map RAM as NS if PSCI providerMarek Vasut1-5/+11
In case U-Boot is a PSCI provider, map RAM explicitly as NS, otherwise secondary cores crash with SError when attempting to access RAM mapped as secure in EL2. Signed-off-by: Marek Vasut <marex@denx.de>
2023-01-31arm: imx: imx8m: Enable GICv3 support if PSCI providerMarek Vasut2-0/+4
In case U-Boot is a PSCI provider, enable GICv3 support as this is necessary to bring up secondary cores. Signed-off-by: Marek Vasut <marex@denx.de>
2023-01-31arm: imx: imx8m: Only use ROM pointers if not PSCI providerMarek Vasut1-4/+5
The ROM pointers are in fact populated by the ATF BL31 blob, in case U-Boot itself if the PSCI provider, there is no ATF BL31 blob, hence ignore the ROM pointers. Signed-off-by: Marek Vasut <marex@denx.de>
2023-01-31arm: dts: imx8m: Require ATF BL31 blob only if not PSCI providerMarek Vasut4-0/+16
In case U-Boot itself if the PSCI provider on i.MX8M, do not require the ATF BL31 blob, as at that point the blob is useless and would interfere with U-Boot operation. Signed-off-by: Marek Vasut <marex@denx.de>
2023-01-31arm: imx: Drop custom lowlevel_initMarek Vasut2-24/+0
The custom lowlevel_init implementation is no longer necessary, since it is responsible for routing and trapping SErrors in U-Boot in EL2, which is implemented in common code since commit: 6c7691edd55 ("armv8: Always unmask SErrors") Signed-off-by: Marek Vasut <marex@denx.de>
2023-01-31arm: psci: Fix RESET2 hookMarek Vasut3-2/+6
The RESET2 hook is a PSCI v1.1 functionality, rename the macro accordinly. Add missing handler for the RESET2 hook, so it can be implemented by U-Boot. Signed-off-by: Marek Vasut <marex@denx.de>
2023-01-31arm: psci: Add PSCI v1.1 macroMarek Vasut1-0/+1
Add macro representing the PSCI v1.1 . Signed-off-by: Marek Vasut <marex@denx.de>
2023-01-31imx6q-sabrelite: Re-add mmc aliasesDetlev Casanova1-0/+13
In commit d0399a46e7cda63c07e3eb8558bef84cfb068028, the device tree was synchronized from linux and the aliases were dropped. They need to be kept so that the mmc cards are in the right order. Without the aliases, u-boot reports: MMC: FSL_SDHC: 2, FSL_SDHC: 3 With the aliases, u-boot reports: MMC: FSL_SDHC: 0, FSL_SDHC: 1 The upstream linux device tree does not contain the same aliases than u-boot (It keeps the devices order with /dev/mmcblk2 and /dev/mmcblk3). Because this board has been using different aliases in u-boot and linux, a imx6q-sabrelite-u-boot.dtsi file is added to be automatically included in imx6q-sabrelite.dts. This way, linux and u-boot each keep their own aliases and there is no breakage on current installations. This should never be done for new boards as we want to keep linux and u-boot with the same aliases as much as possible. This patch is only necessary to avoid breaking existing setups. Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
2023-01-31imx: mx6sxsabreauto: select DM_SERIALPeng Fan1-0/+4
Select DM_SERIAL Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-01-31imx: mx6sllevk: select DM_SERIALPeng Fan1-0/+8
Select DM_SERIAL Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-01-31imx: mx6ull/z_14x14_evk: clean up UART iomuxPeng Fan2-0/+16
After DM_SERIAL, and set pinctrl_uart1 as pre-reloc, no need initialize iomux at board file. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-01-30ARM: dts: imx8ulp-evk: Fix iomuxc issueYe Li1-0/+1
The property fsl,mux_mask is deleted by commit ed7bda5 (imx8ulp: synchronise device tree with linux). This causes the pinctrl driver not work on 8ULP, so fail to print any log. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2023-01-30dts: imx8mp-rsb3720: modify configrations to load fip into memoryYing-Chun Liu (PaulLiu)1-6/+4
The changes of commit 6a21c695213b ("arm: dts: imx8mp: add of-list support to common imx8mp-u-boot.dtsi") breaks the loading of the fip. This commit fixes the break by modify the configuration properly. Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
2023-01-30dts: imx8mp: assign binman_configuration label to config-SEQYing-Chun Liu (PaulLiu)1-1/+1
assign a label for config-SEQ so that the board dts can modify the configuration more easily. Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
2023-01-30imx8mm-phg: Add board supportFabio Estevam5-0/+753
Add the board support for the i.MX8MM Cloos PHG board. This board uses a imx8mm-tqma8mqml SoM from TQ-Group. imx8mm-phg.dts and imx8mm-tqma8mqml.dtsi are taken directly from Linux 6.2-rc3. Signed-off-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
2023-01-30arm64: dts: imx8mm-kontron: Add RTC aliasesFrieder Schrempf2-2/+9
Add aliases for the RTCs on the board and on the SoC. This ensures that the primary RTC is always the one on the board that has a buffered supply and maximum accuracy. This is a direct port of the pending commit from linux-next. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org> Reviewed-by: Fabio Estevam <festevam@denx.de>
2023-01-30mx7: clock: Use 60MHz for the I2C clocksFabio Estevam1-1/+1
When an I2C clock is enabled inside enable_i2c_clk() the clock rate is configured as PLL_SYS_MAIN_120M_CLK / 2 = 60MHz. Currently, the I2C clock is retrieved from I2C1_CLK_ROOT, which may not be the one that was enabled. As there is no clock driver for the imx7d, it is better to return 60MHz for the I2C clock. This provides a workaround for the imx7d-pico board, where I2C4 is connected to the PMIC. With this change, it is possible to convert the imx7d-pico board to DM_I2C and DM_PMIC. Signed-off-by: Fabio Estevam <festevam@denx.de>
2023-01-30ARM: imx: bootaux: Fix LTO -Wlto-type-mismatchMarek Vasut4-2/+17
Commit 56c2dbdabab5 ("imx: bootaux: cleanup code") introduces the following LTO related warning: " arch/arm/mach-imx/imx_bootaux.c:24:31: warning: type of ‘hostmap’ does not match original declaration [-Wlto-type-mismatch] 24 | const __weak struct rproc_att hostmap[] = { }; | ^ arch/arm/mach-imx/imx8m/soc.c:1590:24: note: array types have different bounds 1590 | const struct rproc_att hostmap[] = { | ^ arch/arm/mach-imx/imx8m/soc.c:1590:24: note: ‘hostmap’ was previously declared here ../aarch64-linux-gnu/bin/ld: warning: u-boot has a LOAD segment with RWX permissions " This is because the weak empty array of structures "hostmap" is eventually replaced by non-empty array of structures with different number of elements. Fix this by avoiding weak variable size array, instead use a weak function which returns single pointer to the array. Fixes: 56c2dbdabab5 ("imx: bootaux: cleanup code") Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-01-30ARM: imx: bootaux: Fix macro misuseMarek Vasut1-4/+4
There are no CONFIG_{TOOLS_,SPL_,TPL_,}IMX8M macros, nor is there one for ARM64. Use plain IS_ENABLED(CONFIG_IMX8M) and IS_ENABLED(CONFIG_ARM64) to avoid expanding the {TOOLS_,SPL_,TPL_,} part. Fixes: 56c2dbdabab5 ("imx: bootaux: cleanup code") Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
generated by cgit v1.1 at 2024-09-08 09:14:39 +0000