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2015-01-13x86: coreboot: Configure pci memory regionsBin Meng1-2/+28
2015-01-13x86: Make chromebook_link the default board for corebootBin Meng3-219/+217
2015-01-13x86: coreboot: Move coreboot-specific defines from coreboot.h to KconfigBin Meng2-0/+17
2015-01-13x86: Hide ROM chip size when CONFIG_X86_RESET_VECTOR is not selectedBin Meng1-0/+2
2015-01-13x86: Move CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to KconfigBin Meng1-0/+9
2015-01-13x86: Allow a hardcoded TSC frequency provided by KconfigBin Meng2-2/+26
2015-01-13x86: coreboot: Set up timer base correctlyBin Meng1-13/+20
2015-01-13x86: fsp: Drop get_hob_type() and get_hob_length()Bin Meng5-44/+14
2015-01-13x86: Add an 'mtrr' command to list and adjust MTRRsSimon Glass2-0/+139
2015-01-13x86: ivybridge: Update microcode early in bootSimon Glass5-13/+40
2015-01-13x86: Disable CAR before relocation on platforms that need itSimon Glass1-0/+8
2015-01-13x86: ivybridge: Add a way to turn off the CARSimon Glass1-0/+46
2015-01-13x86: Commit the current MTRRs before relocationSimon Glass1-0/+8
2015-01-13x86: ivybridge: Request MTRRs for DRAM regionsSimon Glass1-0/+10
2015-01-13x86: ivybridge: Set up an MTRR for the video frame bufferSimon Glass1-0/+7
2015-01-13x86: Add support for MTRRsSimon Glass6-101/+187
2015-01-13x86: ivybridge: Drop support for ROM cachingSimon Glass1-25/+0
2015-01-13x86: Tidy up VESA mode numbersSimon Glass1-4/+7
2015-01-13x86: Use cache, don't clear the display in video BIOSSimon Glass1-3/+2
2015-01-13x86: ivybridge: Only run the Video BIOS when video is enabledSimon Glass1-1/+8
2015-01-13x86: Drop RAMTOP KconfigSimon Glass2-12/+0
2015-01-13x86: Correct XIP_ROM_SIZESimon Glass1-1/+1
2015-01-13x86: crownbay: Add pci devices in the dts fileBin Meng1-0/+81
2015-01-13x86: Use ePAPR defined properties for x86-uartBin Meng1-3/+2
2015-01-12x86: Simplify the fsp hob access functionsBin Meng5-100/+101
2015-01-12pci: Make pci apis usable before relocationBin Meng3-6/+5
2015-01-12x86: Support pci bus scan in the early phaseBin Meng1-0/+1
2015-01-12x86: Add missing DECLARE_GLOBAL_DATA_PTR for pci.cBin Meng1-0/+2
2015-01-12x86: Clean up the board dts filesBin Meng3-24/+7
2015-01-12x86: Rename coreboot.dsti to serial.dtsiBin Meng3-2/+2
2015-01-12x86: Remove alex.dts in arch/x86/dtsBin Meng2-25/+0
2014-12-18x86: Clean up the FSP support codesBin Meng13-290/+279
2014-12-18x86: Rename coreboot-serial to x86-serialBin Meng1-1/+1
2014-12-18x86: crownbay: Add SDHCI supportBin Meng2-1/+48
2014-12-18x86: crownbay: Add SPI flash supportBin Meng2-1/+40
2014-12-18x86: Use consistent name XXX_ADDR for binary blob flash addressBin Meng4-5/+5
2014-12-18x86: Add queensbay and crownbay Kconfig filesBin Meng2-0/+92
2014-12-18x86: Enable the queensbay cpu directory buildBin Meng1-0/+1
2014-12-18x86: ich6-gpio: Add Intel Tunnel Creek GPIO supportBin Meng2-2/+15
2014-12-18x86: Convert microcode format to device-tree-onlySimon Glass2-7/+11
2014-12-18x86: Add basic support to queensbay platform and crownbay boardBin Meng6-0/+326
2014-12-18x86: Integrate Tunnel Creek processor microcodeBin Meng1-0/+368
2014-12-18x86: Correct problems in the microcode loadingSimon Glass1-10/+15
2014-12-18x86: ivybridge: Update the microcodeSimon Glass6-1374/+1504
2014-12-18x86: Move microcode updates into a separate directorySimon Glass3-2/+2
2014-12-15x86: move arch-specific asmlinkage to <asm/linkage.h>Masahiro Yamada5-1/+11
2014-12-13x86: Add a simple command to show FSP HOB informationBin Meng2-0/+68
2014-12-13x86: Support Intel FSP initialization path in start.SBin Meng3-0/+20
2014-12-13x86: Add post failure codes for bist and carBin Meng2-0/+3
2014-12-13x86: queensbay: Adapt FSP support codesBin Meng3-18/+28
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