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2014-12-15x86: move arch-specific asmlinkage to <asm/linkage.h>Masahiro Yamada5-1/+11
Commit 65dd74a674d6 (x86: ivybridge: Implement SDRAM init) introduced x86-specific asmlinkage into arch/x86/include/asm/config.h. Commit ed0a2fbf14f7 (x86: Add a definition of asmlinkage) added the same macro define again, this time, into include/common.h. (Please do not add arch-specific stuff to include/common.h any more; it is already too cluttered.) The generic asmlinkage is defined in <linux/linkage.h>. If you want to override it with an arch-specific one, the best way is to add it to <asm/linkage.h> like Linux Kernel. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2014-12-13x86: Add a simple command to show FSP HOB informationBin Meng2-0/+68
FSP builds a series of data structures called the Hand-Off-Blocks (HOBs) as it progresses through initializing the silicon. These data structures conform to the HOB format as described in the Platform Initialization (PI) specification Volume 3 Shared Architectual Elements specification, which is part of the UEFI specification. Create a simple command to parse the HOB list to display the HOB address, type and length in bytes. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2014-12-13x86: Support Intel FSP initialization path in start.SBin Meng3-0/+20
Per Intel FSP architecture specification, FSP provides 3 routines for bootloader to call. The first one is the TempRamInit (aka Cache-As-Ram initialization) and the second one is the FspInit which does the memory bring up (like MRC for other x86 targets) and chipset initialization. Those two routines have to be called before U-Boot jumping to board_init_f in start.S. The FspInit() will return several memory blocks called Hand Off Blocks (HOBs) whose format is described in Platform Initialization (PI) specification (part of the UEFI specication) to the bootloader. Save this HOB address to the U-Boot global data for later use. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2014-12-13x86: Add post failure codes for bist and carBin Meng2-0/+3
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2014-12-13x86: queensbay: Adapt FSP support codesBin Meng3-18/+28
Use inline assembly codes to call FspNotify() to make sure parameters are passed on the stack as required by the FSP calling convention. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2014-12-13x86: Initial import from Intel FSP release for Queensbay platformBin Meng12-0/+1522
This is the initial import from Intel FSP release for Queensbay platform (Tunnel Creek processor and Topcliff Platform Controller Hub), which can be downloaded from Intel website. For more details, check http://www.intel.com/fsp. Note: U-Boot coding convention was applied to these codes, so it looks completely different from the original Intel release. Also update FSP support codes license header to use SPDX ID. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2014-12-13x86: Add a simple superio driver for SMSC LPC47MBin Meng1-0/+90
On most x86 boards, the legacy serial ports (io address 0x3f8/0x2f8) are provided by a superio chip connected to the LPC bus. We must program the superio chip so that serial ports are available for us. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2014-12-13x86: Add Intel Crown Bay board dts fileBin Meng2-1/+55
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2014-12-13x86: ich6-gpio: Move setup_pch_gpios() to board support codesBin Meng3-0/+7
Movie setup_pch_gpios() in the ich6-gpio driver to the board support codes, so that the driver does not need to know any platform specific stuff (ie: include the platform specifc chipset header file). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2014-12-13x86: Clean up asm-offsetsBin Meng2-2/+3
Move GD_BIST from lib/asm-offsets.c to arch/x86/lib/asm-offsets.c as it is x86 arch specific stuff. Also remove GENERATED_GD_RELOC_OFF which is not referenced anymore. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2014-12-13x86: Make ROM_SIZE configurable in KconfigBin Meng1-1/+77
Currently the ROM_SIZE is hardcoded to 8MB in arch/x86/Kconfig. This will not be the case when adding additional board support. Hence we make ROM_SIZE configurable (512KB/1MB/2MB/4MB/8MB/16MB) and have the board Kconfig file select the default ROM_SIZE. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2014-12-08Replace <compiler.h> with <linux/compiler.h>Masahiro Yamada5-6/+7
Including <linux/compiler.h> is enough for general use. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-08Kbuild: introduce Makefile in arch/$ARCH/Daniel Schwierzeck1-0/+12
Introduce a Makefile under arch/$ARCH/ and include it in the top Makefile (similar to Linux kernel). This allows further refactoringi like moving architecture-specific code out of global makefiles, deprecating config variables (CPU, CPUDIR, SOC) or deprecating arch/$ARCH/config.mk. In contrary to Linux kernel, U-Boot defines the ARCH variable by Kconfig, thus the arch Makefile can only included conditionally after the top config.mk. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-11-25x86: dts: Add video information to the device treeSimon Glass1-0/+13
This provides panel timing information needed by the video driver. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25x86: Add initial video device init for Intel GMASimon Glass5-1/+927
Intel's Graphics Media Accelerator (GMA) is a generic name for a wide range of video devices. Add code to set up the hardware on ivybridge. Part of the init happens in native code, part of it happens in a 16-bit option ROM for those nostalgic for the 1970s. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25x86: Add support for running option ROMs nativelySimon Glass5-0/+946
On x86 machines we can use an emulator to run option ROMS as with other architectures. But with some additional effort (mostly due to the 16-bit nature of option ROMs) we can run them natively. Add support for this. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25x86: Add vesa mode configuration optionsSimon Glass1-0/+149
Add Kconfig options to allow selection of a vesa mode on x86 machines. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25x86: Add GDT descriptors for option ROMsSimon Glass2-22/+18
Option ROMs require a few additional descriptors. Add these, and remove the enum since we now have to access several descriptors from assembler. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25x86: ivybridge: Add northbridge init functionsSimon Glass5-1/+207
Add init for the northbridge, another part of the platform controller hub. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25x86: Drop some msr functions that we don't supportSimon Glass1-11/+0
These are not available in U-Boot as yet, so drop them. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25x86: Add init for model 206AX CPUSimon Glass5-0/+526
Add the setup code for the CPU so that it can be used at full speed. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25x86: Add LAPIC setup codeSimon Glass4-2/+181
Add code to set up the Local Advanced Peripheral Interrupt Controller. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-25x86: Drop old CONFIG_INTEL_CORE_ARCH codeSimon Glass1-28/+0
This is no-longer used, so drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-25x86: Refactor interrupt_init()Bin Meng3-14/+23
Rename interrupt_init() in arch/x86/lib/pcat_interrupts.c to i8259_init() and create a new interrupt_init() in arch/x86/cpu/interrupt.c to call i8259_init() followed by a call to cpu_init_interrupts(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2014-11-25x86: Remove cpu_init_r() for x86Bin Meng2-8/+0
Since cpu_init_interrupts() was moved out of cpu_init_r(), it is useless to keep cpu_init_r() for x86, thus remove it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2014-11-25x86: Call cpu_init_interrupts() from interrupt_init()Bin Meng2-2/+3
Currently cpu_init_interrupts() is called from cpu_init_r() to setup the interrupt and exception of the cpu core, but at that time the i8259 has not been initialized to mask all the irqs and remap the master i8259 interrupt vector base, so the whole system is at risk of being interrupted, and if interrupted, wrong interrupt/exception message is shown. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2014-11-25x86: Add Intel speedstep and turbo mode codeSimon Glass4-0/+219
Intel chips have a turbo mode where they can run faster for a short period until they reach thermal limits. Add code to adjust and query this feature. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25x86: ivybridge: Set up XHCI USBSimon Glass3-0/+34
Add init for XHCI so that high-speed USB can be used. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25x86: ivybridge: Set up EHCI USBSimon Glass4-0/+33
Add init for EHCI so that USB can be used. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25x86: dts: Add SATA settings for linkSimon Glass1-0/+7
Add the requires settings to enable SATA on link. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25x86: ivybridge: Add SATA initSimon Glass5-0/+306
Add code to set up the SATA interfaces on boot. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25x86: dts: Add LPC settings for linkSimon Glass1-0/+8
Add some settings required to set up the LPC correctly. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25x86: dts: Move PCI peripherals into a pci nodeSimon Glass1-13/+15
These peripherals should not be at the top level, since they exist inside the PCI bus. We don't have a full device tree node for pci yet, but we should at least put it at the right level. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25x86: ivybridge: Add additional LPC initSimon Glass2-1/+528
Set up all the remaining pieces of the LPC (low-pin-count) peripheral in PCH (Peripheral Controller Hub). Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25x86: ivybridge: Add PCH initSimon Glass3-0/+173
Add required init for the Intel Platform Controller Hub in ivybridge. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25x86: Add a simple header file for ACPISimon Glass1-0/+24
We don't use many features yet, so this only has a few declarations. It will be expanded as needed. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25x86: ivybridge: Add support for BD82x6x PCHSimon Glass5-0/+167
Add basic setup for the PCH. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25x86: Set up edge triggering on interrupt 9Simon Glass2-0/+49
Add this additional init in case it is needed by the OS. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-25x86: pci: Add handlers before and after a PCI hose scanSimon Glass2-0/+15
Some boards will want to do some setup before and after a PCI hose is scanned. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-25x86: Add ioapic.h headerSimon Glass1-0/+38
Add definitions for the I/O Advanced Peripheral Interrupt Controller. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25x86: Factor out common values in the link scriptSimon Glass2-7/+12
Define the reset base in config.mk so that it does not need to be calculated twice in the link script. Also tidy up the START_16 and RESET_VEC_LOC values to fit with this new approach. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-25x86: Ensure that all relocation data is included in the imageSimon Glass1-1/+3
Some toolchains put the relocation data into separate sections. Adjust the linker script to catch this case. Without relocation data, U-Boot will not boot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-25x86: Panic if there is no relocation dataSimon Glass1-0/+3
This normally indicates a problem which will prevent relocation from functioning, resulting in a hang. Panic in this case to make it easier to debug. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-25x86: Remove board_early_init_r()Simon Glass1-11/+0
This function is not needed. Remove it to improve the generic init sequence slightly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-25x86: Add ivybridge directory to MakefileSimon Glass1-0/+2
It is now required to add subdirectories in the x86 cpu Makefile. Add this to fix a build breakage for chromebook_link. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-24Merge git://git.denx.de/u-boot-x86Tom Rini57-175/+6391
Conflicts: arch/x86/cpu/Makefile Signed-off-by: Tom Rini <trini@ti.com>
2014-11-23x86: use CONFIG_SYS_COREBOOT to descend into coreboot/ directoryMasahiro Yamada2-7/+7
The references of CONFIG_SYS_COREBOOT in arch/x86/cpu/coreboot/Makefile are redundant because the build system descends into the directory only when CONFIG_SYS_COREBOOT is defined. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
2014-11-23kbuild: Descend into SOC directory from CPU directoryMasahiro Yamada1-0/+2
Some CPUs of some architectures have SOC directories. At present, the build system directly descends into SOC directories from the top Makefile, but it should generally descend into each directory from its parent directory. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-11-23linux/kernel.h: sync min, max, min3, max3 macros with LinuxMasahiro Yamada2-2/+2
U-Boot has never cared about the type when we get max/min of two values, but Linux Kernel does. This commit gets min, max, min3, max3 macros synced with the kernel introducing type checks. Many of references of those macros must be fixed to suppress warnings. We have two options: - Use min, max, min3, max3 only when the arguments have the same type (or add casts to the arguments) - Use min_t/max_t instead with the appropriate type for the first argument Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Pavel Machek <pavel@denx.de> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> [trini: Fixup arch/blackfin/lib/string.c] Signed-off-by: Tom Rini <trini@ti.com>
2014-11-21x86: Rename chromebook-x86 to corebootSimon Glass1-1/+1
Rename this vendor since it is intended to be used on any platform where coreboot runs at reset and then loads U-Boot. So far it is only tested on link. When other boards are supported it is likely that we will need to move to multiple board names, all under the 'coreboot' vendor. So while it would be possible to remove the vendor for now, that would be short-sighted. Suggested-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-07-14 07:14:27 +0000