aboutsummaryrefslogtreecommitdiff
path: root/arch/x86/cpu/queensbay/tnc.c
AgeCommit message (Collapse)AuthorFilesLines
2021-08-03x86: queensbay: Return directly if IGD / SDVO were already disabledBin Meng1-11/+9
Initialize 'igd' and 'sdvo' to NULL so that we just need to test them against NULL later, to be compatible with that case that IGD and SDVO devices were already in disabled state. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop init.h from common headerSimon Glass1-0/+1
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2019-10-08x86: Rename existing FSP code to fsp1Simon Glass1-1/+1
Since there is now a new version of the FSP and it is incompatible with the existing version, move the code into an fsp1 directory. This will allow us to put FSP v2 code into an fsp2 directory. Add a Kconfig which defines which version is in use. Some of the code in this new fsp1/ directory is generic across both FSPv1 and FSPv2. Future patches will address this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2018-06-13x86: irq: Remove chipset specific irq router driversBin Meng1-0/+39
At present there are 3 irq router drivers. One is the common one and the other two are chipset specific for queensbay and quark. However these are really the same drivers as the core logic is the same. The two chipset specific drivers configure some registers that are outside the irq router block which should really be part of the chipset initialization. Now we remove these specific drivers and make all x86 boards use the common one. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-07SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini1-2/+1
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2017-04-04dm: core: Add flags parameter to device_remove()Stefan Roese1-2/+2
This patch adds the flags parameter to device_remove() and changes all calls to this function to provide the default value of DM_REMOVE_NORMAL for "normal" device removal. This is in preparation for the driver specific pre-OS (e.g. DMA cancelling) remove support. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
2016-09-23x86: squash lines for immediate returnMasahiro Yamada1-7/+1
arch_cpu_init() can be simpler by this refactoring. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-02-05x86: tnc: Remove IGD and SDVO devices from driver modelBin Meng1-0/+36
With recent DM PCI changes to vesa_fb driver, external graphics card does not work any more. This is because: after setting the function disable bit, IGD and SDVO devices will disappear in the PCI configuration space. This however creates an inconsistent state from a driver model PCI controller point of view, as these two PCI devices are still attached to its parent's child device list as maintained by the driver model. Some driver model PCI APIs like dm_pci_find_class() used in the vesa_fb driver, are referring to the list to speed up the finding process instead of re-enumerating the whole PCI bus, so it gets the stale cached data which is wrong. To fix this, manually remove these two devices. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05x86: tnc: Use DM PCI API in disable_igd()Bin Meng1-3/+19
Once we get udevice of IGD and SDVO, we can use its udevice to access PCI configuration space with dm_pci_write_config32(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05x86: tnc: Change disable_igd() to have a return valueBin Meng1-3/+7
So far disable_igd() does not have any return value, but we may need that in the future. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05x86: tnc: Drop unprotect_spi_flash()Bin Meng1-16/+0
Unprotecting SPI flash is now handled in the SPI controller driver, via a call to the PCH driver. Drop the ad-hoc version. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-01-24dm: x86: queensbay: Add an interrupt driverSimon Glass1-37/+0
Add a driver for interrupts on queensbay and move the code currently in cpu_irq_init() into its probe() method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24dm: x86: Set up interrupt routing from interrupt_init()Simon Glass1-1/+1
At present interrupt routing is set up from arch_misc_init(). We can do it a little later instead, in interrupt_init(). This removes the manual pirq_init() call. Where the platform does not have an interrupt router defined in its device tree, no error is generated. Some platforms do not have this. Drop pirq_init() since it is no-longer used. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-12-01x86: Convert to use driver model timerBin Meng1-3/+0
Convert all x86 boards to use driver model tsc timer. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-11-13x86: queensbay: Really disable IGDBin Meng1-6/+20
According to Atom E6xx datasheet, setting VGA Disable (bit17) of Graphics Controller register (offset 0x50) prevents IGD (D2:F0) from reporting itself as a VGA display controller class in the PCI configuration space, and should also prevent it from responding to VGA legacy memory range and I/O addresses. However test result shows that with just VGA Disable bit set and a PCIe graphics card connected to one of the PCIe controllers on the E6xx, accessing the VGA legacy space still causes system hang. After a number of attempts, it turns out besides VGA Disable bit, the SDVO (D3:F0) device should be disabled to make it work. To simplify, use the Function Disable register (offset 0xc4) to disable both IGD (D2:F0) and SDVO (D3:F0) devices. Now these two devices will be completely disabled (invisible in the PCI configuration space) unless a system reset is performed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21x86: Allow disabling IGD on Intel QueensbayBin Meng1-0/+19
Add a Kconfig option to disable the Integrated Graphics Device (IGD) so that it does not show in the PCI configuration space as a VGA disaplay controller. This gives a chance for U-Boot to run PCI/PCIe based graphics card's VGA BIOS and use that for the graphics console. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-08-26x86: queensbay: Move unprotect_spi_flash() to arch_misc_init()Bin Meng1-2/+2
With dm pci conversion, pci config read/write in unprotect_spi_flash() silently fails as at that time dm pci is not ready and bus enumeration is not done yet. Actually we don't need to do this in that early phase, hence we delay this call to arch_misc_init(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-08-14x86: Allow pirq_init() to return an errorSimon Glass1-3/+1
This function can fail. In this case we should return the error rather than swallowing it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-07-28x86: Convert to use driver model pci on queensbay/crownbayBin Meng1-5/+0
Move to driver model pci for Intel queensbay/crownbay. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-07-14x86: queensbay: Change PCIe root ports' interrupt routingBin Meng1-6/+7
So far interrupt routing works pretty well for any on-chip devices on Intel Crown Bay. When inserting any PCIe card to any PCIe slot, Linux kernel is smart enough to do interrupt swizzling and figure out device's irq using its parent bridge's interrupt routing info all the way up to its root port. In U-Boot all PCIe root ports' interrupts were routed to PIRQ E/F/G/H before, while actually all PCIe downstream ports received INTx are routed to PIRQ A/B/C/D directly and not configurable. Now we change this mapping so that any external PCIe device can work correctly. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04x86: Refactor PIRQ routing supportBin Meng1-1/+38
PIRQ routing is pretty much common in Intel chipset. It has several PIRQ links (normally 8) and corresponding registers (either in PCI configuration space or memory-mapped IBASE) to configure the legacy 8259 IRQ vector mapping. Refactor current Queensbay PIRQ routing support using device tree and move it to a common place, so that we can easily add PIRQ routing support on a new platform. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29x86: queensbay: Implement PIRQ routingBin Meng1-1/+9
Implement Intel Queensbay platform-specific PIRQ routing support. The chipset PIRQ routing setup is called in the arch_misc_init(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29x86: queensbay: Avoid using PCH prefixBin Meng1-2/+2
The prefix PCH was taken from ivybridge port. However Queensbay platform official document does not mention PCH. It is composed of TunnelCreek processor and Topcliff IOH chipset. For accuracy, avoid using PCH prefix in the macro. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-04-16x86: Add a x86_ prefix to the x86-specific PCI functionsSimon Glass1-2/+2
These functions currently use a generic name, but they are for x86 only. This may introduce confusion and prevents U-Boot from using these names more widely. In fact it should be possible to remove these at some point and use generic functions, but for now, rename them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-02-06x86: mmc: Move common FSP functions into a common fileSimon Glass1-27/+0
Since these board functions seem to be the same for all boards which use FSP, move them into a common file. We can adjust this later if future FSPs need more flexibility. This creates a generic PCI MMC device. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-02-05x86: Move common FSP code into a common locationSimon Glass1-1/+1
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2014-12-18x86: crownbay: Add SPI flash supportBin Meng1-1/+25
The Crown Bay board has an SST25VF016B flash connected to the Tunnel Creek processor SPI controller used as the BIOS media where U-Boot is stored. Enable this flash support. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18x86: Add basic support to queensbay platform and crownbay boardBin Meng1-0/+48
Implement minimum required functions for the basic support to queensbay platform and crownbay board. Currently the implementation is to call fsp_init() in the car_init(). We may move that call to cpu_init_f() in the future. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-08-02 01:35:33 +0000