rocket-tools/riscv-gnu-toolchain/qemu/roms/u-boot.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2019-12-10	riscv: add option to wait for ack from secondary harts in smp functions	Lukas Auer	5	-12/+28
2019-12-10	riscv: add functions for reading the IPI status	Lukas Auer	4	-0/+43
2019-12-10	riscv: dts: Add #address-cells and #size-cells in nor node	Rick Chen	2	-2/+6
2019-12-10	riscv: dts: Support four cores SMP	Rick Chen	2	-6/+108
2019-12-10	riscv: Fix clear bss loop in the start-up code	Rick Chen	3	-4/+4
2019-12-10	riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL	Rick Chen	1	-14/+46
2019-12-10	riscv: andes_plic: Fix some wrong configurations	Rick Chen	1	-4/+7
2019-12-10	riscv: ax25: add SPL support	Rick Chen	1	-1/+3
2019-12-10	riscv: dts: Add hifive-unleashed-a00 dts from Linux	Jagan Teki	3	-0/+348
2019-12-10	riscv: increase stack size to avoid a stack overflow during distro boot	Lukas Auer	1	-1/+1
2019-12-02	common: Move board_get_usable_ram_top() out of common.h	Simon Glass	1	-0/+1
2019-12-02	common: Move enable/disable_interrupts out of common.h	Simon Glass	1	-0/+1
2019-12-02	common: Move interrupt functions into a new header	Simon Glass	1	-0/+1
2019-12-02	common: Move ARM cache operations out of common.h	Simon Glass	3	-0/+3
2019-12-02	common: Move some cache and MMU functions out of common.h	Simon Glass	3	-0/+3
2019-10-18	RISC-V: Align boot image header with Linux	Atish Patra	1	-5/+6
2019-10-18	gpio: sifive: add support for DM based gpio driver for FU540-SoC	Sagar Shrikant Kadam	2	-0/+41
2019-09-03	riscv: cache: use CCTL to flush d-cache	Rick Chen	1	-9/+13
2019-09-03	riscv: dts: move out AE350 L2 node from cpus node	Rick Chen	2	-12/+22
2019-09-03	riscv: cache: Flush L2 cache before jump to linux	Rick Chen	1	-0/+17
2019-09-03	riscv: ax25: add imply v5l2 cache controller	Rick Chen	1	-0/+1
2019-09-03	riscv: andes_plic: init plic by scanning each cpu node	Rick Chen	1	-11/+25
2019-09-03	riscv: update fix_rela_dyn	Marcus Comstedt	1	-5/+5
2019-08-26	riscv: add a generic FIT generator script	Lukas Auer	1	-0/+100
2019-08-26	riscv: support SPL stack and global data relocation	Lukas Auer	1	-1/+34
2019-08-26	riscv: add SPL support	Lukas Auer	7	-1/+190
2019-08-26	riscv: add run mode configuration for SPL	Lukas Auer	7	-18/+44
2019-08-15	riscv: Access CSRs using CSR numbers	Bin Meng	4	-243/+19
2019-08-15	riscv: Sync csr.h with Linux kernel v5.2	Bin Meng	2	-16/+114
2019-08-11	env: Drop environment.h header file where not needed	Simon Glass	1	-1/+0
2019-07-16	efi_loader: use predefined constants in crt0_*_efi.S	Heinrich Schuchardt	1	-6/+5
2019-06-05	riscv: Add Microchip MPFS Icicle board support	Padmarao Begari	1	-0/+4
2019-05-18	CONFIG_SPL_SYS_[DI]CACHE_OFF: add	Trevor Woerner	2	-4/+18
2019-05-18	CONFIG_SYS_[DI]CACHE_OFF: convert to Kconfig	Trevor Woerner	1	-0/+12
2019-05-09	RISCV: image: Add booti support	Atish Patra	2	-0/+56
2019-05-09	riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is ena...	Rick Chen	2	-0/+4
2019-05-09	riscv: Introduce CONFIG_XIP to support booting from flash	Rick Chen	6	-0/+21
2019-04-12	dts: switch spi-flash to jedec, spi-nor compatible	Neil Armstrong	2	-2/+2
2019-04-08	riscv: dts: fix CONFIG_DEFAULT_DEVICE_TREE failure	Rick Chen	1	-0/+2
2019-04-08	riscv: dts: ae350 support SMP	Rick Chen	2	-44/+118
2019-04-08	riscv: ax25: Andes specific cache shall only support in M-mode	Rick Chen	1	-0/+1
2019-04-08	riscv: ax25: Add platform-specific Kconfig options	Rick Chen	1	-0/+6
2019-04-08	riscv: Add a SYSCON driver for Andestech's PLMT	Rick Chen	5	-0/+67
2019-04-08	riscv: Add a SYSCON driver for Andestech's PLIC	Rick Chen	5	-2/+127
2019-04-08	riscv: hang if relocation of secondary harts fails	Lukas Auer	1	-1/+12
2019-04-08	riscv: do not rely on hart ID passed by previous boot stage	Lukas Auer	1	-0/+4
2019-04-08	riscv: boot images passed to bootm on all harts	Lukas Auer	1	-1/+12
2019-04-08	riscv: add support for multi-hart systems	Lukas Auer	5	-2/+147
2019-04-08	riscv: save hart ID in register tp instead of s0	Lukas Auer	1	-2/+2
2019-04-08	riscv: delay initialization of caches and debug UART	Lukas Auer	1	-8/+8