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2023-12-18Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-riscv ↵WIP/18Dec2023-nextTom Rini4-0/+117
into next - VisionFive2: Enable CONFIG_SYSRESET - StarFive: Modify starfive timer driver - AMD/Xilinx: Add MicroBlaze V support - Unmatched: Migrate to text environment
2023-12-18Merge tag 'v2024.01-rc5' into nextTom Rini3-28/+29
Prepare v2024.01-rc5
2023-12-18riscv: Add support for AMD/Xilinx MicroBlaze VMichal Simek3-0/+112
MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP. It is hardware compatible with classic MicroBlaze processor. The patch contains initial wiring and configuration for initial HW design with memory, cpu, interrupt controller, timers and uartlite console (interrupt controller is listed but U-Boot is not using it). Provided DT is just describing one configuration and should be taken only as example. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
2023-12-18riscv: dts: jh7110: Add a gpio-restart nodeJaehoon Chung1-0/+5
Add gpio-restart node to do reset. Before applied this patch, System Reset Extension doesn't appear with sbi command. OpenSBI 1.3 Machine: Vendor ID 489 Architecture ID 8000000000000007 Implementation ID 4210427 Extensions: sbi_set_timer sbi_console_putchar ...[snip]... IPI Extension RFENCE Extension Hart State Management Extension Performance Monitoring Unit Extension After applied this patch, System Reset Extension is supported from SBI. OpenSBI 1.3 Machine: Vendor ID 489 Architecture ID 8000000000000007 Implementation ID 4210427 Extensions: sbi_set_timer sbi_console_putchar ...[snip]... IPI Extension RFENCE Extension Hart State Management Extension System Reset Extension Performance Monitoring Unit Extension Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-12-06riscv: binman: fix the load field formatRandolph1-10/+4
Using /bits/ 64 prefix for 64 bits address Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-12-06riscv: andes: Fix enable register settings of PLICSWYu Chien Peter Lin1-18/+15
On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
2023-12-05riscv: dts: jh7110: Add watchdog device tree nodeChanho Park1-0/+10
Adds jh7110 watchdog device tree node. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-11-28riscv: io.h: Fix signatures of reads/writes functionsIgor Prusov1-6/+12
Change type of address parameter from int* to volatile void* for {read,write}s{b,w,l}() functions and add const qualifier for reads. This is done to keep function signatures in sync with asm-generic/io.h and other platforms. Signed-off-by: Igor Prusov <ivprusov@salutedevices.com>
2023-11-28riscv: io.h: Add defines for reads/writes functionsIgor Prusov1-0/+8
Add defines for {read,write}s{b,w,l} functions to make asm-generic/io.h aware of them. Signed-off-by: Igor Prusov <ivprusov@salutedevices.com>
2023-11-02riscv: dts: jh7110: Add rng device tree nodeChanho Park1-0/+10
Adds jh7110 trng device tree node. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-11-02riscv: import read/write_relaxed functionsChanho Park1-0/+45
This imports mmio functions from Linux's arch/riscv/include/asm/mmio.h to use read/write[b|w|l|q]_relaxed functions. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-11-02riscv: allow resume after exceptionHeinrich Schuchardt1-0/+13
If CSRs like seed are readable by S-mode, may not be determinable by S-mode. For safe driver probing allow to resume via a longjmp after an exception. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-11-02riscv: cpu: jh7110: Add gpio helper macrosChanho Park1-0/+85
Add gpio.h header file that includes JH7110 helper macros. The file is imported from StarFive github[1] with small changes such as alignment. [1]: https://github.com/starfive-tech/u-boot Signed-off-by: Chanho Park <chanho61.park@samsung.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-11-02riscv: Weakly define invalidate_icache_range()Samuel Holland1-1/+1
Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-11-02riscv: Align the trap handler to 64 bytesSamuel Holland1-1/+1
This is required on CPUs which always operate in CLIC mode, such as the T-HEAD E906 and E907. Per the CLIC specification: "In this mode, the trap vector base address held in mtvec is constrained to be aligned on a 64-byte or larger power-of-two boundary." Reported-by: Madushan Nishantha <jlmadushan@gmail.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-11-02riscv: Sort target configs alphabeticallySamuel Holland1-9/+9
Clean things up for the next time somebody adds a target. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-10-30Kconfig: Remove all default n/no optionsMichal Simek1-1/+0
Similar change was done by commit b4c2c151b14b ("Kconfig: Remove all default n/no options") and again sync is required. default n/no doesn't need to be specified. It is default option anyway. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com> # tegra Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Angelo Dureghello <angelo@kernel-space.org>
2023-10-24riscv: Remove common.h usageTom Rini31-29/+8
We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
2023-10-22sunxi: dts: arm: add T113s/D1 DT files from Linux-v6.6-rc6Andre Przywara2-0/+942
This copies in some devicetree files from the official Linux kernel tree, v6.6-rc6. It covers a board with the Allwinner T113s SoC, which shares many devices with its RISC-V sibling, the Allwinner D1(s). This is the reason for the core .dtsi files landing in the arch/riscv directory. We are only adjusting the include path to accommodate for the differences in the U-Boot build system. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-10-19riscv: Add Zbb support for building U-BootYu Chien Peter Lin7-1/+392
This patch adds ISA string to the -march to generate zbb instructions for U-Boot binaries, along with optimized string functions introduced from Linux kernel. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-10-19riscv: dts: binman: add condition for opensbi os bootRandolph1-0/+24
Add condition for OpenSBI OS boot mode, by default it is not enabled. By default, binman creates the output file u-boot.itb. If SPL_OPENSBI_OS_BOOT is enabled, linux.itb will be created after compilation instead of the default u-boot.itb. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-19riscv: kconfig: introduce SPL_LOAD_FIT_OPENSBI_OS_BOOT symbolRandolph1-0/+8
Introduce common Kconfig symbol for riscv architecture. This symbol SPL_LOAD_FIT_OPENSBI_OS_BOOT is like falcon mode on ARM, the Falcon boot is a shortcut boot method for SD/eMMC targets. It skips the loading the RAM version U-Boot. Instead, it will loads the FIT image and boots directly to Linux. When SPL_OPENSBI_OS_BOOT is enabled, linux.itb is created after compilation instead of the default u-boot.itb. It initialises memory with the U-Boot SPL at the first stage, just as a normal boot process does at the beginning. Instead of jumping to the U-Boot proper from OpenSBI before booting the Linux kernel, the RISC-V falcon mode process jumps directly to the Linux kernel to gain shorter booting time. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-19riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategyRandolph1-13/+11
Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-10-19riscv: binman: Fix compilation errorMayuresh Chitale1-4/+10
Some platforms may not have any DDR memory below 4G and for such platforms the TEXT_BASE and LOAD addresses etc are all 64 bit addresses due to which the u-boot build fails with below error: u-boot/arch/riscv/dts/binman.dtsi:30.14-25 Value out of range for 32-bit array element u-boot/arch/riscv/dts/binman.dtsi:43.14-25 Value out of range for 32-bit array element u-boot/arch/riscv/dts/binman.dtsi:44.15-26 Value out of range for 32-bit array element FATAL ERROR: Syntax error parsing input tree Fix by setting the address-cells property to 2 and converting load addresses to 64 bit values. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-19riscv: remove dram_init_banksize()Heinrich Schuchardt1-16/+0
Remove dram_init_banksize() on the architecture level. Limiting used RAM to under 4 GiB is only necessary for CPUs which have a DMA issue. SoC specific code already exists for FU540, FU740, JH7110. Not all RISC-V boards will have memory below 4 GiB. A weak implementation of dram_init_banksize() exists in common/board_f.c. See the discussion in https://lore.kernel.org/u-boot/545fe813-cb1e-469c-a131-0025c77aeaa2@canonical.com/T/ Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2023-10-04riscv: andesv5: Prefer using the generic RISC-V timer driver in S-modeYu Chien Peter Lin1-1/+2
The Andes PLMT driver directly accesses the mtime MMIO region, indicating its intended use in the M-mode boot stage. However, since U-Boot proper (S-mode) also uses the PLMT driver, we need to specifically mark the region as readable through PMPCFGx (or S/U-mode read-only shared data region for Smepmp) in OpenSBI. Granting permission for this case doesn't make sense. Instead, we should use the generic RISC-V timer driver to read the mtime through the TIME CSR. Therefore, we add the SPL_ANDES_PLMT_TIMER config, which ensures that the PLMT driver is linked exclusively against M-mode U-Boot or U-Boot SPL binaries. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Samuel Holland <samuel@sholland.org>
2023-10-04configs: andes: add vender prefix for target nameRandolph2-3/+3
Modify "CONFIG_TARGET_AE350" to "CONFIG_TARGET_ANDES_AE350" Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2023-10-04riscv: enable CONFIG_DEBUG_UART by defaultHeinrich Schuchardt1-0/+1
Most boards don't enable the pre-console buffer. So we will not see any early messages. OpenSBI 1.3 provides us with the debug console extension that can fill this gap. For S-Mode U-Boot enable CONFIG_DEBUG_UART by default. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-10-04riscv: bootstage: correct bootstage_report guardChanho Park1-1/+1
Below warning can be occurred when CONFIG_BOOTSTAGE and !CONFIG_SPL_BOOTSTAGE. It should be guarded by using CONFIG_IS_ENABLED for SPL build. arch/riscv/lib/bootm.c:46:9: warning: implicit declaration of function 'bootstage_report' 46 | bootstage_report(); | ^~~~~~~~~~~~~~~~ | bootstage_error Signed-off-by: Chanho Park <chanho61.park@samsung.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-10-02Merge branch 'next'Tom Rini6-11/+22
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-09-26riscv: set fdtfile on VisionFive 2Heinrich Schuchardt1-0/+1
Multiple revisions of the StarFive VisionFive 2 board exist. They can be identified by reading their EEPROM. Linux uses two differently named device-tree files. To load the correct device-tree we need to set $fdtfile to the device-tree file name that matches the board revision. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Tested-by: Milan P. Stanić <mps@arvanta.net>
2023-09-24common: Drop linux/printk.h from common headerSimon Glass1-0/+1
This old patch was marked as deferred. Bring it back to life, to continue towards the removal of common.h Move this out of the common header and include it only where needed. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-09-22Record the position of the SMBIOS tablesSimon Glass1-0/+3
Remember where these end up so that we can pass this information on to the EFI layer. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-09-20riscv: dts: starfive: generate u-boot-spl.bin.normal.outHeinrich Schuchardt1-0/+11
The StarFive VisionFive 2 board cannot load spl/u-boot-spl.bin but needs a prefixed header. We have referring to a vendor tool (spl_tool) for this task. 'mkimage -T sfspl' can generate the prefixed file. Use binman to invoke mkimage for the generation of file spl/u-boot-spl.bin.normal.out. Update the documentation. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Tested-by: Milan P. Stanić <mps@arvanta.net>
2023-09-20riscv: set fdtfile on VisionFive 2Heinrich Schuchardt1-0/+1
Multiple revisions of the StarFive VisionFive 2 board exist. They can be identified by reading their EEPROM. Linux uses two differently named device-tree files. To load the correct device-tree we need to set $fdtfile to the device-tree file name that matches the board revision. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-09-06riscv: Correct event usage for riscv_cpu_probe/setupTom Rini1-5/+1
With having both an EVENT_SPY_SIMPLE setup for both riscv_cpu_probe and riscv_cpu_setup we do not need the latter function to call the former function as it will already have been done in time. Fixes: 1c55d62fb9cc ("riscv: cpu: make riscv_cpu_probe to EVT_DM_POST_INIT_R callback") Tested-by: Milan P. Stanić <mps@arvanta.net> Signed-off-by: Tom Rini <trini@konsulko.com>
2023-09-06riscv: Rework riscv_cpu_probe for current event macrosTom Rini1-2/+2
This function should now be a EVENT_SPY_SIMPLE call, update it. Tested-by: Milan P. Stanić <mps@arvanta.net> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2023-09-05risc-v: implement DBCN write byteHeinrich Schuchardt2-0/+17
The DBCN extension provides a Console Write Byte call. Implement function sbi_dbcn_write_byte to invoke it. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-09-05riscv: cpu: jh7110: Imply SPL_SYS_MALLOC_CLEAR_ON_INITShengyu Qu1-0/+1
Starfive JH7110 needs to clear L2 LIM to zero before use or ECC error would be triggered. Currently, we use DDR ram for SPL malloc arena on Visionfive 2 board in defconfig, but it's also possible to use L2 LIM as SPL malloc arena. To avoid triggering ECC error in this scenario, we imply SPL_SYS_MALLOC_CLEAR_ON_INIT as default. Signed-off-by: Bo Gan <ganboing@gmail.com> Signed-off-by: Shengyu Qu <wiagn233@outlook.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-09-05riscv: jh7110: enable riscv,timer in the device treeTorsten Duwe1-0/+9
The JH7110 has the arhitectural CPU timer on all 5 rv64 cores. Note that in the device tree. Signed-off-by: Torsten Duwe <duwe@suse.de> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-09-04Merge tag 'v2023.10-rc4' into nextTom Rini1-8/+3
Prepare v2023.10-rc4
2023-08-31event: Convert existing spy records to simpleSimon Glass3-4/+4
Very few of the existing event-spy records use the arguments they are passed. Update them to use a simple spy instead, to simplify the code. Where an adaptor function is currently used, remove it where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-08-22riscv: cpu: make riscv_cpu_probe to EVT_DM_POST_INIT_R callbackChanho Park1-8/+3
Since the Patch 55171aedda88, VisionFive2 booting has been broken [1]. VisionFive2 board requires to enable CONFIG_TIMER_EARLY but booting went to panic from initr_dm_devices due to lack of a timer device. - Error logs initcall sequence 00000000fffd8d38 failed at call 00000000402185e4 (err=-19) Thus, we need to move riscv_cpu_probe function in order to register the timer earlier than initr_dm_devices. Fixes: 7fe32b3442f0 ("event: Convert arch_cpu_init_dm() to use events") Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Chanho Park <chanho61.park@samsung.com> Tested-by: Milan P. Stanić <mps@arvanta.net> Tested-by: Roland Ruckerbauer <mail@ruabmbua.dev> Tested-by: Roland Ruckerbauer <mail@ruabmbua.dev>
2023-08-15common: return type board_get_usable_ram_topHeinrich Schuchardt4-4/+4
board_get_usable_ram_top() returns a physical address that is stored in gd->ram_top. The return type of the function should be phys_addr_t like the current type of gd->ram_top. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-08-10riscv: cpu: jh7110: Select SPL_ZERO_MEM_BEFORE_USEShengyu Qu1-0/+1
Add Kconfig item for Starfive JH7110 to select SPL_ZERO_MEM_BEFORE_USE. Signed-off-by: Bo Gan <ganboing@gmail.com> Signed-off-by: Shengyu Qu <wiagn233@outlook.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-08-10riscv: Add SPL_ZERO_MEM_BEFORE_USE implementationShengyu Qu2-25/+12
Add the actual support code for SPL_ZERO_MEM_BEFORE_USE and remove existing Starfive JH7110's L2 LIM clean code, since existing code has following issues: 1. Each hart (in the middle of a function call) overwriting its own stack and other harts' stacks. (data-race and data-corruption) 2. Lottery winner hart can be doing "board_init_f_init_reserve", while other harts are in the middle of zeroing L2 LIM. (data-race) Signed-off-by: Bo Gan <ganboing@gmail.com> Signed-off-by: Shengyu Qu <wiagn233@outlook.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-08-10riscv: Kconfig: Add SPL_ZERO_MEM_BEFORE_USEShengyu Qu1-0/+8
Add a Kconfig item to allow SPL to clear stack/GD/malloc area before using them. Signed-off-by: Bo Gan <ganboing@gmail.com> Signed-off-by: Shengyu Qu <wiagn233@outlook.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-08-10riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable SYS_CACHELINE_SIZEMinda Chen1-0/+1
Some device driver need SYS_CACHELINE_SIZE macro. Add StarFive SYS_CACHE_SHIFT_6 to enable it. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-08-10riscv: dts: starfive: Enable pcie0 dts nodeMinda Chen1-1/+1
In StarFive VF2 board. pcie0 connect to VTI usb controller. Enable it to support usb host. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-08-10cmd/sbi: display new extensionsHeinrich Schuchardt1-0/+2
The SBI specification v2.0-rc2 defines new extensions: * Nested Acceleration Extension (NACL) * Steal Time Accounting (STA) Allow the sbi command to display these. Add missing implementation IDs. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
generated by cgit v1.1 at 2024-09-16 21:04:41 +0000