rocket-tools/riscv-gnu-toolchain/qemu/roms/u-boot.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-11-02	riscv: dts: jh7110: Add rng device tree node	Chanho Park	1	-0/+10
2023-11-02	riscv: import read/write_relaxed functions	Chanho Park	1	-0/+45
2023-11-02	riscv: allow resume after exception	Heinrich Schuchardt	1	-0/+13
2023-11-02	riscv: cpu: jh7110: Add gpio helper macros	Chanho Park	1	-0/+85
2023-11-02	riscv: Weakly define invalidate_icache_range()	Samuel Holland	1	-1/+1
2023-11-02	riscv: Align the trap handler to 64 bytes	Samuel Holland	1	-1/+1
2023-11-02	riscv: Sort target configs alphabetically	Samuel Holland	1	-9/+9
2023-10-30	Kconfig: Remove all default n/no options	Michal Simek	1	-1/+0
2023-10-24	riscv: Remove common.h usage	Tom Rini	31	-29/+8
2023-10-22	sunxi: dts: arm: add T113s/D1 DT files from Linux-v6.6-rc6	Andre Przywara	2	-0/+942
2023-10-19	riscv: Add Zbb support for building U-Boot	Yu Chien Peter Lin	7	-1/+392
2023-10-19	riscv: dts: binman: add condition for opensbi os boot	Randolph	1	-0/+24
2023-10-19	riscv: kconfig: introduce SPL_LOAD_FIT_OPENSBI_OS_BOOT symbol	Randolph	1	-0/+8
2023-10-19	riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy	Randolph	1	-13/+11
2023-10-19	riscv: binman: Fix compilation error	Mayuresh Chitale	1	-4/+10
2023-10-19	riscv: remove dram_init_banksize()	Heinrich Schuchardt	1	-16/+0
2023-10-04	riscv: andesv5: Prefer using the generic RISC-V timer driver in S-mode	Yu Chien Peter Lin	1	-1/+2
2023-10-04	configs: andes: add vender prefix for target name	Randolph	2	-3/+3
2023-10-04	riscv: enable CONFIG_DEBUG_UART by default	Heinrich Schuchardt	1	-0/+1
2023-10-04	riscv: bootstage: correct bootstage_report guard	Chanho Park	1	-1/+1
2023-10-02	Merge branch 'next'	Tom Rini	6	-11/+22
2023-09-26	riscv: set fdtfile on VisionFive 2	Heinrich Schuchardt	1	-0/+1
2023-09-24	common: Drop linux/printk.h from common header	Simon Glass	1	-0/+1
2023-09-22	Record the position of the SMBIOS tables	Simon Glass	1	-0/+3
2023-09-20	riscv: dts: starfive: generate u-boot-spl.bin.normal.out	Heinrich Schuchardt	1	-0/+11
2023-09-20	riscv: set fdtfile on VisionFive 2	Heinrich Schuchardt	1	-0/+1
2023-09-06	riscv: Correct event usage for riscv_cpu_probe/setup	Tom Rini	1	-5/+1
2023-09-06	riscv: Rework riscv_cpu_probe for current event macros	Tom Rini	1	-2/+2
2023-09-05	risc-v: implement DBCN write byte	Heinrich Schuchardt	2	-0/+17
2023-09-05	riscv: cpu: jh7110: Imply SPL_SYS_MALLOC_CLEAR_ON_INIT	Shengyu Qu	1	-0/+1
2023-09-05	riscv: jh7110: enable riscv,timer in the device tree	Torsten Duwe	1	-0/+9
2023-09-04	Merge tag 'v2023.10-rc4' into next	Tom Rini	1	-8/+3
2023-08-31	event: Convert existing spy records to simple	Simon Glass	3	-4/+4
2023-08-22	riscv: cpu: make riscv_cpu_probe to EVT_DM_POST_INIT_R callback	Chanho Park	1	-8/+3
2023-08-15	common: return type board_get_usable_ram_top	Heinrich Schuchardt	4	-4/+4
2023-08-10	riscv: cpu: jh7110: Select SPL_ZERO_MEM_BEFORE_USE	Shengyu Qu	1	-0/+1
2023-08-10	riscv: Add SPL_ZERO_MEM_BEFORE_USE implementation	Shengyu Qu	2	-25/+12
2023-08-10	riscv: Kconfig: Add SPL_ZERO_MEM_BEFORE_USE	Shengyu Qu	1	-0/+8
2023-08-10	riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable SYS_CACHELINE_SIZE	Minda Chen	1	-0/+1
2023-08-10	riscv: dts: starfive: Enable pcie0 dts node	Minda Chen	1	-1/+1
2023-08-10	cmd/sbi: display new extensions	Heinrich Schuchardt	1	-0/+2
2023-08-02	acpi: Add missing RISC-V acpi_table header	Heinrich Schuchardt	1	-0/+11
2023-08-02	riscv: dts: starfive: Enable PCIe host controller	Mason Huo	2	-0/+85
2023-07-24	riscv: define a cache line size for the generic CPU	Heinrich Schuchardt	1	-0/+1
2023-07-24	riscv: dts: jh7110: Add clock source from PLL	Xingyu Wu	3	-6/+9
2023-07-24	riscv: dts: jh7110: Add PLL clock controller node	Xingyu Wu	1	-1/+7
2023-07-24	riscv: setup per-hart stack earlier	Bo Gan	1	-13/+24
2023-07-12	riscv: dts: t-head: Add basic device tree for Sipeed Lichee PI 4A board	Yixun Lan	4	-0/+473
2023-07-12	riscv: t-head: licheepi4a: initial support added	Yixun Lan	1	-0/+5
2023-07-12	riscv: Rename SiFive CLINT to RISC-V ALINT	Bin Meng	9	-21/+21