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2023-04-20riscv: Support CONFIG_REMAKE_ELFSamuel Holland1-0/+2
Add flags to tell objcopy what kind of ELF to create. Signed-off-by: Samuel Holland <samuel@sholland.org>
2023-04-20riscv: Update alignment for some sections in linker scriptsBin Meng2-4/+4
Some sections in the linker scripts are aligned to 4 bytes, which may cause misaligned exception on some platforms, e.g.: clearing the bss section on 64-bit hardware if __bss_start does not start from a naturally 8 bytes aligned address. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-04-20riscv: spl: Remove relocation sectionsBin Meng2-25/+2
U-Boot SPL is not relocable. Drop these relocation sections. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-04-20riscv: Avoid updating the link registerBin Meng1-1/+1
board_init_r does not return for U-Boot SPL hence there is no need to update the link register when jumping to board_init_r. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-04-20riscv: Change to use positive offset to access relocation entriesBin Meng1-12/+7
The codes currently skip the very first relocation entry, and have an inaccurate comment "skip first reserved entry" indicating that the first entry is reserved, but later it references the elements in the first relocation entry using a minus offset. Change to use a positive offset so that there is no need to skip the first relocation entry. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-04-20riscv: Optimize loading relocation typeBin Meng1-1/+0
't5' already contains relocation type so don't bother reloading it. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Rick Chen <rick@andestech.com>
2023-04-20riscv: Optimize source end address calculation in start.SBin Meng1-3/+1
The __bss_start is the source end address hence load its address directly into register 't2' for optimization. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Rick Chen <rick@andestech.com>
2023-04-20riscv: Enforce DWARF4 outputBin Meng1-2/+1
Since commit 409e4b547872 ("Makefile: Enforce DWARF4 output") the whole U-Boot build switched to enforce DWARF4 output, but RISC-V is still on its own setting. Let's switch to use U-Boot's setting. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-04-20riscv: Correct a comment in io.hBin Meng1-1/+1
Replace NDS32 with RISC-V in the comments. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Rick Chen <rick@andestech.com>
2023-04-20riscv: dts: jh7110: Add initial StarFive VisionFive v2 board device treeYanhong Wang6-1/+483
Add initial device tree for StarFive VisionFive v2 board. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-20riscv: dts: jh7110: Add initial u-boot device treeYanhong Wang1-0/+99
Add initial u-boot device tree for the JH7110 RISC-V SoC. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-20riscv: dts: jh7110: Add initial StarFive JH7110 device treeYanhong Wang1-0/+573
Add initial device tree for the JH7110 RISC-V SoC. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-20board: starfive: Add TARGET_STARFIVE_VISIONFIVE2 to KconfigYanhong Wang1-0/+5
Add board support for StarFive VisionFive v2. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-20riscv: cpu: jh7110: Add Kconfig for StarFive JH7110 SoCYanhong Wang1-0/+28
Add Kconfig to select the basic functions for StarFive JH7110 SoC. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-20riscv: cpu: jh7110: Add support for jh7110 SoCYanhong Wang6-0/+166
Add StarFive JH7110 SoC to support RISC-V arch. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Reviewed-by: Rick Chen <rick@andestech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
2023-03-06riscv: semihosting: replace inline assembly with assembly fileAndre Przywara2-24/+22
So far we used inline assembly to inject the actual instruction that triggers the semihosting service. While this sounds elegant, as it's really only about a few instructions, it has some serious downsides: - We need some barriers in place to force the compiler to issue writes to a data structure before issuing the trap instruction. - We need to convince the compiler to actually fill the structures that we use pointers to. - We need a memory clobber to avoid the compiler caching the data in those structures, when semihosting writes data back. - We need register arguments to make sure the function ID and the pointer land in the right registers. This is all doable, but fragile and somewhat cumbersome. Since we now have a separate function in an extra file anyway, we can do away with all the magic and just write that in an actual assembler. This is much more readable and robust. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Sean Anderson <sean.anderson@seco.com>
2023-02-27Merge tag 'v2023.04-rc3' into nextTom Rini14-265/+221
Prepare v2023.04-rc3
2023-02-17riscv: binman: Add help message for missing blobsRick Chen1-0/+1
Add the 'missing-msg' for more detailed output on missing system firmware. Signed-off-by: Rick Chen <rick@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
2023-02-17riscv: Rename Andes cpu and board namesLeo Yu-Chi Liang7-5/+5
The current ae350-related defconfigs could also support newer Andes CPU IP, so modify the names of CPU from ax25 to andesv5, and board name from ax25-ae350 to ae350. Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-17configs: ae350: Enable v5l2 cache for AE350 platforms in SPLYu Chien Peter Lin1-0/+1
To reduce the code size, CONFIG_V5L2_CACHE was disabled since commit: ca06444aac2c643db3a3f2eb37afc60fae15177e Turing on does not significantly increase the size of u-boot-spl.bin, so we enable it by default to improve performance. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-17riscv: ax25: cache.c: Cleanups to L1/L2 cache function used in SPLYu Chien Peter Lin1-30/+68
This patch refines L1 cache enable/disable and v5l2-cache enable functions. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-17riscv: ae350: dts: Update L2 cache compatible stringYu Chien Peter Lin2-2/+2
Update the compatible string of L2 cache. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-17riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init()Yu Chien Peter Lin2-37/+43
As the OpenSBI v1.2 does not enable the cache [0], we enable the i/d-cache in harts_early_init() and do not disable in cleanup_before_linux(). This patch also simplifies the logic and moves the CSR encoding to include/asm/arch-andes/csr.h. [0] https://github.com/riscv-software-src/opensbi/commit/bd7ef4139829da5c30fa980f7498d385124408fa Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-17riscv: Remove redundant Kconfig "RISCV_NDS_CACHE"Leo Yu-Chi Liang2-92/+2
There is no need for RISCV_NDS_CACHE config to control cache switches. Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-17riscv: global_data.h: Correct the comment for PLICSWYu Chien Peter Lin1-1/+1
PLIC is used for external interrupt, while PLICSW is an Andes-specific design for software interrupt. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-14dm: dts: Convert driver model tags to use new schemaSimon Glass7-71/+71
Now that Linux has accepted these tags, move the device tree files in U-Boot over to use them. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-10Correct SPL uses of LMBSimon Glass1-1/+1
This converts 9 usages of this option to the non-SPL form, since there is no SPL_LMB defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-01riscv: memcpy: check src and dst before copyRick Chen1-0/+2
Add src and dst address checking, if they are the same address, just return and don't copy data anymore. Signed-off-by: Rick Chen <rick@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-02-01riscv: ax25: bypass malloc when spl fit boots from ramRick Chen2-0/+28
When fit image boots from ram, the payload will be prepared in the address of SPL_LOAD_FIT_ADDRESS. In spl fit generic flow, it will malloc another memory address and copy whole fit image to this malloc address. But it is un-necessary for booting from RAM. This patch improves this flow by declare the board_spl_fit_buffer_addr() to replace the original one. The larger image size (eq: Kernel Image 10~20MB), it can save more booting time. Signed-off-by: Rick Chen <rick@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-02-01riscv: ae350: Enable CCTL_SUENRick Chen1-7/+11
CCTL operations are available to Supervisor/User-mode software under the control of the mcache_ctl.CCTL_SUEN control bit. Enable it to support Supervisor(and User) CCTL operations. Signed-off-by: Rick Chen <rick@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-02-01riscv: cpu: check U-Mode before counteren writeNikita Shubin1-8/+8
The Priv ISA states: "In systems without U-mode, the mcounteren register should not exist." Check U-Mode is present in MISA before writing to counteren, otherwise we endup with Illegal Instruction exception on systems without U-Mode. Also make checking MISA default for M-Mode. Signed-off-by: Nikita Shubin <n.shubin@yadro.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-01-20global: Finish CONFIG -> CFG migrationTom Rini1-1/+1
At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-09Merge branch 'next'Tom Rini1-2/+0
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-29efi_loader: set IMAGE_FILE_LARGE_ADDRESS_AWAREHeinrich Schuchardt1-5/+12
For the 64bit EFI binaries that we create set the IMAGE_FILE_LARGE_ADDRESS_AWARE characteristic in the PE-COFF header to indicate that they can handle addresses above 2 GiB. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-12-22Convert CONFIG_STANDALONE_LOAD_ADDR to KconfigTom Rini1-2/+0
This converts the following to Kconfig: CONFIG_STANDALONE_LOAD_ADDR Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-08arch/riscv: add semihosting support for RISC-VKautuk Consul4-0/+52
We add RISC-V semihosting based serial console for JTAG based early debugging. The RISC-V semihosting specification is available at: https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Kautuk Consul <kconsul@ventanamicro.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2022-11-15riscv: clarify meaning of CONFIG_SBI_V02Heinrich Schuchardt1-7/+7
Describe that CONFIG_SBI_V02=y does not mean SBI specification v0.2 but v0.2 or later. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Rick Chen <rick@andestech.com>
2022-11-15riscv: Fix detecting FPU support in standard extensionYu Chien Peter Lin1-3/+11
We should check the string until it hits underscore, in case it searches multi-letter extensions. For example, "rv64imac_xandes" will be treated as D extension support since there is a "d" in "andes", resulting illegal instruction caused by initializing FCSR. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Samuel Holland <samuel@sholland.org>
2022-11-15riscv: dts: fix the mpfs's reference clock frequencyConor Dooley2-8/+10
The initial devicetree for PolarFire SoC incorrectly created a fixed frequency clock in the devicetree to represent the msspll, but the msspll is not a fixed frequency clock. The actual reference clock on a board is either 125 or 100 MHz, 125 MHz in the case of the icicle kit. Swap the incorrect representation of the msspll out for the actual reference clock. Fixes: dd4ee416a6 ("riscv: dts: Add device tree for Microchip Icicle Kit") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
2022-11-03riscv: dts: Add QSPI NAND device nodePadmarao Begari1-0/+16
Add QSPI NAND device node to the Microchip PolarFire SoC Icicle kit device tree. The Winbond NAND flash memory can be connected to the Icicle Kit by using the Mikroe Flash 5 click board and the Pi 3 Click shield. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Rick Chen <rick@andestech.com>
2022-11-03riscv: dts: Update memory configurationPadmarao Begari1-58/+17
In the v2022.10 Icicle reference design, the seg registers have been changed, resulting in a required change to the memory map. A small 4MB reservation is made at the end of 32-bit DDR to provide some memory for the HSS to use, so that it can cache its payload between reboots of a specific context. Co-developed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Rick Chen <rick@andestech.com>
2022-11-03riscv: Rename Andes PLIC to PLICSWYu Chien Peter Lin9-28/+28
As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2022-10-31Rename CONFIG_SYS_TEXT_BASE to CONFIG_TEXT_BASESimon Glass1-1/+1
The current name is inconsistent with SPL which uses CONFIG_SPL_TEXT_BASE and this makes it imposible to use CONFIG_VAL(). Rename it to resolve this problem. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-10-20riscv: andes_plic.c: use modified IPI schemeYu Chien Peter Lin1-3/+4
The IPI scheme in OpenSBI has been updated to support 8-core AE350 platform, the plicsw configuration needs to be modified accordingly. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2022-10-20riscv: support building double-float modulesHeinrich Schuchardt2-3/+27
The riscv32 toolchain for GCC-12 provided by kernel.org contains libgcc.a compiled for double-float. To link to it we have to adjust how we build U-Boot. As U-Boot actually does not use floating point at all this should not make a significant difference for the produced binaries. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2022-10-07riscv: Fix build against binutils 2.38WIP/2022-10-07-riscv-toolchain-updateAlexandre Ghiti1-1/+10
The following description is copied from the equivalent patch for the Linux Kernel proposed by Aurelien Jarno: >From version 2.38, binutils default to ISA spec version 20191213. This means that the csr read/write (csrr*/csrw*) instructions and fence.i instruction has separated from the `I` extension, become two standalone extensions: Zicsr and Zifencei. As the kernel uses those instruction, this causes the following build failure: arch/riscv/cpu/mtrap.S: Assembler messages: arch/riscv/cpu/mtrap.S:65: Error: unrecognized opcode `csrr a0,scause' arch/riscv/cpu/mtrap.S:66: Error: unrecognized opcode `csrr a1,sepc' arch/riscv/cpu/mtrap.S:67: Error: unrecognized opcode `csrr a2,stval' arch/riscv/cpu/mtrap.S:70: Error: unrecognized opcode `csrw sepc,a0' Signed-off-by: Alexandre Ghiti <alexandre.ghiti@canonical.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Christian Stewart <christian@paral.in> Reviewed-by: Rick Chen <rick@andestech.com>
2022-09-29dm: core: Drop ofnode_is_available()Simon Glass2-2/+2
This function is also available as ofnode_is_enabled(), so use that instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29treewide: Drop bootm_headers_t typedefSimon Glass1-4/+4
This is not needed and we should avoid typedefs. Use the struct instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-26Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-riscv ↵Tom Rini6-11/+36
into next
2022-09-26riscv: Introduce AVAILABLE_HARTSRick Chen6-5/+23
In SMP all harts will register themself in available_hart during start up. Then main hart will send IPI to other harts according to this variables. But this mechanism may not guarantee that all other harts can jump to next stage. When main hart is sending IPI to other hart according to available_harts, but other harts maybe still not finish the registration. Then the SMP booting will miss some harts finally. So let it become an option and it will be enabled by default. Please refer to the discussion: https://www.mail-archive.com/u-boot@lists.denx.de/msg449997.html Signed-off-by: Rick Chen <rick@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
generated by cgit v1.1 at 2024-07-13 21:17:34 +0000