rocket-tools/riscv-gnu-toolchain/qemu/roms/u-boot.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2022-03-15	k210: dts: align plic node with Linux	Niklas Cassel	1	-2/+2
2022-03-15	k210: dts: align fpioa node with Linux	Damien Le Moal	1	-2/+1
2022-03-15	k210: dts: add missing power bus clocks	Damien Le Moal	1	-23/+53
2022-03-15	k210: use the board vendor name rather than the marketing name	Damien Le Moal	2	-50/+51
2022-02-09	dts: automatically build necessary .dtb files	Rasmus Villemoes	1	-0/+2
2021-12-23	riscv: qemu: Split devicetree files for qemu_riscv32/64	Simon Glass	3	-1/+15
2021-12-02	riscv: Support booting SiFive Unmatched from SPI.	Thomas Skibo	1	-0/+11
2021-12-02	riscv: dts: Split Microchip device tree	Padmarao Begari	2	-389/+700
2021-10-18	riscv: Remove OF_PRIOR_STAGE from RISC-V boards	Ilias Apalodimas	1	-3/+3
2021-07-21	board: sifive: drop stuff related to unmatched revision 1	Zong Li	4	-1501/+1
2021-07-07	riscv: dts: add OpenPiton RISC-V board dts support	Tianrui Wei	1	-2/+2
2021-07-06	riscv: dts: add dts for unmatched rev1	Zong Li	4	-1/+1501
2021-07-06	riscv: sifive: fu740: Support i2c in spl	Zong Li	1	-0/+4
2021-07-06	board: riscv: add openpiton-riscv64 SoC support	Tianrui Wei	2	-0/+154
2021-06-28	Merge tag 'v2021.07-rc5' into next	Tom Rini	3	-7/+61
2021-06-17	k210: dts: Set PLL1 to the same rate as PLL0	Sean Anderson	1	-0/+2
2021-06-17	riscv: ae350: dts: Add missing "u-boot, dm-spl" for SPL config	Bin Meng	3	-0/+54
2021-06-17	riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bit	Bin Meng	1	-1/+1
2021-06-17	riscv: ae350: dts: Remove the unnecessary #address-cells in plic nodes	Bin Meng	2	-4/+0
2021-06-17	riscv: ae350: dts: Remove the unnecessary space in bootargs	Bin Meng	2	-2/+2
2021-06-17	riscv: ae350: dts: Add SPDX license header	Bin Meng	2	-0/+4
2021-05-31	riscv: dts: add SiFive Unmatched board support	Green Wan	4	-0/+1790
2021-05-31	riscv: dts: add fu740 support	Green Wan	2	-0/+434
2021-05-19	riscv: ae350: Switch to use binman to generate u-boot.itb	Bin Meng	2	-0/+4
2021-05-19	riscv: qemu: Switch to use binman to generate u-boot.itb	Bin Meng	3	-0/+17
2021-05-19	riscv: dts: Sort build targets in alphabetical order	Bin Meng	1	-1/+1
2021-05-19	riscv: sifive: unleashed: Switch to use binman to generate u-boot.itb	Bin Meng	2	-0/+71
2021-05-14	riscv: Don't reserve AI ram in k210 dts	Sean Anderson	1	-12/+0
2021-05-14	riscv: k210: Use AI as the parent clock of aisram, not PLL1	Sean Anderson	1	-1/+1
2021-05-14	riscv: k210: Rename airam to aisram	Sean Anderson	1	-2/+2
2021-05-14	riscv: Enable some devices pre-relocation	Sean Anderson	1	-0/+4
2021-04-08	riscv: dts: mpfs-icicle-kit: Drop 'clock-frequency' in the uart nodes	Bin Meng	1	-4/+0
2021-04-08	riscv: sifive: Rename fu540 board to unleashed	Bin Meng	1	-1/+1
2021-04-08	riscv: Add watchdog bindings for the k210	Sean Anderson	1	-1/+0
2021-02-25	riscv: k210: Enable QSPI for spi3	Sean Anderson	1	-0/+2
2021-01-18	riscv: dts: Add device tree for Microchip Icicle Kit	Padmarao Begari	3	-0/+436
2020-12-18	riscv: Add device tree bindings for SPI	Sean Anderson	2	-1/+47
2020-12-18	spi: dw: Add SoC-specific compatible strings	Sean Anderson	1	-5/+8
2020-10-26	riscv: fu540: dts: Correct reg size of clint node	Pragnesh Patel	1	-1/+1
2020-10-26	riscv: k210: Reduce DMA block size	Sean Anderson	1	-2/+2
2020-10-08	riscv: add DT binding for BOOT button on Maix board	Heinrich Schuchardt	1	-0/+11
2020-10-08	riscv: Add pinmux and gpio bindings for Kendryte K210	Sean Anderson	2	-0/+116
2020-09-30	riscv: Update SiFive device tree for new CLINT driver	Sean Anderson	2	-2/+10
2020-09-30	riscv: Update Kendryte device tree for new CLINT driver	Sean Anderson	1	-3/+4
2020-08-04	fu540: dtsi: add reset producer and consumer entries	Sagar Shrikant Kadam	1	-0/+12
2020-07-24	riscv: dts: hifive-unleashed-a00: Make memory node available to SPL	Bin Meng	1	-0/+4
2020-07-24	sifive: fu540: Add Booting from SPI	Jagan Teki	1	-0/+12
2020-07-06	Merge branch 'next'	Tom Rini	4	-0/+646
2020-07-03	riscv: sifive: fu540: enable all cache ways from U-Boot proper	Pragnesh Patel	1	-0/+4
2020-07-02	riscv: fu540: dts: Correct reg size of otp and dmc nodes	Bin Meng	1	-2/+2