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2023-12-18Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-riscv ↵WIP/18Dec2023-nextTom Rini3-0/+113
into next - VisionFive2: Enable CONFIG_SYSRESET - StarFive: Modify starfive timer driver - AMD/Xilinx: Add MicroBlaze V support - Unmatched: Migrate to text environment
2023-12-18riscv: Add support for AMD/Xilinx MicroBlaze VMichal Simek2-0/+108
MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP. It is hardware compatible with classic MicroBlaze processor. The patch contains initial wiring and configuration for initial HW design with memory, cpu, interrupt controller, timers and uartlite console (interrupt controller is listed but U-Boot is not using it). Provided DT is just describing one configuration and should be taken only as example. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
2023-12-18riscv: dts: jh7110: Add a gpio-restart nodeJaehoon Chung1-0/+5
Add gpio-restart node to do reset. Before applied this patch, System Reset Extension doesn't appear with sbi command. OpenSBI 1.3 Machine: Vendor ID 489 Architecture ID 8000000000000007 Implementation ID 4210427 Extensions: sbi_set_timer sbi_console_putchar ...[snip]... IPI Extension RFENCE Extension Hart State Management Extension Performance Monitoring Unit Extension After applied this patch, System Reset Extension is supported from SBI. OpenSBI 1.3 Machine: Vendor ID 489 Architecture ID 8000000000000007 Implementation ID 4210427 Extensions: sbi_set_timer sbi_console_putchar ...[snip]... IPI Extension RFENCE Extension Hart State Management Extension System Reset Extension Performance Monitoring Unit Extension Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-12-06riscv: binman: fix the load field formatRandolph1-10/+4
Using /bits/ 64 prefix for 64 bits address Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-12-05riscv: dts: jh7110: Add watchdog device tree nodeChanho Park1-0/+10
Adds jh7110 watchdog device tree node. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-11-02riscv: dts: jh7110: Add rng device tree nodeChanho Park1-0/+10
Adds jh7110 trng device tree node. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-10-22sunxi: dts: arm: add T113s/D1 DT files from Linux-v6.6-rc6Andre Przywara2-0/+942
This copies in some devicetree files from the official Linux kernel tree, v6.6-rc6. It covers a board with the Allwinner T113s SoC, which shares many devices with its RISC-V sibling, the Allwinner D1(s). This is the reason for the core .dtsi files landing in the arch/riscv directory. We are only adjusting the include path to accommodate for the differences in the U-Boot build system. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-10-19riscv: dts: binman: add condition for opensbi os bootRandolph1-0/+24
Add condition for OpenSBI OS boot mode, by default it is not enabled. By default, binman creates the output file u-boot.itb. If SPL_OPENSBI_OS_BOOT is enabled, linux.itb will be created after compilation instead of the default u-boot.itb. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-19riscv: binman: Fix compilation errorMayuresh Chitale1-4/+10
Some platforms may not have any DDR memory below 4G and for such platforms the TEXT_BASE and LOAD addresses etc are all 64 bit addresses due to which the u-boot build fails with below error: u-boot/arch/riscv/dts/binman.dtsi:30.14-25 Value out of range for 32-bit array element u-boot/arch/riscv/dts/binman.dtsi:43.14-25 Value out of range for 32-bit array element u-boot/arch/riscv/dts/binman.dtsi:44.15-26 Value out of range for 32-bit array element FATAL ERROR: Syntax error parsing input tree Fix by setting the address-cells property to 2 and converting load addresses to 64 bit values. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-10-04configs: andes: add vender prefix for target nameRandolph1-1/+1
Modify "CONFIG_TARGET_AE350" to "CONFIG_TARGET_ANDES_AE350" Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2023-10-02Merge branch 'next'Tom Rini1-0/+11
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-09-20riscv: dts: starfive: generate u-boot-spl.bin.normal.outHeinrich Schuchardt1-0/+11
The StarFive VisionFive 2 board cannot load spl/u-boot-spl.bin but needs a prefixed header. We have referring to a vendor tool (spl_tool) for this task. 'mkimage -T sfspl' can generate the prefixed file. Use binman to invoke mkimage for the generation of file spl/u-boot-spl.bin.normal.out. Update the documentation. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Tested-by: Milan P. Stanić <mps@arvanta.net>
2023-09-05riscv: jh7110: enable riscv,timer in the device treeTorsten Duwe1-0/+9
The JH7110 has the arhitectural CPU timer on all 5 rv64 cores. Note that in the device tree. Signed-off-by: Torsten Duwe <duwe@suse.de> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-08-10riscv: dts: starfive: Enable pcie0 dts nodeMinda Chen1-1/+1
In StarFive VF2 board. pcie0 connect to VTI usb controller. Enable it to support usb host. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-08-02riscv: dts: starfive: Enable PCIe host controllerMason Huo2-0/+85
Enable and add pinctrl configuration for PCIe host controller. Signed-off-by: Mason Huo <mason.huo@starfivetech.com> Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-07-24riscv: dts: jh7110: Add clock source from PLLXingyu Wu3-6/+9
Change the PLL clock source from syscrg to sys_syscon child node. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Reviewed-by: Torsten Duwe <duwe@suse.de> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-07-24riscv: dts: jh7110: Add PLL clock controller nodeXingyu Wu1-1/+7
Add child node about PLL clock controller in sys_syscon node. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Reviewed-by: Torsten Duwe <duwe@suse.de> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-07-12riscv: dts: t-head: Add basic device tree for Sipeed Lichee PI 4A boardYixun Lan4-0/+473
Only add basic support for CPU, PLIC UART and Timer. Reviewed-by: Wei Fu <wefu@redhat.com> Signed-off-by: Yixun Lan <dlan@gentoo.org>
2023-07-12riscv: dts: starfive: Add support eeprom device tree nodeYanhong Wang2-0/+20
Add support "atmel,24c04" eeprom for StarFive VisionFive2 board. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-07-12riscv: dts: jh7110: Combine the board device tree files of 1.2A and 1.3BYanhong Wang5-86/+26
The difference between 1.2A and 1.3B is dynamically configured according to the PCB version, and there is no difference on the board device tree, so the same DT file can be used. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-07-12riscv: dts: jh7110: Add ethernet device tree nodesYanhong Wang2-0/+103
Add ethernet device tree node to support StarFive ethernet driver for the JH7110 RISC-V SoC. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-07-06riscv: dts: sync mpfs-icicle devicetree with linuxConor Dooley3-302/+387
The "notable" disappearances are: - the pac193x stanza - there's nothing in mainline linux w.r.t. bindings for this & what is going to appear in mainline linux is going to be incompatible with what is currently in U-Boot. - operating points - these operating points should not be set at the soc.dtsi level as they may not be possible depending on the design programmed to the FPGA - clock output names - there are defines for the clock indices, these should not be needed - the dt maintainers in linux NAKed using defines for IRQ numbers - the qspi nand, which is not part of the icicle's default configuration is removed. Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Rick Chen <rick@andestech.com>
2023-07-06riscv: dts: drop microchip from dts filenamesConor Dooley4-2/+2
The original names picked for the DT doesn't match Linux's naming scheme and it was renamed there a while ago. Rename it in U-Boot to allow easily syncing dts between the two projects. Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-20riscv: dts: jh7110: Add initial StarFive VisionFive v2 board device treeYanhong Wang6-1/+483
Add initial device tree for StarFive VisionFive v2 board. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-20riscv: dts: jh7110: Add initial u-boot device treeYanhong Wang1-0/+99
Add initial u-boot device tree for the JH7110 RISC-V SoC. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-20riscv: dts: jh7110: Add initial StarFive JH7110 device treeYanhong Wang1-0/+573
Add initial device tree for the JH7110 RISC-V SoC. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
2023-02-27Merge tag 'v2023.04-rc3' into nextTom Rini4-3/+4
Prepare v2023.04-rc3
2023-02-17riscv: binman: Add help message for missing blobsRick Chen1-0/+1
Add the 'missing-msg' for more detailed output on missing system firmware. Signed-off-by: Rick Chen <rick@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
2023-02-17riscv: Rename Andes cpu and board namesLeo Yu-Chi Liang1-1/+1
The current ae350-related defconfigs could also support newer Andes CPU IP, so modify the names of CPU from ax25 to andesv5, and board name from ax25-ae350 to ae350. Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-17riscv: ae350: dts: Update L2 cache compatible stringYu Chien Peter Lin2-2/+2
Update the compatible string of L2 cache. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-14dm: dts: Convert driver model tags to use new schemaSimon Glass7-71/+71
Now that Linux has accepted these tags, move the device tree files in U-Boot over to use them. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-11-15riscv: dts: fix the mpfs's reference clock frequencyConor Dooley2-8/+10
The initial devicetree for PolarFire SoC incorrectly created a fixed frequency clock in the devicetree to represent the msspll, but the msspll is not a fixed frequency clock. The actual reference clock on a board is either 125 or 100 MHz, 125 MHz in the case of the icicle kit. Swap the incorrect representation of the msspll out for the actual reference clock. Fixes: dd4ee416a6 ("riscv: dts: Add device tree for Microchip Icicle Kit") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
2022-11-03riscv: dts: Add QSPI NAND device nodePadmarao Begari1-0/+16
Add QSPI NAND device node to the Microchip PolarFire SoC Icicle kit device tree. The Winbond NAND flash memory can be connected to the Icicle Kit by using the Mikroe Flash 5 click board and the Pi 3 Click shield. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Rick Chen <rick@andestech.com>
2022-11-03riscv: dts: Update memory configurationPadmarao Begari1-58/+17
In the v2022.10 Icicle reference design, the seg registers have been changed, resulting in a required change to the memory map. A small 4MB reservation is made at the end of 32-bit DDR to provide some memory for the HSS to use, so that it can cache its payload between reboots of a specific context. Co-developed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Rick Chen <rick@andestech.com>
2022-11-03riscv: Rename Andes PLIC to PLICSWYu Chien Peter Lin3-7/+7
As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2022-10-31Rename CONFIG_SYS_TEXT_BASE to CONFIG_TEXT_BASESimon Glass1-1/+1
The current name is inconsistent with SPL which uses CONFIG_SPL_TEXT_BASE and this makes it imposible to use CONFIG_VAL(). Rename it to resolve this problem. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-06riscv: dts: sifive: Synchronize FU740 and Unmatched DTIcenowy Zheng2-88/+59
These DT files are synchronized from Linux 5.19. Signed-off-by: Icenowy Zheng <uwu@icenowy.me> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2022-09-06dt-bindings: clock: sifive: sync FU740 PRCI clock binding headerIcenowy Zheng2-22/+22
This commit sychronizes the header file for FU740 PRCI clocks with the one from Linux 5.19. The constant values are the same, but all constant names are changed (most are just prefixed with FU740_). Signed-off-by: Icenowy Zheng <uwu@icenowy.me> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2022-09-05riscv: dts: Sync important Unmatched pmic and qspi0 changes from LinuxJessica Clarke1-1/+14
This adds the onkey, RTC and watchdog children to the DA9063 PMIC node, fixes the compatible for qspi0's flash node to match the official DT schema (it being an is25wp256 is discoverable, hence jedec,spi-nor is the only compatible that should be present) and exposes the card detect GPIO. Note that the device trees still diverge in some places (including important things like the PCIe controller's clock name) and should be cleaned up so that a common device tree is used in both projects rather than having different bindings. This patch does not attempt to do that, merely expose important functionality present in Linux's that is not in U-Boot's so that it can be used without the OS providing its own bundled copy. Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2022-03-15k210: dts: align plic node with LinuxNiklas Cassel1-2/+2
The Linux PLIC interrupt-controller driver actually initializes the hart context registers in the PLIC driver exactly in the same order as specified in the interrupts-extended device tree property. See the device tree binding [1]. The ordering of the interrupts is therefore essential in order to configure the PLIC correctly. Fix the order so that we will have sane IRQ behavior when booting Linux with the u-boot device tree. [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2022-03-15k210: dts: align fpioa node with LinuxDamien Le Moal1-2/+1
Linux kernel fpioa pinctrl driver expects the sysctl phandle and the power bit offset of the fpioa device to be specified as a single property "canaan,k210-sysctl-power". Replace the "canaan,k210-sysctl" and "canaan,k210-power-offset" properties with "canaan,k210-sysctl-power" to satisfy the Linux kernel requirements. This new property is parsed using the existing function dev_read_phandle_with_args(). Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com> Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2022-03-15k210: dts: add missing power bus clocksDamien Le Moal1-23/+53
Linux drivers for many of the K210 peripherals depend on the power bus clock to be specified. Add the missing clocks and their names to avoid problems when booting Linux using u-boot DT. Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com> Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2022-03-15k210: use the board vendor name rather than the marketing nameDamien Le Moal2-50/+51
"kendryte" is the marketing name for the K210 RISC-V SoC produced by Canaan Inc. Rather than "kendryte,k210", use the usual "canaan,k210" vendor,SoC compatibility string format in the device tree files and use the SoC name for file names. With these changes, the device tree files are more in sync with the Linux kernel DTS and drivers, making uboot device tree usable by the kernel. Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com> Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2022-02-09dts: automatically build necessary .dtb filesRasmus Villemoes1-0/+2
When building for a custom board, it is quite common to maintain a private branch which include some defconfig and .dts files. But to hook up those .dts files requires modifying a file "belonging" to upstream U-Boot, the arch/*/dts/Makefile. Forward-porting that branch to a newer upstream then often results in a conflict which, while it is trivial to resolve by hand, makes it harder to have a CI do "try to build our board against latest upstream". The .config usually includes information on precisely what .dtb(s) are needed, so to avoid having to modify the Makefile, simply add the files in (SPL_)OF_LIST to dtb-y. A technicality is that (SPL_)OF_LIST is not always defined, so rework the Kconfig symbols so that (SPL_)OF_LIST is always defined (when (SPL_)OF_CONTROL), but only prompted for in the cases which used to be their "depends on". nios2 and microblaze already have something like this in their dts/Makefile, and the rationale in commit 41f59f68539 is similar to the above. So this simply generalizes existing practice. Followup patches could remove the logic in those two makefiles, just as there's potential for moving some common boilerplate from all the arch/*/dts/Makefile files to the new scripts/Makefile.dts. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-12-23riscv: qemu: Split devicetree files for qemu_riscv32/64Simon Glass3-1/+15
This uses QEMU virt which creates its own devicetree. Copy the existing empty version of this file, so splitting the existing qemu-virt into two, since anyone actually trying to use this will need a different devicetree for 32- and 64-bit machines. Tested-by: Heinrich Schuchardt <heinrich.schuchardt@canaonical.com> Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-02riscv: Support booting SiFive Unmatched from SPI.Thomas Skibo1-0/+11
Configure SPI flash devices into SPL. Add SPI boot option to spl.c. Document how to format flash for booting. Signed-off-by: Thomas Skibo <thomas-git@skibo.net> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-12-02riscv: dts: Split Microchip device treePadmarao Begari2-389/+700
The device tree split into .dtsi and .dts files, common device node for eMMC/SD, enable I2C1, UART1 for console instead of UART0, enable the DDR 2GB memory and in that 288MB memory is reserved for fabric buffer. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-10-18riscv: Remove OF_PRIOR_STAGE from RISC-V boardsIlias Apalodimas1-3/+3
At some point back in 2018 prior_stage_fdt_address and OF_PRIOR_STAGE got introduced, in order to support a DTB handed over by an earlier stage boo loader. However we have another option in the Kconfig (OF_BOARD) which has identical semantics. On RISC-V some of the boards pick up the DTB from a1 and copy it in their private gd_t. Apart from that they copy it to prior_stage_fdt_address, if the Kconfig option is selected, which is unnecessary. So let's switch the config option for those boards to OF_BOARD and define the required board_fdt_blob_setup() for them. Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-07-21board: sifive: drop stuff related to unmatched revision 1Zong Li4-1501/+1
This patch reverts the following commits: - 4b4159d0f3 ("riscv: dts: add dts for unmatched rev1") - ffe9a394df ("board: sifive: support spl multi-dtb on unmatched board") We won't plan to support unmatched that the revision below 3 in u-boot, so they can be dropped because they might be useless. Changed in v2: - rebase codebase to the latest master branch Signed-off-by: Zong Li <zong.li@sifive.com> Suggested-by: David Abdurachmanov <david.abdurachmanov@sifive.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-07-07riscv: dts: add OpenPiton RISC-V board dts supportTianrui Wei1-2/+2
Previous device tree for OpenPiton emits a warning during compilation. This commit fixes the previous warning adds dts to the OpenPiton RISC-V board and added the device tree to MAINTAINER file. Signed-off-by: Tianrui Wei <tianrui-wei@outlook.com> Reported-by: Tom Rini <trini@konsulko.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
generated by cgit v1.1 at 2024-07-15 05:17:24 +0000