rocket-tools/riscv-gnu-toolchain/qemu/roms/u-boot.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-11-02	riscv: Align the trap handler to 64 bytes	Samuel Holland	1	-1/+1
2023-10-24	riscv: Remove common.h usage	Tom Rini	12	-12/+0
2023-10-19	riscv: remove dram_init_banksize()	Heinrich Schuchardt	1	-16/+0
2023-10-04	riscv: andesv5: Prefer using the generic RISC-V timer driver in S-mode	Yu Chien Peter Lin	1	-1/+2
2023-10-02	Merge branch 'next'	Tom Rini	1	-9/+5
2023-09-06	riscv: Correct event usage for riscv_cpu_probe/setup	Tom Rini	1	-5/+1
2023-09-06	riscv: Rework riscv_cpu_probe for current event macros	Tom Rini	1	-2/+2
2023-09-05	riscv: cpu: jh7110: Imply SPL_SYS_MALLOC_CLEAR_ON_INIT	Shengyu Qu	1	-0/+1
2023-09-04	Merge tag 'v2023.10-rc4' into next	Tom Rini	1	-8/+3
2023-08-31	event: Convert existing spy records to simple	Simon Glass	1	-2/+2
2023-08-22	riscv: cpu: make riscv_cpu_probe to EVT_DM_POST_INIT_R callback	Chanho Park	1	-8/+3
2023-08-15	common: return type board_get_usable_ram_top	Heinrich Schuchardt	4	-4/+4
2023-08-10	riscv: cpu: jh7110: Select SPL_ZERO_MEM_BEFORE_USE	Shengyu Qu	1	-0/+1
2023-08-10	riscv: Add SPL_ZERO_MEM_BEFORE_USE implementation	Shengyu Qu	2	-25/+12
2023-08-10	riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable SYS_CACHELINE_SIZE	Minda Chen	1	-0/+1
2023-07-24	riscv: define a cache line size for the generic CPU	Heinrich Schuchardt	1	-0/+1
2023-07-24	riscv: setup per-hart stack earlier	Bo Gan	1	-13/+24
2023-07-12	riscv: Rename SiFive CLINT to RISC-V ALINT	Bin Meng	4	-5/+5
2023-07-12	ram: starfive: Read memory size information from EEPROM	Yanhong Wang	1	-1/+31
2023-06-27	riscv: Fix alignment of RELA sections in the linker scripts	Bin Meng	1	-3/+1
2023-05-11	dm: Emit the arch_cpu_init_dm() even only before relocation	Simon Glass	1	-1/+1
2023-04-20	riscv: Update alignment for some sections in linker scripts	Bin Meng	2	-4/+4
2023-04-20	riscv: spl: Remove relocation sections	Bin Meng	2	-25/+2
2023-04-20	riscv: Avoid updating the link register	Bin Meng	1	-1/+1
2023-04-20	riscv: Change to use positive offset to access relocation entries	Bin Meng	1	-12/+7
2023-04-20	riscv: Optimize loading relocation type	Bin Meng	1	-1/+0
2023-04-20	riscv: Optimize source end address calculation in start.S	Bin Meng	1	-3/+1
2023-04-20	riscv: cpu: jh7110: Add Kconfig for StarFive JH7110 SoC	Yanhong Wang	1	-0/+28
2023-04-20	riscv: cpu: jh7110: Add support for jh7110 SoC	Yanhong Wang	4	-0/+135
2023-02-17	riscv: Rename Andes cpu and board names	Leo Yu-Chi Liang	5	-0/+0
2023-02-17	configs: ae350: Enable v5l2 cache for AE350 platforms in SPL	Yu Chien Peter Lin	1	-0/+1
2023-02-17	riscv: ax25: cache.c: Cleanups to L1/L2 cache function used in SPL	Yu Chien Peter Lin	1	-30/+68
2023-02-17	riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init()	Yu Chien Peter Lin	1	-37/+12
2023-02-17	riscv: Remove redundant Kconfig "RISCV_NDS_CACHE"	Leo Yu-Chi Liang	2	-92/+2
2023-02-01	riscv: ax25: bypass malloc when spl fit boots from ram	Rick Chen	2	-0/+28
2023-02-01	riscv: ae350: Enable CCTL_SUEN	Rick Chen	1	-7/+11
2023-02-01	riscv: cpu: check U-Mode before counteren write	Nikita Shubin	1	-8/+8
2022-11-15	riscv: Fix detecting FPU support in standard extension	Yu Chien Peter Lin	1	-3/+11
2022-11-03	riscv: Rename Andes PLIC to PLICSW	Yu Chien Peter Lin	1	-1/+1
2022-09-26	Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-riscv ...	Tom Rini	2	-8/+13
2022-09-26	riscv: Introduce AVAILABLE_HARTS	Rick Chen	2	-5/+10
2022-09-26	spl: introduce SPL_XIP to config	Nikita Shubin	2	-3/+3
2022-09-23	board_f: Fix types for board_get_usable_ram_top()	Pali Rohár	3	-3/+3
2022-08-11	riscv: ae350: Fix XIP config boot failure	Leo Yu-Chi Liang	1	-1/+3
2022-08-11	riscv: cpu: set gp before board_init_f_init_reserve	Nikita Shubin	1	-0/+1
2022-06-23	linker_lists: Rename sections to remove . prefix	Andrew Scull	2	-4/+4
2022-06-06	Migrate CUSTOM_SYS_INIT_SP_ADDR to Kconfig using system-constants.h	Tom Rini	1	-1/+2
2022-03-10	event: Convert arch_cpu_init_dm() to use events	Simon Glass	1	-1/+4
2021-12-02	riscv: Enable SPI flash env for SiFive Unmatched.	Thomas Skibo	1	-0/+13
2021-10-18	riscv: Remove OF_PRIOR_STAGE from RISC-V boards	Ilias Apalodimas	2	-8/+0