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path: root/arch/riscv/cpu/ax25
AgeCommit message (Expand)AuthorFilesLines
2021-03-27cpu: Rename SPL_CPU_SUPPORT to SPL_CPUSimon Glass1-1/+1
2020-10-26timer: Add _TIMER suffix to Andes PLMT KconfigSean Anderson1-1/+1
2020-09-30riscv: Rework riscv timer driver to only support S-modeSean Anderson1-1/+1
2020-05-18common: Drop net.h from common headerSimon Glass1-0/+1
2020-04-23riscv: ax25: cache: Remove SPL_RISCV_MMODE config checkPragnesh Patel1-8/+8
2019-12-10riscv: ax25: cache: Add SPL_RISCV_MMODE for SPLRick Chen1-14/+46
2019-12-10riscv: ax25: add SPL supportRick Chen1-1/+3
2019-12-02common: Move ARM cache operations out of common.hSimon Glass1-0/+1
2019-12-02common: Move some cache and MMU functions out of common.hSimon Glass2-0/+2
2019-09-03riscv: cache: use CCTL to flush d-cacheRick Chen1-9/+13
2019-09-03riscv: cache: Flush L2 cache before jump to linuxRick Chen1-0/+17
2019-09-03riscv: ax25: add imply v5l2 cache controllerRick Chen1-0/+1
2019-08-26riscv: add run mode configuration for SPLLukas Auer1-3/+3
2019-05-18CONFIG_SPL_SYS_[DI]CACHE_OFF: addTrevor Woerner1-4/+4
2019-04-08riscv: ax25: Andes specific cache shall only support in M-modeRick Chen1-0/+1
2019-04-08riscv: ax25: Add platform-specific Kconfig optionsRick Chen1-0/+6
2019-01-15riscv: move the AX25-specific implementation of flush_dcache_allLukas Auer1-0/+22
2018-12-18riscv: ax25: Hide the ax25-specific Kconfig optionBin Meng2-11/+18
2018-11-26riscv: cache: Implement i/dcache [status, enable, disable]Rick Chen4-0/+107
2018-10-03riscv: Move do_reset() to a common placeBin Meng1-9/+0
2018-10-03riscv: Make start.S available for all targetsBin Meng2-294/+0
2018-10-03riscv: Move the linker script to the CPU root directoryBin Meng1-90/+0
2018-08-20riscv: Include bss subsections in linker scriptAlexander Graf1-1/+1
2018-07-25efi_loader: Rename sections to allow for implicit dataAlexander Graf1-10/+16
2018-05-29riscv: cpu: nx25: Rename as ax25Rick Chen4-0/+416