rocket-tools/riscv-gnu-toolchain/qemu/roms/u-boot.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-02-17	riscv: Rename Andes cpu and board names	Leo Yu-Chi Liang	1	-15/+0
2023-02-17	configs: ae350: Enable v5l2 cache for AE350 platforms in SPL	Yu Chien Peter Lin	1	-0/+1
2023-02-17	riscv: Remove redundant Kconfig "RISCV_NDS_CACHE"	Leo Yu-Chi Liang	1	-10/+0
2022-11-03	riscv: Rename Andes PLIC to PLICSW	Yu Chien Peter Lin	1	-1/+1
2021-03-27	cpu: Rename SPL_CPU_SUPPORT to SPL_CPU	Simon Glass	1	-1/+1
2020-10-26	timer: Add _TIMER suffix to Andes PLMT Kconfig	Sean Anderson	1	-1/+1
2020-09-30	riscv: Rework riscv timer driver to only support S-mode	Sean Anderson	1	-1/+1
2019-12-10	riscv: ax25: add SPL support	Rick Chen	1	-1/+3
2019-09-03	riscv: ax25: add imply v5l2 cache controller	Rick Chen	1	-0/+1
2019-08-26	riscv: add run mode configuration for SPL	Lukas Auer	1	-3/+3
2019-04-08	riscv: ax25: Andes specific cache shall only support in M-mode	Rick Chen	1	-0/+1
2019-04-08	riscv: ax25: Add platform-specific Kconfig options	Rick Chen	1	-0/+6
2018-12-18	riscv: ax25: Hide the ax25-specific Kconfig option	Bin Meng	1	-5/+12
2018-11-26	riscv: cache: Implement i/dcache [status, enable, disable]	Rick Chen	1	-0/+7