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2011-10-05image: push default arch values to arch headersMike Frysinger1-0/+4
This pushes the ugly duplicated arch ifdef lists we maintain in various image related files out to the arch headers themselves. Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Tested-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-10-05POST: add post_log_res field for post results in global dataValentin Longchamp1-0/+1
The current post_log_word in global data is currently split into 2x 16 bits: half for the test start, half for the test success. Since we alredy have more than 16 POST tests defined and more could be defined, this may result in an overflow and the post_output_backlog would not work for the tests defined further of these 16 positions. An additional field is added to global data so that we can now support up to 32 (depending of architecture) tests. The post_log_word is only used to record the start of the test and the new field post_log_res for the test success (or failure). The post_output_backlog is for this change also adapted. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
2011-10-05console: Implement pre-console bufferGraeme Russ1-0/+3
Allow redirection of console output prior to console initialisation to a temporary buffer. To enable this functionality, the board (or arch) must define: - CONFIG_PRE_CONSOLE_BUFFER - Enable pre-console buffer - CONFIG_PRE_CON_BUF_ADDR - Base address of pre-console buffer - CONFIG_PRE_CON_BUF_SZ - Size of pre-console buffer (in bytes) The pre-console buffer will buffer the last CONFIG_PRE_CON_BUF_SZ bytes Any earlier characters are silently dropped.
2011-10-04Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk43-168/+2283
* 'master' of git://git.denx.de/u-boot-mpc85xx: powerpc/p3060: Add SoC related support for P3060 platform powerpc/85xx: Add support for setting up RAID engine liodns on P5020 powerpc/85xx: Refactor some defines out of corenet_ds.h fm-eth: Add ability for board code to disable a port powerpc/mpc8548: Add workaround for erratum NMG_LBC103 powerpc/mpc8548: Add workaround for erratum NMG_DDR120 powerpc/mpc85xxcds: Fix PCI speed powerpc/mpc8548cds: Fix booting message powerpc/p4080: Add support for secure boot flow powerpc/85xx: Add Secure Boot support on P1010RDB for NOR, NAND & SPIFLASH powerpc/85xx: Add PBL & SECUREBOOT support on P3041/P5020DS boards powerpc/p2041rdb: remove watch dog related codes powerpc/p2041rdb: updated description of cpld command powerpc/p2041rdb: add more ddr frequencies support powerpc/p2041rdb: set sysclk according to status of physical switch SW1 powerpc/p2041rdb: update cpld reset command according to CPLD 2.0 powerpc/mpc8349emds: Migrate from spd_sdram to unified DDR driver powerpc/mpc83xx: Migrate from spd_sdram to unified DDR driver powerpc/mpc8xxx: Add DDR2 to unified DDR driver powerpc/mpc8xxx: Fix picos_to_mclk() and get_memory_clk_period_ps() powerpc/mpc8xxx: Add SPD EEPROM address for single controller 2 slots powerpc/mpc8xxx: Fix DDR code for empty first DIMM slot and enable DQS_en powerpc/85xx: Refactor P2041RDB to use common p_corenet files powerpc/85xx: refactor common P-Series CoreNet files for FSL boards powerpc/85xx: Enable CMD_REGINFO on corenet boards powerpc/85xx: p2041rdb - Remove unused 'execute' perm in TLB entries powerpc/85xx: Fix USB protocol definitions for P1020RDB powerpc/corenet_ds: Use separated speed tables for UDIMM and RDIMM powerpc/mpc8xxx: Move DDR RCW overriding to common code powerpc/mpc8xxx: Extend CWL table powerpc/85xx: Cleanup how SVR_MAJ() is defined on MPC8536 powerpc/85xx: Cleanup extern in corenet_ds board code powerpc/p2041rdb: Add ethernet support on P2041RDB board powerpc/85xx: Add networking support to P1023RDS powerpc/hydra: Add ethernet support on P5020/P3041 DS boards powerpc/85xx: Add FMan ethernet support to P4080DS powerpc/85xx: Add support for FMan ethernet in Independent mode powerpc/mpc8548cds: Cleanup mpc8548cds.c powerpc/mp: add support for discontiguous cores powerpc/85xx: corenet_ds - Remove unused 'execute' perm in TLB entries fdt: Add new fdt_create_phandle helper fdt: Rename fdt_create_phandle to fdt_set_phandle powerpc/85xx: Fix compile warnings/errors if CONFIG_SYS_DPAA_FMAN isn't set fsl_ifc: Add the workaround for erratum IFC A-003399(enabled on P1010) powerpc/P1010: Add workaround for erratum P1010-A003549 (related to IFC) fsl_ifc: Add the workaround for erratum IFC-A002769 (enable on P1010) powerpc/85xx: Expanding the window of CCSRBAR in AS=1 from 4k to 1M powerpc/85xx: Add NAND/NAND_SPL support to P1010RDB nand: Freescale Integrated Flash Controller NAND support powerpc/85xx: Add basic support for P1010RDB powerpc/85xx: Add support for new P102x/P2020 RDB style boards powerpc/85xx: relocate CCSR before creating the initial RAM area powerpc/85xx: introduce and document CONFIG_SYS_CCSRBAR macros powerpc/85xx: Enable internal USB UTMI PHY on p204x/p3041/p50x0 powerpc/85xx: Add ULPI and UTMI USB Phy support for P1010/P1014
2011-10-03powerpc/p3060: Add SoC related support for P3060 platformShengzhou Liu8-1/+293
Add P3060 SoC specific information:cores setup, LIODN setup, etc The P3060 SoC combines six e500mc Power Architecture processor cores with high-performance datapath acceleration architecture(DPAA), CoreNet fabric infrastructure, as well as network and peripheral interfaces. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-03powerpc/85xx: Add support for setting up RAID engine liodns on P5020Kumar Gala5-2/+69
Add support for Job Queue/Ring LIODN for the RAID Engine on P5020. Each Job Queue/Ring combo needs one id assigned for a total of 4 (2 JQs/2 Rings per JQ). This just handles RAID Engine in non-DPAA mode. Signed-off-by: Santosh Shukla <santosh.shukla@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-03powerpc/mpc8548: Add workaround for erratum NMG_LBC103Kumar Gala3-0/+7
The erratum NMG_LBC103 is LBIU3 in MPC8548 errata document. Any local bus transaction may fail during LBIU resynchronization process when the clock divider [CLKDIV] is changing. Ensure there is no transaction on the local bus for at least 100 microseconds after changing clock divider LCRR[CLKDIV]. Refer to the erratum LBIU3 of mpc8548. Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-03powerpc/mpc8548: Add workaround for erratum NMG_DDR120Kumar Gala3-0/+25
Erratum NMG_DDR120 (DDR19 in MPC8548 errata document) applies to some early version silicons. The default settings of the DDR IO receiver biasing may not work at cold temperature. When a failure occurs, a DDR input latches an incorrect value. The workaround will set the receiver to an acceptable bias point. Signed-off-by: Gong Chen Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-03powerpc/p4080: Add support for secure boot flowRuchika Gupta5-3/+118
Pre u-boot Flow: 1. User loads the u-boot image in flash 2. PBL/Configuration word is used to create LAW for Flash at 0xc0000000 (Please note that ISBC expects all these addresses, images to be validated, entry point etc within 0 - 3.5G range) 3. ISBC validates the u-boot image, and passes control to u-boot at 0xcffffffc. Changes in u-boot: 1. Temporarily map CONFIG_SYS_MONITOR_BASE to the 1M CONFIG_SYS_PBI_FLASH_WINDOW in AS=1. (The CONFIG_SYS_PBI_FLASH_WINDOW is the address map for the flash created by PBL/configuration word within 0 - 3.5G memory range. The u-boot image at this address has been validated by ISBC code) 2. Remove TLB entries for 0 - 3.5G created by ISBC code 3. Remove the LAW entry for the CONFIG_SYS_PBI_FLASH_WINDOW created by PBL/configuration word after switch to AS = 1 Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Kuldip Giroh <kuldip.giroh@freescale.com> Acked-by: Wood Scott-B07421 <B07421@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-01sbc82xx: delete support for obsolete SBC8240/SBC8260Paul Gortmaker1-1/+1
The EST SBC8260 is over 10 years old, and the SBC8240 older than that. With the tiny amount of RAM (by today's standards), there really isn't anyone interested in running the latest U-boot on these EOL products anymore. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> CC: jon.diekema@smiths-aerospace.com
2011-10-01console: Squelch pre-console output in console functionsGraeme Russ2-32/+16
There are some locations in the code which anticipate printf() being called before the console is ready by squelching printf() on gd->have_console. Move this squelching into printf(), vprintf(), puts() and putc(). Also make tstc() and getc() return 0 if console is not yet initialised Signed-off-by: Graeme Russ <graeme.russ@gmail.com> Tested-by: Simon Glass <sjg@chromium.org>
2011-09-29powerpc/mpc83xx: Migrate from spd_sdram to unified DDR driverYork Sun9-17/+234
Unified DDR driver is maintained for better performance, robustness and bug fixes. Upgrading to use unified DDR driver for MPC83xx takes advantage of overall improvement. It requires changes for board files to customize platform-dependent parameters. To utilize the unified DDR driver, a board needs to define CONFIG_FSL_DDRx in the header file. No more boards will be accepted without such definition. Note: the workaround for erratum DDR6 for the very old MPC834x Rev 1.0/1.1 and MPC8360 Rev 1.1/1.2 parts is not migrated to unified driver. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29powerpc/mpc8xxx: Add DDR2 to unified DDR driverYork Sun3-17/+235
DDR2 has different ODT table and values. Adding table according to Samsung application note. Fix additive latency calculation to avoid interger underflow. Also converted typedef dynamic_odt_t to struct dynamic_odt. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29powerpc/mpc8xxx: Fix picos_to_mclk() and get_memory_clk_period_ps()York Sun1-15/+11
Reduce the calculation error to 1ps. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29powerpc/mpc8xxx: Add SPD EEPROM address for single controller 2 slotsYork Sun1-4/+7
The two slots on the same controller have different addresses. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29powerpc/mpc8xxx: Fix DDR code for empty first DIMM slot and enable DQS_enYork Sun2-9/+14
Check second DIMM slot in case the first one is empty. Honor DQS enable option for SDRAM mode register. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29powerpc/mpc8xxx: Move DDR RCW overriding to common codeYork Sun1-0/+15
DDR RCW varies at different speeds. It is common for all platform. Move it out from corenet_ds. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29powerpc/mpc8xxx: Extend CWL tableYork Sun1-2/+16
Extend CAS write Latency (CWL) table to comply with DDR3 spec Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29powerpc/85xx: Cleanup how SVR_MAJ() is defined on MPC8536Kumar Gala2-3/+4
The MPC8536 seems to use only 3 bits for the major revision field in the SVR rather than the 4 bits used by all other processors. The most significant bit is used as a mfg code on MPC8536. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29powerpc/85xx: Add networking support to P1023RDSRoy Zang1-0/+4
The P1023 has two 1G ethernet controllers the first can run in SGMII, RGMII, or RMII. The second can only do SGMII & RGMII. We need to setup a for SoC & board registers based on our various configuration for ethernet to function properly on the board. Removed CONFIG_SYS_FMAN_FW as its not used anywhere. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Lei Xu <B33228@freescale.com> Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29powerpc/85xx: Add support for FMan ethernet in Independent modeKumar Gala7-12/+741
The Frame Manager (FMan) on QorIQ SoCs with DPAA (datapath acceleration architecture) is the ethernet contoller block. Normally it is utilized via Queue Manager (Qman) and Buffer Manager (Bman). However for boot usage the FMan supports a mode similar to QE or CPM ethernet collers called Independent mode. Additionally the FMan block supports multiple 1g and 10g interfaces as a single entity in the system rather than each controller being managed uniquely. This means we have to initialize all of Fman regardless of the number of interfaces we utilize. Different SoCs support different combinations of the number of FMan as well as the number of 1g & 10g interfaces support per Fman. We add support for the following SoCs: * P1023 - 1 Fman, 2x1g * P4080 - 2 Fman, each Fman has 4x1g and 1x10g * P204x/P3041/P5020 - 1 Fman, 5x1g, 1x10g Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Dai Haruki <dai.haruki@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com> Signed-off-by: Lei Xu <B33228@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29powerpc/mp: add support for discontiguous coresTimur Tabi6-26/+61
Some SOCs have discontiguously-numbered cores, and so we can't determine the valid core numbers via the FRR register any more. We define CPU_TYPE_ENTRY_MASK to specify a discontiguous core mask, and helper functions to process the mask and enumerate over the set of valid cores. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29fdt: Rename fdt_create_phandle to fdt_set_phandleKumar Gala1-1/+1
The old fdt_create_phandle didn't actually create a phandle it just set one. We'll introduce a new helper that actually does creation. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Gerald Van Baren <vanbaren@cideas.com>
2011-09-29powerpc/85xx: Fix compile warnings/errors if CONFIG_SYS_DPAA_FMAN isn't setKumar Gala2-1/+8
Add ifdef protection around fman specific code related to device tree clock setup. If we dont have CONFIG_SYS_DPAA_FMAN defined we shouldn't be executing this code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29fsl_ifc: Add the workaround for erratum IFC A-003399(enabled on P1010)Poonam Aggrwal5-0/+95
Issue: Address masking doesn't work properly. When sum of the base address, defined by BA, and memory bank size, defined by AM, exceeds 4GB (0xffff_ffff) then AMASKn[AM] doesn't mask CSPRn[BA] bits. Impact: This will impact booting when we are reprogramming CSPR0(BA) and AMASK0(AMASK) while executing from NOR Flash. Workaround: Re-programming of CSPR(BA) and AMASK is done while not executing from NOR Flash. The code which programs the BA and AMASK is executed from L2-SRAM. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29powerpc/P1010: Add workaround for erratum P1010-A003549 (related to IFC)Poonam Aggrwal3-0/+17
Issue: Peripheral connected to IFC_CS3 may hamper booting from IFC. Impact: Boot from IFC may not be successful if IFC_CS3 is used. Workaround: If IFC_CS3 is used, gate IFC_CS3 while booting from NAND or NOR. Also Software should select IFC_CS3 using PMUXCR[26:27] = 0x01. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29fsl_ifc: Add the workaround for erratum IFC-A002769 (enable on P1010)Poonam Aggrwal3-0/+10
Issue: The NOR-FCM does not support access to unaligned addresses for 16 bit port size Impact: When 16 bit port size is used, accesses not aligned to 16 bit address boundary will result in incorrect data Workaround: The workaround is to switch to GPCM mode for NOR Flash access. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29powerpc/85xx: Expanding the window of CCSRBAR in AS=1 from 4k to 1MPoonam Aggrwal1-3/+4
For an IFC Erratum (A-003399) we will need to access IFC registers in cpu_init_early_f() so expand the TLB covering CCSR to 1M. Since we need a TLB to cover 1M we move to using TLB1 array for all the early mappings so we can cover various sizes beyond 4k. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29nand: Freescale Integrated Flash Controller NAND supportDipen Dudhat3-7/+27
Add NAND support (including spl) on IFC, such as is found on the p1010. Note that using hardware ECC on IFC with small-page NAND (which is what comes on the p1010rdb reference board) means there will be insufficient OOB space for JFFS2, since IFC does not support 1-bit ECC. UBI should work, as it does not use OOB for anything but ECC. When hardware ECC is not enabled in CSOR, software ECC is now used. Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> [scottwood@freescale.com: ECC rework and misc fixes] Signed-off-by: Scott Wood <scottwood@freescale.com>
2011-09-29powerpc/85xx: relocate CCSR before creating the initial RAM areaTimur Tabi2-58/+234
Before main memory (DDR) is initialized, the on-chip L1 cache is used as a memory area for the stack and the global data (gd_t) structure. This is called the initial RAM area, or initram. The L1 cache is locked and the TLBs point to a non-existent address (so that there's no chance it will overlap main memory or any device). The L1 cache is also configured not to write out to memory or the L2 cache, so everything stays in the L1 cache. One of the things we might do while running out of initram is relocate CCSR. On reset, CCSR is typically located at some high 32-bit address, like 0xfe000000, and this may not be the best place for CCSR. For example, on 36-bit systems, CCSR is relocated to 0xffe000000, near the top of 36-bit memory space. On some future Freescale SOCs, the L1 cache will be forced to write to the backing store, so we can no longer have the TLBs point to non-existent address. Instead, we will point the TLBs to an unused area in CCSR. In order for this technique to work, CCSR needs to be relocated before the initram memory is enabled. Unlike the original CCSR relocation code in cpu_init_early_f(), the TLBs we create now for relocating CCSR are deleted after the relocation is finished. cpu_init_early_f() will still need to create a TLB for CCSR (at the new location) for normal U-Boot purposes. This is done to keep the impact to existing U-Boot code minimal and to better isolate the CCSR relocation code. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29powerpc/85xx: introduce and document CONFIG_SYS_CCSRBAR macrosTimur Tabi1-0/+39
Introduce the CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW macros, which contain the high and low portions of CONFIG_SYS_CCSRBAR_PHYS. This is necessary for the assembly-language code that relocates CCSR, since the assembler does not understand 64-bit constants. CONFIG_SYS_CCSRBAR_PHYS is automatically defined from the CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW macros, so it should not be defined in a board header file. Similarly, CONFIG_SYS_CCSRBAR_DEFAULT is defined for each SOC in config_mpc85xx.h, so it should also not be defined in the board header file. CONFIG_SYS_CCSR_DO_NOT_RELOCATE is a "short-cut" macro that guarantees that CONFIG_SYS_CCSRBAR_PHYS is set to the same value as CONFIG_SYS_CCSRBAR_DEFAULT, and so CCSR will not be relocated. Since CONFIG_SYS_CCSRBAR_DEFAULT is locked to a fixed value, multi-stage U-Boot builds (e.g. NAND) are required to relocate CCSR only during the last stage (i.e. the "real" U-Boot). All other stages should define CONFIG_SYS_CCSR_DO_NOT_RELOCATE to ensure that CCSR is not relocated. README is updated with descriptions of all the CONFIG_SYS_CCSRBAR_xxx macros. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29powerpc/85xx: Enable internal USB UTMI PHY on p204x/p3041/p50x0Kumar Gala1-0/+5
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29powerpc/85xx: Add ULPI and UTMI USB Phy support for P1010/P1014Ramneek Mehresh1-0/+2
Add UTMI and ULPI PHY support for USB controller on qoriq series of processors with internal UTMI PHY implemented, for example P1010/P1014 - Use both getenv() and hwconfig to get USB phy type till getenv() is depricated - Introduce CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY to specify if soc has internal UTMI phy Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Acked-by: Remy Bohmer <linux@bohmer.net> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-19ppc4xx: Flush dcache after DDR2 autocalibration with caches onStefan Roese1-0/+7
Flush the dcache before removing the TLB with caches enabled. Otherwise this might lead to problems later on, e.g. while booting Linux (as seen on ICON-440SPe). Signed-off-by: Stefan Roese <sr@denx.de>
2011-09-19Fix incorrect array size of phy settings for 405EXWeirich, Bernhard1-1/+1
Change bd_t->bi_phy* arrays from 1 to 2 for PPC405EX since 405EX has 2 ethernet interfaces. Signed-off-by: Bernhard Weirich <bernhard.weirich@riedel.net> Signed-off-by: Stefan Roese <sr@denx.de>
2011-09-05Flush cache after the OS image is loaded into the memory.Diana CRACIUN1-14/+6
Since we are loading an executable image into memory we need flush it out of the cache to possible maintain coherence on CPUs with split instruction and data caches. We do this for other executable image loading command. On PowerPC once we do this we no longer need to explicitly flush the dcache on multi-core systems in the BOOTM_STATE_OS_PREP phase. We now treat the BOOTM_STATE_OS_PREP as a no-op to maintain backwards compatibility with the bootm subcommand. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Diana CRACIUN <Diana.Craciun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-08-04Convert ISO-8859 files to UTF-8Albert ARIBAUD1-1/+1
There was a mix of UTF-8 and ISO-8859 files in the U-Boot source tree, which could cause issues with the patchwork review system. This commit converts all ISO-8859 files to UTF-8. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2011-08-04hwmon: do not init sensors on startupHeiko Schocher1-3/+0
The U-Boot Design Principles[1] clearly say: Initialize devices only when they are needed within U-Boot, i.e. don't initialize the Ethernet interface(s) unless U-Boot performs a download over Ethernet; don't initialize any IDE or USB devices unless U-Boot actually tries to load files from these, etc. (and don't forget to shut down these devices after using them - otherwise nasty things may happen when you try to boot your OS). So, do not initialize and read the sensors on startup. Signed-off-by: Heiko Schocher <hs@denx.de> cc: Wolfgang Denk <wd@denx.de> cc: Holger Brunck <holger.brunck@keymile.com>
2011-08-04video: Add SHARP LQ084S3LG01 LCD support on P1022DSTimur Tabi1-1/+1
The SHARP LQ084S3LG01 is a TFT LCD used on the P1022DS (revision "C") board. This device only supports 800x600 resolution, so if that resolution is selected, assume that this is the device. The device is attached to the LVDS port on the P1022DS board. The existing 800x600 entry (for the PDM360NG board) is actually 800x480, so we fix that. To support two different 800x resolutions, the Y-resolution is now passed to fsl_diu_init() and both values are used to pick the proper fb_videomode structure. The data for the 800x600 video mode is originally from Jiang Yutang. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Jiang Yutang <b14898@freescale.com>
2011-07-29powerpc/8xxx: Remove dependency on <usb.h>Kumar Gala1-4/+3
We used <usb.h> for USB_MAX_DEVICE. However this requires we actual build in support for USB into u-boot (which should not be required for device tree fixup). At this time no FSL SoC that utilizies this code (83xx/85xx) has more than 2 USB controllers. So we replace USB_MAX_DEVICE with a local define FSL_MAX_NUM_USB_CTRLS. If/when a device shows up with more than 2 controllers we can easily bump this value or refactor into a proper define per SoC. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-29powerpc/85xx: enable USB2 gadget mode for corenet ds boardShaohui Xie1-2/+0
to make USB2 worked in gadget mode, we need to set it's 'dr_mode' to 'peripheral' in hwconfig, but driver starts scan from 'usb1', it'll break out if it cannot find 'usb1', so drop the 'else' clause to make driver scan all the 'usbx'. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-29powerpc/85xx: verify the device tree before booting LinuxTimur Tabi2-0/+93
Introduce ft_verify_fdt(), a function that is called after the device tree has been fixed up, that displays warning messages if there is a mismatch between the physical addresses of some devices that U-Boot has configured with what the device tree says the addresses are. This is a particular problem when booting a 36-bit device tree from a 32-bit U-Boot (or vice versa), because the physical address of CCSR is wrong in the device tree. When the operating system boots, no messages are displayed, so the user generally has no idea what's wrong. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-29MPC8xxx: drop redundant boot messagesWolfgang Denk1-1/+1
Current code would print RAM size information like this: DRAM: DDR: 256 MiB (DDR1, 64-bit, CL=2, ECC off) Turn a number of printf()s into debug() to get rid of the redundant "DDR: " string like this: DRAM: 256 MiB (DDR1, 64-bit, CL=2, ECC off) Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-29powerpc/85xx: Cleanup handling of PVR detection for e500/e500mc/e5500Kumar Gala2-19/+17
At some point we broke the detection of e500v1 class cores. Fix that and simply the code to just utilize PVR_VER() to have a single case statement. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-29powerpc/85xx: Fix up clock_freq property in CAN node of dtsBhaskar Upadhaya1-0/+3
Fix up the device tree property associated with the Flexcan clock frequency. This property is used to calculate the bit timing parameters for Flexcan. Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-29powerpc/85xx: provide 85xx flush_icache for cmd_cacheMatthew McClintock1-0/+2
This provides a function that will override the weak function flush_icache to let 85xx boards to flush the icache cc: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Matthew McClintock <msm@freescale.com>
2011-07-29powerpc/85xx: Handle the lack of L2 cache on P2040/P2040EKumar Gala3-9/+37
The P2040/P2040E have no L2 cache. So we utilize the SVR to determine if we are one of these devices and skip the L2 init code in cpu_init.c and release. For the device tree we skip the updating of the L2 cache properties but we still update the chain of caches so the CPC/L3 node can be properly updated. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-29powerpc/85xx: Add support for P2041[e] XAUI in SERDESKumar Gala1-5/+21
We add XAUI_FM1 into the SERDES tables for P2041[e] devices. However for the P2040[e] devices that dont support XAUI we handle this at runtime via SVR checks. If we are on a P2040[e] device the SERDES functions will behave as follows: is_serdes_prtcl_valid() will always report invalid if prtcl passed in is XAUI_FM1. serdes_get_prtcl() will report NONE if the prtcl in the table is set to XAUI_FM1. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-29powerpc/85xx: Rename P2040 id & SERDES to P2041Kumar Gala3-3/+3
P2041 is the superset part that covers both P2040 & P2041. The only difference between the two devices is that P2041 supports 10g/XAUI and has an L2 cache. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-29powerpc/85xx: Adding configuration for DCSRCR to enable 32M accessStephen George2-1/+17
Configuring DCSRCR to define the DCSR space to be 1G instead of the default 4M. DCSRCR only allows selection of either 4M or 1G. Most DCSR registers are within 4M but the Nexus trace buffer is located at offset 16M within the DCSR. Configuring the LAW to be 32M to allow access to the Nexus trace buffer. No TLB modification is required since accessing the Nexus trace buffer from within u-boot is not required. Signed-off-by: Stephen George <stephen.george@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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