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2021-02-02common: Drop asm/global_data.h from common headerSimon Glass1-0/+1
Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
2020-07-18mips: sync asm/mipsregs.h with Linux 5.7Daniel Schwierzeck3-194/+1101
Sync asm/mipsregs.h with Linux 5.7. Also replace the custom symbols EBASE_CPUNUM and EBASE_WG with the according symbols from Linux. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
2020-07-18mips: sync asm/addrspace.h with Linux 5.7Daniel Schwierzeck1-12/+2
Sync asm/addrspace.h with Linux 5.7 Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
2020-07-18mips: sync asm/asm.h with Linux 5.7Daniel Schwierzeck1-120/+10
Sync asm/asm.h with Linux 5.7. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
2020-07-18mips: remove deprecated UNCACHED_SDRAM() macroDaniel Schwierzeck1-13/+0
This macro only served as a wrapper for CKSEG1ADDR() with an exception for CONFIG_TB0229. CONFIG_TB0229 doesn't exist, thus use CKSEG1ADDR() directly. This also prepares for an upcoming asm header sync with Linux. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
2020-07-18mips: cache: Allow using CONFIG_MIPS_L2_CACHE without CONFIG_MIPS_CMStefan Roese1-0/+12
This patch enables the usage of CONFIG_MIPS_L2_CACHE without CONFIG_MIPS_CM, which is what is needed for the newly added Octeon platform. Signed-off-by: Stefan Roese <sr@denx.de>
2020-07-18mips: reloc: Change R_MIPS_NONE to catch pre-reloc BSS usageStefan Roese1-1/+1
This patch changes the R_MIPS_NONE define from 0 to a magic value. This makes it possible to better detect any forbidden pre-relocation usage of BSS variables, as they are often zero'ed and then relocation is stopped too early. Additionally the error message is improved to also print the faulting address. This helps finding the root-cause for this breakage by comparing this address with the values in System.map. This patch helps a lot when working on pre-relocation code, like the Octeon DDR init code, where such variables have hit me multiple times now. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com>
2020-07-18mips: traps: Set WG bit in EBase register on OcteonStefan Roese1-0/+1
WG (bit 11) needs to be set on Octeon to enable writing bits 63:30 of the exception base register. Signed-off-by: Stefan Roese <sr@denx.de>
2020-05-18common: Drop linux/bitops.h from common headerSimon Glass2-0/+2
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop net.h from common headerSimon Glass1-0/+2
Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-27mips: add a mtmips-specific field to architecture-specific global dataWeijie Gao1-0/+3
SoCs of mtmips can use different CPU frequencies depending on the HW/SW configurations. For example mt7628 uses 580MHz clock if the input xtal frequency is 40MHz, and 575MHz clock if the xtal is 25MHz. Upon cold boot the CPU uses the xtal frequency directly. So hardcoding the timer frequency (half of the CPU frequency) in CONFIG_SYS_MIPS_TIMER_FREQ is not a good idea for this case. This patch adds a mtmips-specific field timer_freq to arch_global_data. This field will be used later in mtmips-specific get_tbclk() to provide accurate timer frequency in different boot stage. Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2020-04-27mips: add support to restore exception vector base before booting linuxWeijie Gao1-0/+2
In U-Boot the exception vector base will be moved to top of memory, to be used to display register dump when exception occurs. But some old linux kernel does not honor the base set in CP0_EBASE. A modified exception vector base will cause kernel crash. This patch adds an option to enable reset exception vector base to its previous value, or a user configured value before booting linux kernel. Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2020-02-20dma-mapping: add <asm/dma-mapping.h> for all architecturesMasahiro Yamada1-0/+1
To avoid "asm/dma-mapping.h: No such file or directory" error, we need something. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-12-19mips: Add SPL headerPaul Burton1-0/+33
Add header with SPL boot mode and type definitions. Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
2018-12-19MIPS: Allow to prefetch and lock instructions into cacheGregory CLEMENT1-0/+19
This path add a new helper allowing to prefetch and lock instructions into cache. This is useful very early in the boot when no RAM is available yet. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-12-19MIPS: move create_tlb() in an proper header: mipsregs.hGregory CLEMENT1-0/+11
Export create_tlb() as an inline function in mipsregs.h. It allows to remove the declaration of the function from the board files. Then it will allow also to use this function very early in the boot when the stack is not usable. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-12-19MIPS: remove local_irq_[save|restore] from CP0 macrosDaniel Schwierzeck1-7/+0
With moving write_on_tlb() to arch/mips/include/asm/mipsregs.h there are now compiler warnings when some generic code includes asm/io.h. This happens for example when enabling OF live tree. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-11-20MIPS: drop asm/const.hBaruch Siach1-27/+0
Commit 86f21c96f467368 (mips: Use common _AC macro now.) removed the _AC definition from const.h. All other macros defined in const.h are not used anywhere, and there is now no user of this header. Remove this header. Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-11-20Use _AC and UL macros from linux/const.hBaruch Siach1-1/+1
Drop the _AC and UL macros from common.h. Linux headers is the original source of this macro, so keep its definition in the same header. Update existing users of these macros to include const.h directly. Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Rick Chen <rick@andestech.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-11-18mips: mt76xx: Enable watchdog supportStefan Roese1-0/+2
This patch enables and starts the watchdog on the MT7620 platform. Currently the WD timeout is configured to 60 seconds. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> [fixed build error due to missing function prototype arch_misc_init] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-11-14mips: Implement {in, out}_{le, be}_{16, 32, 64} and {in, out}_8Mario Six1-0/+22
MIPS is the only architecture currently supported by U-Boot that does not implement any of the in/out register access functions. To have a interface that is useable across architectures, add the functions to the MIPS architecture (implemented using the __raw_write and __raw_read functions). Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-09-25mips: use asm-generic/atomic.hChris Packham1-43/+1
Make use of asm-generic/atomic.h. Signed-off-by: Chris Packham <judge.packham@gmail.com>
2018-09-22mips: Add arch/mips/include/asm/atomic.hStefan Roese1-0/+54
This is needed for the UBIFS support. The file is a copy of arch/xtensa/include/asm/atomic.h Signed-off-by: Stefan Roese <sr@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-09-10arch: types.h: factor out fixed width typedefs to int-ll64.hMasahiro Yamada1-34/+2
All architectures have the same definition for s8/16/32/64 and u8/16/32/64. Factor out the duplicated code into <asm-generic/int-ll64.h>. BTW, Linux unified the kernel space definition into int-ll64.h a few years ago as you see in Linux commit 0c79a8e29b5f ("asm/types.h: Remove include/asm-generic/int-l64.h"). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-08-08mips: au1x00: Remove support for these SoCsTom Rini1-3/+3
The only platform left for the AU1x00 SoCs was the pb1x00 platform, an apparent clone of the dbau1x00 platform. As pb1x00 had no listed maintainer I am assuming that it is also orphaned. Remove this platform and then remove the unused SoC support. Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-05-07SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini37-76/+37
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2017-11-28MIPS: Clear instruction hazards in flush_cache()Paul Burton1-0/+13
When writing code, for example during relocation, we ensure that the icache has a coherent view of the new instructions with a call to flush_cache(). This handles the bulk of the work to ensure the new instructions will execute as expected, however it does not ensure that the CPU pipeline doesn't already contain instructions taken from a stale view of the affected memory. This could theoretically be a problem for relocation, but in practice typically isn't because we sync caches for enough code after the entry point of the newly written code that by the time the CPU pipeline might possibly fetch any of it we'll have long ago written it back & invalidated any stale icache entries. This is however a problem for shorter regions of code. In preparation for later patches which write shorter segments of code, ensure any instruction hazards are cleared by flush_cache() by introducing & using a new instruction_hazard_barrier() function which makes use of the jr.hb instruction to clear the hazard. Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: u-boot@lists.denx.de
2017-10-02mips: Use asm-generic/io.hPaul Burton1-11/+6
Convert the mips architecture to make use of the new asm-generic/io.h to provide address mapping functions. As mips actually performs non-identity mapping between physical & virtual addresses we can't simply make use of the generic functions, with the exception of being able to drop our no-op unmap_physmem() and definitions of unused map flags. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2017-07-25MIPS: Stop building position independent codePaul Burton2-0/+31
U-Boot has up until now built with -fpic for the MIPS architecture, producing position independent code which uses indirection through a global offset table, making relocation fairly straightforward as it simply involves patching up GOT entries. Using -fpic does however have some downsides. The biggest of these is that generated code is bloated in various ways. For example, function calls are indirected through the GOT & the t9 register: 8f998064 lw t9,-32668(gp) 0320f809 jalr t9 Without -fpic the call is simply: 0f803f01 jal be00fc04 <puts> This is more compact & faster (due to the lack of the load & the dependency the jump has on its result). It is also easier to read & debug because the disassembly shows what function is being called, rather than just an offset from gp which would then have to be looked up in the ELF to discover the target function. Another disadvantage of -fpic is that each function begins with a sequence to calculate the value of the gp register, for example: 3c1c0004 lui gp,0x4 279c3384 addiu gp,gp,13188 0399e021 addu gp,gp,t9 Without using -fpic this sequence no longer appears at the start of each function, reducing code size considerably. This patch switches U-Boot from building with -fpic to building with -fno-pic, in order to gain the benefits described above. The cost of this is an extra step during the build process to extract relocation data from the ELF & write it into a new .rel section in a compact format, plus the added complexity of dealing with multiple types of relocation rather than the single type that applied to the GOT. The benefit is smaller, cleaner, more debuggable code. The relocate_code() function is reimplemented in C to handle the new relocation scheme, which also makes it easier to read & debug. Taking maltael_defconfig as an example the size of u-boot.bin built using the Codescape MIPS 2016.05-06 toolchain (gcc 4.9.2, binutils 2.24.90) shrinks from 254KiB to 224KiB. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: u-boot@lists.denx.de Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Tested-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2017-06-05mips: Make u-boot-mips.h a private headerSimon Glass1-0/+1
Rather than including this arch-specific header file in common.h, include it from within mips's u-boot.h header. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2017-01-10mips: Use common _AC macro now.Tom Rini1-3/+0
MIPS no longer needs to have its own version of this macro now. Fixes: 2a6713b09b8d ("move UL() macro from armv8/mmu.h into common.h") Signed-off-by: Tom Rini <trini@konsulko.com>
2016-11-30MIPS: Fix map_physmem for cached mappingsPaul Burton1-1/+1
map_physmem should return a pointer that can be used by the CPU to access the given memory - on MIPS simply returning the physical address as it does prior to this patch doesn't achieve that. Instead return a pointer to the memory within (c)kseg0, which matches up consistently with the (c)kseg1 pointer that uncached mappings return via ioremap. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-11-30mips: Let cache.h be included from assembly sourceMarek Vasut1-0/+2
Add ifdef __ASSEMBLY__ around the function prototype to let cache.h be included from assembly code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com>
2016-11-30MIPS: add handling for generic and EJTAG exceptionsDaniel Schwierzeck2-0/+12
Add exception handlers for generic and EJTAG exceptions. Most of the assembly code is imported from Linux kernel and adapted to U-Boot. The exception vector table will be reserved above the stack before U-Boot is relocated. The exception handlers will be installed and activated after relocation in the initr_traps hook function. Generic exceptions are handled by showing a CPU register dump similar to Linux kernel. For example: malta # md 1 00000001: Ooops: $ 0 : 00000000 00000000 00000009 00000004 $ 4 : 8ff7e108 00000000 0000003a 00000000 $ 8 : 00000008 00000001 8ff7cd18 00000004 $12 : 00000002 00000000 00000005 0000003a $16 : 00000004 00000040 00000001 00000001 $20 : 00000000 8fff53c0 00000008 00000004 $24 : ffffffff 8ffdea44 $28 : 90001650 8ff7cd00 00000004 8ffe6818 Hi : 00000000 Lo : 00000004 epc : 8ffe6848 (text bfc28848) ra : 8ffe6818 (text bfc28818) Status: 00000006 Cause : 00000410 (ExcCode 04) BadVA : 8ff9e928 PrId : 00019300 ### ERROR ### Please RESET the board ### EJTAG exceptions are checked for SDBBP and delegated to the SDBBP handler if necessary. Otherwise the debug mode will simply be exited. The SDBBP handler currently prints the contents of registers c0_depc and c0_debug. This could be extended in the future to handle semi-hosting according to the MIPS UHI specification. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Tested-by: Paul Burton <paul.burton@imgtec.com>
2016-11-30MIPS: add asm-offsets for struct pt_regsDaniel Schwierzeck1-0/+5
Import asm-offsets.c from kernel to generate offset for struct pt_regs needed by exception handlers. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-11-30MIPS: fix iand optimize setup of CP0 registersDaniel Schwierzeck1-0/+1
Clear cp0 status while preserving implementation specific bits. Set bits BEV and ERL as the arch specification requires after a reset or soft-reset exception. Extend and fix initialization of watch registers. Check if additional watch register sets are implemented and initialize them too. Initialize cp0 count as early as possible to get the most accurate boot timing. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-10-19efi: Use asmlinkage for EFIAPISimon Glass1-0/+0
This is required for x86 and is also correct for ARM (since it is empty). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2016-09-23Remove arch/${ARCH}/include/asm/errno.hMasahiro Yamada1-1/+0
Unlike Linux, nothing about errno.h is arch-specific in U-Boot. As you see, all of arch/${ARCH}/include/asm/errno.h is just a wrapper of <asm-generic/errno.h>. Actually, U-Boot does not export headers to user-space, so we just have to care about the consistency in the U-Boot tree. Now all of include directives for <asm/errno.h> are gone. Deprecate <asm/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
2016-09-21MIPS: Hang if run on a secondary CPUPaul Burton1-0/+7
Some systems are configured such that multiple CPUs begin running from their reset vector following a system reset. If this occurs then U-Boot will be run on multiple CPUs simultaneously, which causes all sorts of issues as the multiple instances of U-Boot clobber each other. Prevent this from happening by simply hanging with an infinite loop if we run on a CPU whose ID, as determined by GlobalNumber or EBase.CPUNum as appropriate, is non-zero. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21MIPS: Join the coherent domain when a CM is presentPaul Burton1-0/+5
MIPS Linux expects the bootloader to leave the boot CPU a member of the coherent domain when running on a system with a CM, and we will need to do so if we wish to make use of IOCUs to have cache-coherent DMA in U-Boot (and on some systems there is no choice in that matter). When a CM is present, join the coherent domain after completing cache initialisation. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21MIPS: L2 cache supportPaul Burton3-0/+46
This patch adds support for initialising & maintaining L2 caches on MIPS systems. The L2 cache configuration may be advertised through either coprocessor 0 or the MIPS Coherence Manager depending upon the system, and support for both is included. If the L2 can be bypassed then we bypass it early in boot & initialise the L1 caches first, such that we can start making use of the L1 instruction cache as early as possible. Otherwise we initialise the L2 first such that the L1s have no opportunity to generate access to the uninitialised L2. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21MIPS: Map CM Global Control RegistersPaul Burton1-0/+19
Map the Global Control Registers (GCRs) provided by the MIPS Coherence Manager (CM) in preparation for using some of them in later patches. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21MIPS: Preserve Config implementation-defined bitsPaul Burton1-0/+1
The coprocessor 0 Config register includes 9 implementation defined bits, which in some processors do things like enable write combining or other functionality. We ought not to wipe them to 0 during boot. Rather than doing so, preserve their value & only clear the bits standardised by the MIPS architecture. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21MIPS: Probe cache line sizes once during bootPaul Burton2-0/+13
Rather than probing the cache line sizes on every call of any cache maintenance function, probe them once during boot & store the values in the global data structure for later use. This will reduce the overhead of the cache maintenance functions, which isn't a big deal yet but becomes more important once L2 caches which may expose their properties via coprocessor 2 or the CM are supported. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-05-31MIPS: Split I & D cache line size configPaul Burton1-0/+7
Allow L1 Icache & L1 Dcache line size to be specified separately, since there's no architectural mandate that they be the same. The [id]cache_line_size functions are tidied up to take advantage of the fact that the Kconfig entries are always present to simply check them for zero rather than needing to #ifdef on their presence. Signed-off-by: Paul Burton <paul.burton@imgtec.com> [removed CONFIG_SYS_CACHELINE_SIZE in include/configs/pic32mzdask.h] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-05-31MIPS: remove dead code from asm/u-boot-mips.hDaniel Schwierzeck1-18/+3
Those wrappers for linker symbols were once used in the MIPS specific board.c implementation. Since the migration to generic board.c, those wrappers are dead code and can be removed. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-05-31MIPS: Use CPHYSADDR to implement mips32 virt_to_physPaul Burton1-4/+1
Use CPHYSADDR to implement the virt_to_phys function for converting from a virtual to a physical address for MIPS32, much as is already done for MIPS64. This allows for virt_to_phys to work regardless of whether the address being translated is in kseg0 or kseg1, unlike the previous subtraction based approach which only worked for addresses in kseg0. This allows for drivers to provide an address to virt_to_phys without needing to manually ensure that kseg1 addresses are converted to equivalent kseg0 addresses first. This patch is equivalent to this Linux patch currently waiting to be reviewed & merged: https://patchwork.linux-mips.org/patch/12564/ Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-05-27mips: Drop unused code in u-boot.hSimon Glass1-16/+0
Since generic board init is enabled, this is not used. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-05-26mips: Drop JZ4740 remnantsMarek Vasut2-1158/+0
Remove the remnants of JZ4740 support. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com>
2016-05-21mips: add base support for QCA/Atheros ath79 SOCsWills Wang1-0/+6
This patch add some common code for QCA/Atheros ath79 SOCs such as DDR tuning, chip reset and CPU detection. Signed-off-by: Wills Wang <wills.wang@live.com>
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