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2022-01-21Convert CONFIG_AT91_EFLASH to KconfigPatrick Delaunay1-0/+8
This converts the following to Kconfig: CONFIG_AT91_EFLASH Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Eugen Hristev <eugen.hristev@microchip.com>
2022-01-21Convert CONFIG_BOOTP_SERVERIP to KconfigSimon Glass1-0/+1
This converts the following to Kconfig: CONFIG_BOOTP_SERVERIP Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-21Convert CONFIG_TIMESTAMP to KconfigSimon Glass2-0/+2
This converts the following to Kconfig: CONFIG_TIMESTAMP Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-20Merge https://source.denx.de/u-boot/custodians/u-boot-marvellWIP/20Jan2022Tom Rini7-58/+103
- fdt_support: Add fdt_for_each_node_by_compatible() helper macro (Marek) - turris_omnia: Fixup SATA or PCIe nodes at runtime in DT blob (Pali) - pci_mvebu: Add support for Kirkwood PCIe controllers (Pali) - SPL: More verifications for kwbimage in SPL (Pali) - mvebu: Remove comphy_update_map() (Pali) - Minor misc stuff
2022-01-20Merge tag 'doc-2022-04-rc1' of ↵Tom Rini34-84/+84
https://source.denx.de/u-boot/custodians/u-boot-efi Pull request doc-2022-04-rc1 Replace @return by Return: in code comments.
2022-01-20arm: mvebu: spl: Fix 100 column exceedsMarek Behún1-2/+4
Fix 100 column exceeds in arch/arm/mach-mvebu/spl.c. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-20arm: mvebu: spl: Use IS_ENABLED() instead of #ifdef where possibleMarek Behún1-15/+8
Use the preferred if (IS_ENABLED(X)) instead of #ifdef X where possible. There are still places where this is not possible or is more complicated to convert in this file. Leave those be for now. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-20arm: mvebu: spl: Use preferred types u8/u16/u32 instead of uintN_tMarek Behún1-17/+17
Checkpatch warns about using uint32/16/8_t instead of u32/16/8. Use the preferred types. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-20arm: mvebu: spl: Print srcaddr in error messageMarek Behún1-1/+2
Print the wrong srcaddr (spl_image->offset) in error message also for SATA case. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-20arm: mvebu: Check for kwbimage data checksumPali Rohár1-0/+27
Last 4 bytes of kwbimage boot image is checksum. Verify it via the new spl_check_board_image() function which is called by U-Boot SPL after loading kwbimage. Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-20arm: mvebu: Check that kwbimage blockid matches boot modePali Rohár1-9/+26
Each boot mode has its own kwbimage specified by blockid. So check that kwbimage is valid by blockid. Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-20SPL: Add struct spl_boot_device parameter into spl_parse_board_header()Pali Rohár2-1/+2
Add parameter spl_boot_device to spl_parse_board_header(), which allows the implementations to see from which device we are booting and do boot-device-specific checks of the image header. Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-20arm: mvebu: Check that kwbimage offset and blocksize are validPali Rohár1-0/+12
There are certain restrictions for kwbimage offset and blocksize. Validate them. Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-20pci: pci_mvebu: Add support for Kirkwood PCIe controllersPali Rohár2-2/+5
Kirkwood uses macros KW_DEFADR_PCI_MEM and KW_DEFADR_PCI_IO for base address of PCIe mappings. Size of PCIe windows is not defined in any macro yet, so export them in new KW_DEFADR_PCI_MEM_SIZE and KW_DEFADR_PCI_IO_SIZE macros. Kirkwood arch code already maps mbus windows for io and mem, so avoid calling mvebu_mbus_add_window_by_id() function which would try to do duplicate window mapping. Kirkwood PCIe controllers already use "marvell,kirkwood-pcie" DT compatible string, so mark pci_mvebu.c driver as compatible for it. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-20fdt_support: Add fdt_for_each_node_by_compatible() helper macroMarek Behún3-15/+4
Add macro fdt_for_each_node_by_compatible() to allow iterating over fdt nodes by compatible string. Convert various usages of off = fdt_node_offset_by_compatible(fdt, start, compat); while (off > 0) { code(); off = fdt_node_offset_by_compatible(fdt, off, compat); } and similar, to fdt_for_each_node_by_compatible(off, fdt, start, compat) code(); Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-01-19doc: replace @return by Return:Heinrich Schuchardt34-84/+84
Sphinx expects Return: and not @return to indicate a return value. find . -name '*.c' -exec \ sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \; find . -name '*.h' -exec \ sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \; Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-01-19Merge tag 'xilinx-for-v2022.04-rc1' of ↵WIP/19Jan2022Tom Rini3-30/+48
https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2022.04-rc1 gpio: - Add modepin driver net: - Save random mac addresses to eth variable zynqmp gem: - Add support for mdio bus DT description - Add support for reset and SGMII phy configuration - Reduce timeout for MDIO accesses zynqmp clk: - Fix clock handling for gem and usb phy: - Add zynqmp phy/serdes driver serial: - Add one missing compatible string microblaze: - Symbol alignement - SPL fixups - Code cleanups zynqmp: - Various dt changes, DP pre-reloc, gem resets, gem clocks - Switch SOM to shared psu configuration - Move dcache handling to firmware driver - Workaround gmii2rgmii DT description issue - Enable broadcasts again - Change firmware enablement logic - Small adjustement in firmware driver versal: - Support new mmc@ DT nodes - Fix run time variable handling - Add missing I2C_PMC ID for power domain
2022-01-19Merge https://source.denx.de/u-boot/custodians/u-boot-samsungTom Rini1-3/+3
- Updates for a{3,7}y17lte platforms
2022-01-19arm64: zynqmp: Change firmware dependencyMichal Simek1-2/+2
In case of mini U-Boot configurations there is no need to enable firmware driver which just consume space for nothing. That's why add an option to disable it. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/d439399160ff3374f2b39f54f7dd70fa8c8bfea0.1642162121.git.michal.simek@xilinx.com
2022-01-19arm64: xilinx: dts: Add dma properties to fix dtbs_check warningsShravya Kumbham1-16/+32
Update dma name and add #dma-cells properties to fix dtbs_check warnings. Signed-off-by: Shravya Kumbham <shravya.kumbham@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/fedbf83fd5c682b4d61905d2cb790d33c2f079d6.1642160644.git.michal.simek@xilinx.com
2022-01-19arm64: zynqmp: Update USB node handle from dwc3 to usbManish Narani1-2/+2
The DWC3 bindings require all USB node handles to be '^usb@[0-9a-f]+$'. Update the same in ZynqMP device tree. Signed-off-by: Manish Narani <manish.narani@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/26fc2777eeb92cb5cb1d558d7c19cfb54ac42d0c.1642160613.git.michal.simek@xilinx.com
2022-01-19arm64: zynqmp: Change compatible strings for cadence uartMichal Simek1-2/+2
Based on Linux kernel DT binding there should be different compatible strings used that's why align zynqmp.dtsi with it. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/e2404ccd22fd97fe6020be0b3b6eb3c8677f55b0.1642160583.git.michal.simek@xilinx.com
2022-01-18ARM: dts: ast2600: Add MDIO devicesDylan Hung2-5/+109
There are 4 MDIO bus controllers in AST2600 SOC. Each of them can connect to one or more PHY chips and is flexible to work with the 4 MAC devices in AST2600. On AST2600 EVB, MDIO 0,1,2,3 connect to the PHY chips used by MAC 0,1,2,3 respectively. Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-01-18ARM: dts: s700: add MMC/SD controller nodeAmit Singh Tomar1-0/+10
This patch adds node for mmc/sd controller found on Action Semi OWL S700 SoC. Since, upstream Linux binding has not been merged for S700 MMC/SD controller, Changes are put in u-boot specific dtsi file. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
2022-01-18ARM: dts: sync Actions Semi S700 DT from Linux v5.16-rc3Amit Singh Tomar1-1/+16
This Synchronizes the Actions Semi S700 SoC DT changes from commit "g58e1100fdc59" ("Linux v5.16-rc3"). Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
2022-01-18common: board_r: move init_addr_map() to init.hOvidiu Panait1-8/+0
asm/mmu.h include is currently guarded by CONFIG_ADDR_MAP ifdef because the header is only present on arm and powerpc. In order to remove the dependency on this header and the associated ifdef, move init_addr_map() declaration to init.h, since it is only called during the common init sequence. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
2022-01-18common: board_r: drop initr_addr_map wrapperOvidiu Panait2-2/+4
Add a return value to init_addr_map and use it directly in the post-relocation init sequence, rather than using a wrapper stub. Reviewed-by: Matthias Brugger <mbrugger@suse.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
2022-01-18common: spl: move armv7m-specific code to spl_perform_fixups()Ovidiu Panait1-0/+6
Factor out armv7m fragment to spl_perform_fixups(), which is an arch/board specific function designed for this purpose. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
2022-01-17Merge branch '2022-01-15-TI-platform-updates'WIP/17Jan2022Tom Rini7-3/+157
- Let am335x_evm use the CPSW or PRUSS ethernet. - Implement timer_get_boot_us in the omap timer driver - gpmc bitflip, QSPI clock calculation on am437x, da8xx_gpio bugfixes - Assorted K3 updates
2022-01-17Merge tag 'u-boot-at91-2022.04-b' of ↵Tom Rini2-9/+80
https://source.denx.de/u-boot/custodians/u-boot-at91 Second set of u-boot-at91 features for the 2022.04 cycle: This small feature set includes few changes for sama7g5 and sama7g5ek: turn blue led on at boot, changes required for the Rev4 of the board, better sync with the Linux DT with regards to the new DT nodes.
2022-01-17ARM: dts: at91: sama7g5ek: move eeproms to flexcom8Eugen Hristev1-9/+30
The rev4 of the board sama7g5ek has the eeproms on flexcom8 instead of flexcom1. Initialize flexcom8 with required pincontrol and move the eeproms accordingly. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2022-01-17ARM: dts: at91: sama7g5: add flx8 and required nodesEugen Hristev1-0/+50
Add Flexcom8 node with required referenced nodes as phandles. Since Flexcom8 is present in Linux, take the node exactly as-is from Linux. Some nodes are referenced in Linux as phandles, the dma and the gic. Add them as well to the file, even if they are unused by Uboot. This is a step towards having the U-boot DT equivalent with the DT in Linux. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2022-01-17power: domain: Add Apple pmgr driverMark Kettenis1-0/+3
This driver supports power domains for the power management controller found on Apple SoCs. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-01-17arm: dts: apple: Add u-boot,dm-pre-reloc propertiesMark Kettenis6-0/+30
These are necessary to make sure the power domains needed for the serial console are availble in the pre-relocation phase. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-01-17arm: dts: apple: Update Apple M1 device treesMark Kettenis9-421/+2184
This synchronizes the device trees with those that are in the process of being upstreamed into Linux. This is mostly the current state of the device trees on the asahilinux branch with a few extra bits used by OpenBSD. This includes device trees for machines that were still missing. There are still some differences that will hopefully be resolved soon. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-01-15ARM: dts: K3-am642-r5-sk: Enable Second CPSW port in R5/A53 SPLVignesh Raghavendra2-1/+112
Enable Second Ethernet port on which ROM support Ethboot. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2022-01-15mach-k3: am64_spl: Alias Ethernet RGMII boot to CPGMACVignesh Raghavendra1-0/+1
This is required to enables spl_net boot on AM64x Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2022-01-15mach-k3: am642_init: Probe AM65 CPSW NUSS for R5/A53 SPLVignesh Raghavendra1-0/+7
In order to support Ethernet boot on AM64x, probe AM65 CPSW NUSS. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2022-01-15mach-k3: common: Instantiate AM65 CPSW NUSS wrapperVignesh Raghavendra1-0/+16
Probe toplevel AM65 CPSW NUSS driver from misc_init_r() when driver is enabled. Since driver is modeled as UCLASS_MISC, we need to explicitly probe the driver. Use common misc_init_r() that entire K3 family of SoCs. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2022-01-15ARM: mach-k3: sysfw-loader: Copy sysfw.itb to OCRAM in OSPI/SPI bootmodeVignesh Raghavendra1-2/+16
In case of xSPI bootmode OSPI flash is in DDR mode and needs to be accessed in multiple of 16bit accesses Hence we cannot parse sysfw.itb FIT image directly on OSPI flash via MMIO window. So, copy the image to internal on-chip RAM before parsing the image. Moreover, board cfg data maybe modified by ROM/TIFS in case of HS platform and thus cannot reside in OSPI/xSPI and needs to be copied over to internal OCRAM. This unblocks OSPI/xSPI boot on HS platforms Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Dave Gerlach <d-gerlach@ti.com> Tested-by: Keerthy <j-keerthy@ti.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
2022-01-15arm: mach-k3: am642_init: Unlock MCU PADCFG regsMichael Liebert2-0/+5
Currently only the PADCFG registers of the main domain are unlocked. Also unlock PADCFG registers of MCU domain, so MCU pin muxing can be configured by u-boot or Linux. Signed-off-by: Michael Liebert <liebert@ibv-augsburg.de> Tested-by: Christian Gmeiner <christian.gmeiner@gmail.com> Acked-by: Nishanth Menon <nm@ti.com>
2022-01-15Merge tag 'efi-2022-04-rc1' of ↵WIP/15Jan2022Tom Rini4-8/+10
https://source.denx.de/u-boot/custodians/u-boot-efi Pull request for efi-2022-04-rc1 Documentation: * Fix building HTML documentation of readthedocs.io * Add ARM Juno board documentation * Build requirements for Alpine Linux * Include DM headers in API documentation UEFI: * Fix section alignment of EFI binaries * Fix header length of RISC-V EFI binaries allowing to run them on EDK II * Remove kaslr-seed from device tree if the EFI_RNG_PROTOCOL is provided Other: * Let 'part list' show all 128 GPT partitions
2022-01-15efi_loader: fix SectionAlignment, FileAlignmentHeinrich Schuchardt4-8/+10
The alignment of sections in the EFI binaries generated by U-Boot is incorrect. According to the PE-COFF specification [1] the minimum value for FileAlignment is 512. If the value of SectionAlignment is less then the page size, it must equal FileAlignment. Let's set both values to 512 for the ARM and RISC-V architectures. [1] https://docs.microsoft.com/en-us/windows/win32/debug/pe-format Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-01-14armv8: apple: Disable PSCI resetMark Kettenis1-1/+1
Apple's ARMv8 cores don't implement EL3 and therefore don't provide a PSCI implementation. So don't attempt to use PSCI to reset on machines using Apple SoCs. Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
2022-01-14arm: mvebu: Enable BootROM output on A38xPali Rohár2-0/+10
BootROMs on pre-A38x SoCs enabled its output on UART by default, but A38x' BootROM has its output on UART disabled by default. To enable BootROM output on A38x SoC, it is required to set DEBUG flag (which only enables BootROM output and nothing more) in kwbimage. For UART images this DEBUG flag is ignored by BootROM. Enable kwbimage DEBUG flag for all A38x boards. With this change BootROM prints the following (success) information on UART before booting U-Boot kwbimage: BootROM - 1.73 Booting from SPI flash Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-14arm: mvebu: Correctly set LOAD_ADDRESS for U-Boot SPL binary in kwbimagePali Rohár2-3/+6
U-Boot SPL for mvebu platform is not compiled as position independent. Therefore it is required to instruct BootROM to load U-Boot SPL at the correct address. Loading of kwbimage binary code at specific address can be now achieved by the new LOAD_ADDRESS token as part of BINARY command in kwbimage config file. Update mvebu Makefile to put value of $(CONFIG_SPL_TEXT_BASE) into LOAD_ADDRESS token when generating kwbimage.cfg from kwbimage.cfg.in. It is required to update regex for sed to find replacement tokens at any position on a line in kwbimage config file and not only at the beginning of the line. This is because LOAD_ADDRESS is specified at the end of line containing the BINARY command. It looks like all Armada boards set CONFIG_SPL_TEXT_BASE to value 0x40004030 or 0x40000030. Why this value? It is because main kwbimage header is at address 0x40004030 or 0x40000000 and it is 32 bytes long. After the main header there is the binary header, which consist of 1 byte for type, 3 bytes for size, 1 byte for number of arguments, 3 reserved bytes and then 4 bytes for each argument. After these arguments comes the executable code. So arguments start at address 0x40004028 or 0x40000028. Before commit e6571f38c943 ("arm: mvebu: Remove dummy BIN header arguments for SPL binary") there were two (dummy) arguments, which resulted in load address of 0x40004030 or 0x40000030, always. After that commit (which removed dummy arguments), load address stayed same due to the 128-bit alignment done by mkimage. This patch now reflects the dependency between $(CONFIG_SPL_TEXT_BASE), load address and dummy kwbimage arguments, and allows the user to adjust $(CONFIG_SPL_TEXT_BASE) config option to some other value. For unsupported values, when mkimage/kwbimage cannot set chosen load address as specified by $(CONFIG_SPL_TEXT_BASE), the build process now fails, instead of silently generating non-working kwbimage. Removal of this alignment between $(CONFIG_SPL_TEXT_BASE) and LOAD_ADDRESS can only be done by compiling U-Boot SPL as position independent. But this currently is not possible for 32-bit ARM version of U-Boot SPL. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-14arm: mvebu: Set CPU for U-Boot SPL binary in kwbimagePali Rohár2-0/+11
kwbimage needs to know CPU type, so set it in kwbimage config file. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-14arm: mvebu: Generate kwbimage.cfg with $(call cmd, ...)Pali Rohár1-2/+5
Usage of $(call cmd,...) is standard way to call other commands which generate things. It also has the advantage of printing build information in the form KWBCFG arch/arm/mach-mvebu/kwbimage.cfg if verbosity is disabled, and printing the build command otherwise. Note that the '#' character needs to be escaped in Makefile when used as value for make variable assignment. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-14mtd: nand: pxa3xx: use marvell, prefix for custom DT propertiesPierre Bourdon1-1/+1
The DT properties for the "enable-arbiter" and "keep-config" config knobs were previously named inconsistently: - The u-boot driver used "nand-enable-arbiter" and "nand-keep-config" names, without Marvell prefixes. - The Linux driver uses "marvell,nand-keep-config" ("enable-arbiter" does not exist anymore in recent kernels, but it also used to be "marvell,nand-enable-arbiter"). - The device trees almost all use "marvell," prefixed names, except for one single instance of "nand-enable-arbiter" without vendor prefix. This commit standardizes on the vendor prefixed version, making the u-boot driver read from DT props "marvell,nand-enable-arbiter" and "marvell,nand-keep-config". The one device tree using the unprefixed version is also changed to use the new naming. This has the side effect of making the previously no-op "marvell," config knobs already present in some DTs actually do something. This was likely the original intention of the DT authors, but note that this commit was not tested on every single impacted board. Signed-off-by: Pierre Bourdon <delroth@gmail.com>
2022-01-14arm: mvebu: a38x: serdes: Move non-serdes PCIe code to pci_mvebu.cPali Rohár13-104/+36
As explained in commit 3bedbcc3aa18 ("arm: mvebu: a38x: serdes: Don't overwrite read-only SAR PCIe registers") it is required to set Maximum Link Width bits of PCIe Root Port Link Capabilities Register depending of number of used serdes lanes. As this register is part of PCIe address space and not serdes address space, move it into pci_mvebu.c driver. Read number of PCIe lanes from DT property "num-lanes" which is used also by other PCIe controller drivers in Linux kernel. If this property is absent then it defaults to 1. This property needs to be set to 4 for every mvebu board which use PEX_ROOT_COMPLEX_X4 or PEX_BUS_MODE_X4. Enabling of PCIe port needs to be done afer all registers in PCIe address space are properly configure. For this purpose use new mvebu-reset driver (part of system-controller) and remove this code from serdes code. Because some PCIe ports cannot be enabled individually, it is required to first setup all PCIe ports and then enable them. This change contains also all required "num-lanes" and "resets" DTS properties, to make pci_mvebu.c driver work correctly. Signed-off-by: Pali Rohár <pali@kernel.org>
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