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2023-07-21Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxiWIP/21Jul2023Tom Rini8-176/+370
For once this adds USB support for two SoCs: the H616 and the F1C100s series. The rest is support for LPDDR3 DRAM chips on H616 boards. Gitlab CI passed, and I booted that briefly on an H616 and an F1C200s board. I don't have an H616 board with LPDDR3 DRAM, but reportedly that works for Mikhail, and doesn't regress on my DDR3 boards.
2023-07-21Merge tag 'xilinx-for-v2023.10-rc1-v2' of ↵Tom Rini79-164/+456
https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2023.10-rc1 v2 axi_emac: - Change return value if RX packet is not ready cadence_qspi: - Enable flash reset for Versal NET dt: - Various DT syncups with Linux kernel - SOM - reserved pmufw memory location fpga: - Add load event mtd: - Add missing dependency for FLASH_CFI_MTD spi/nand: - Minor cleanup in Xilinx drivers versal-net: - Prioritize boot device in boot_targets - Wire mini ospi/qspi/emmc configurations watchdog: - Use new versal-wwdt property xilinx: - fix sparse warnings in various places ps7_init* - add missing headers - consolidate code around zynqmp_mmio_read/write - switch to amd.com email zynqmp_clk: - Add handling for gem rx/tsu clocks zynq_gem: - Configure mdio clock at run time zynq: - Enable fdt overlay support zynq_sdhci: - Call dll reset only for ZynqMP SOCs
2023-07-21arm64: zynqmp: Remove clock-names from pcap nodeMichal Simek2-5/+0
Clock is not used in driver and also not described in binding. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/0a0fa0ba197fa4051a2c8a24e1451cefadce7517.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Rename ams_ps/pl node namesMichal Simek1-2/+2
Fix child node names to be aligned with dt-binding available in the Linux kernel which requires names as ams-ps@ and ams-pl@. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/8f1451d614f654cb0d0da1e799e876c078fbf2c9.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Remove interrupt/reg-names for AMSMichal Simek1-2/+0
These two properties are not described in DT binding and also not used by driver that's why remove them. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/b123c7e537dcf70802e828bbcd484a761a264186.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: remove snps, enable_guctl1_resume_quirk quirk for usbPiyush Mehta1-2/+0
To sync with the upstream code, removed 'snps,enable_guctl1_resume_quirk' quirk for usb. This quirk is no more available in linux after the xilinx release 2022.2. This functionality is taken care of by the 'snps,resume-hs-terminations' quirk. Signed-off-by: Piyush Mehta <piyush.mehta@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/4b7a132116bf0248cdb558e04de3b06b412c4a0f.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: add pmu interrupt-affinityRadhey Shyam Pandey1-0/+4
Explicitly specify interrupt affinity to avoid HW perfevents need to guess. This avoids the following error upon linux boot: armv8-pmu pmu: hw perfevents: no interrupt-affinity property, guessing. Reported-by: John Toomey <john.toomey@amd.com> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/c2f55a10cf54c6004f5dfe2ea18bcb4cf04f5723.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Sync node name address with reg (mailbox)Michal Simek1-1/+1
Address in node name should match with the first reg property in DT. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/47bea10bbc3c88727c1fe839ff20e15a0c79c339.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Add L2 cache nodesRadhey Shyam Pandey1-0/+10
Linux kernel throws "cacheinfo: Unable to detect cache hierarchy for CPU 0" warning when booting on zu+ Soc. To fix it add the L2 cache node and let each CPU point to it. Reported-by: John Toomey <john.toomey@amd.com> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/c8dfabab12c97922aaad7fa91be0cbc7e4021528.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Fix usb reset over bootmode pins on zcu100Michal Simek1-0/+2
The commit a4180c369607 ("arm64: zynqmp: Add mode-pin GPIO controller DT node") added usb phy reset over bootmode pins by default on usb0 only. zcu100 is using usb0 as peripheral and usb1 as host. Unfortunately reset line is shared for both usb ulpi phys but usb_rst_b is connected to usb5744 hub which is used only in host mode. Especially this chip requires reset to operate properly that's why better assign gpio reset to usb1 instead of usb0. Without this change usb start crashed when runs. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/1ca80ec5bf7a595c03822f3e4e3683298205067a.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Cover K24 revB/1 SOMMichal Simek1-2/+3
Extend compatible versions for K24 SOM. Changes are not affecting SW behavior that's why all versions are compatible to each other. Describing all revisions is done by purpose because user space SW is reading compatible string for logic around DT overlays and bitstreams. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/92eba01ac316e58bd2d3508b0e63bbfafbedbb73.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Record compatible string for kv260 rev2Michal Simek1-1/+2
PCB rev2 compare to rev1 has some changes in PL side (IAS sensor AR1335 autofocus feature). PS side is completely unchanged. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/42f78dee8429eeac016d73de5c73af46fdaf4a98.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Assign TSU clock frequency for KV and KD boardsHarini Katakam2-0/+2
Set TSU clock frequency as 250MHz (minimum when running at 1G) on KV and KD carrier cards to allow PTP functionality. Signed-off-by: Harini Katakam <harini.katakam@amd.com> Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/4b758d503ef545e4d25d3930b0eb0793f1c415d2.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Increase reset assert time for TI SGMII PHYHarini Katakam2-2/+2
Increase reset assert time for TI SGMII PHY on KR260 CC starting 6.1 kernel. This PHY does not come out of reset with the existing 100us pulse width as per testing on multiple carrier cards. The reset is driven via a PCA9570 I2C expander. The expander driver was updated to an upstream version in 6.1 where gpio_chip _set was optimized. Delays in earlier kernels may have masked this issue. This is a safe workaround value for assert pulse width before the discussions are resolved with TI. Signed-off-by: Harini Katakam <harini.katakam@amd.com> Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/8fb9f17d43a43ef504c9f29006cd686cce8ac98b.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Fix gpio comment about No of gpiosMichal Simek10-10/+10
There are total 174 gpios but from 0 - 173 that's why fix comment to reflect it. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/c7e94b334e7dd6297e0d3a36a6a3d04bd7e9e967.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Assign TSU clock frequency for KR260Harini Katakam3-0/+8
Set TSU clock frequency as 250MHz (minimum when running at 1G) on KR260 CC to allow PTP functionality. Signed-off-by: Harini Katakam <harini.katakam@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/d065b5c2c6450910bf57d104d65946111493caaa.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Update MALI 400 interrupt and clock namesParth Gajjar2-4/+4
Motivation for the commit is to utilize the upstream community device tree so that the either modified ARM Mali 400 driver or upstream lima driver can be used. Signed-off-by: Parth Gajjar <parth.gajjar@amd.com> Signed-off-by: Vishal Sagar <vishal.sagar@amd.com> Link: https://lore.kernel.org/r/1678181001-2327-2-git-send-email-parth.gajjar@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/89d046a9da5638e8b4918f80f3245d73ea46f99f.1688992653.git.michal.simek@amd.com
2023-07-21xilinx: dts: Fix open drain warning on Zynq, ZynqMP and VersalManikanta Guntupalli18-48/+49
Fix for below open drain warning on Zynq, ZynqMP and Versal reported by Linux. "enforced open drain please flag it properly in DT/ACPI DSDT/board file." Signed-off-by: Manikanta Guntupalli <manikanta.guntupalli@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/056b6f60f89fa2addb762669b80640cd5b31b001.1688992653.git.michal.simek@amd.com
2023-07-21arm: xilinx: Setting default i2c clock frequency to 400kHzVaralaxmi Bingi2-0/+4
Setting default i2c clock frequency for Zynq and ZynqMP to maximum rate of 400kHz. Current default value is 100kHz. Signed-off-by: Varalaxmi Bingi <varalaxmi.bingi@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/fb46fe911a68b79c8e4d150ca90c4e94eb5fb9e1.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Switch to amd.com emailsMichal Simek67-78/+78
Update my and DPs email address to match current setup. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/aba5b19b9c5a95608829e86ad5cc4671c940f1bb.1688992543.git.michal.simek@amd.com
2023-07-21xilinx: Consolidate zynqmp_mmio_read/write in zynqmp_firmware.hMichal Simek4-7/+1
zynqmp_mmio_read/write() are firmware provided hooks that's why use only zynqmp_firmware.h for function declaration. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/e7489556f9e447c737a578c169d7e1e43586a273.1687524706.git.michal.simek@amd.com
2023-07-21xilinx: versal-net: Add mini eMMC 5.1 configurationAshok Reddy Soma2-0/+65
Add support for Versal NET mini eMMC 5.1 configuration. Add device tree and defconfig. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20230614121351.21521-4-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-07-21xilinx: versal-net: Add mini ospi configurationAshok Reddy Soma3-0/+98
Add support for Versal NET mini Octal SPI flash configuration. This runs from onchip memory, so it has to be compact. Hence only Octal SPI related settings are enabled. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20230614121351.21521-3-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-07-21xilinx: versal-net: Add mini qspi configurationAshok Reddy Soma3-0/+89
Add support for Versal NET mini Quad SPI flash configuration. This runs from onchip memory, so it has to be compact. Hence only Quad SPI related settings are enabled. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20230614121351.21521-2-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-07-21cadence_qspi: Enable flash reset for Versal NET platformAshok Reddy Soma1-0/+11
Enable flash reset functionality for Versal NET platform. In cadence_qspi.c there is weak function defined for reset, hence remove the check for config, so that it will work for Versal and Versal NET platforms. Add register defines in Versal NET hardware.h for mini U-Boot flash reset. Add read_delay initialization for Versal NET also. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20230614120452.21019-1-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-07-21arm64: zynqmp: Fix the memory node for k26/k24 kria som boardsSharath Kumar Dasari1-0/+11
PMUFW requires top 1MB of the lower DDR memory reserved for its operation, this is missing in k26/k24 sm static dts files because of which U-Boot throws warning messages "efi_free_pool: illegal free" as EFI puts some code to that space which shouldn't happen. Signed-off-by: Sharath Kumar Dasari <sharath.kumar.dasari@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/57452d16df2d48593de206bebf877d2c2cfe7bf1.1685966389.git.michal.simek@amd.com
2023-07-20Merge tag 'dm-pull-20jul23' of ↵WIP/20Jul2023Tom Rini1-0/+1
https://source.denx.de/u-boot/custodians/u-boot-dm binman mkimage and template enhancements misc fixes
2023-07-21sunxi: H616: add LPDDR3 DRAM supportMikhail Kalashnikov4-55/+242
The H616 SoC has support for several types of DRAM: DDR3, LPDDR3, DDR4 and LPDDR4. At the moment, the driver only supports DDR3 memory. Let's extend the driver to support the LPDDR3 memory. All "magic" values obtained from the boot0. Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com> Acked-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-07-21sunxi: H616: add DRAM type selectionMikhail Kalashnikov2-3/+10
Allwinner H616 SoC supports several types of DRAM memory. To further integrate other types of memory, we need to add this delimitation. Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-07-21sunxi: H616: dram: split struct dram_paraAndre Przywara2-91/+101
Currently there is one DRAM parameter struct for the Allwinner H616 DRAM "driver". It contains many fields that are compile time constants (set by Kconfig variables), though there are also some fields that are probed and changed over the runtime of the DRAM initialisation. Because of this mixture, the compiler cannot properly optimise the code for size, as it does not consider constant propagation in its full potential. Help the compiler out by splitting that structure into two: one that only contains values known at compile time, and another one where the values will actually change. The former can then be declared "const", which will let the compiler fold its values directly into the code using it. We also add "const" tags for some new "struct dram_config" pointers, to further increase code optimisation. To help the compiler optimise the code further, the definition of the now "const struct dram_para" has to happen at a file-global level, so move that part out of sunxi_dram_init(). That results in quite some code savings (almost 2KB), and helps to keep the code small with the LPDDR3 support added later. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-07-21sunxi: H616: dram: const-ify DRAM function parametersAndre Przywara3-17/+17
There are quite some functions in the Allwinner H616 DRAM "driver", some of them actually change the parameters in the structure passed to them, but many are actually not. To increase the optimisation potential for the code, mark those functions that just read members of the passed dram_para struct as "const". This in itself does not decrease the code size, but lays the groundwork for future changes doing so. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-07-21sunxi: dram: make MBUS configuration functions staticAndre Przywara3-11/+12
The usage of the C keyword "inline" seems to be a common misunderstanding: it's a *hint* only, and modern compilers will inline (or not) functions based on their own judgement and provided compiler options. So while marking functions as "inline" does not do much, missing the "static" keyword will force to compiler to spell out a version of the function for potential external callers, which actually increases the code size (though hopefully the linker will drop the function). Change the "inline" attribute for the mbus_configure_port() functions in some Allwinner DRAM drivers to "static", so that the explicit version can actually be dropped from the object file, reducing the code size. "static inline" has a use case in header files, where it avoids a warning if a .c file including this header does not use the particular function. In a .c file itself "static inline" is not useful otherwise, so just use static here as well. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-07-21sunxi: Kconfig: rework PHY_USB_SUN4I selectionAndre Przywara1-11/+0
At the moment we use "select" in each Allwinner SoC's Kconfig section to include the USB PHY driver in the build. This means it cannot be disabled via Kconfig, although USB is not really a strictly required core functionality, and a particular board might not even include USB ports. Rework the Kconfig part by removing the "select" lines for each SoC's section, and instead letting it default to "y" in the PHY driver section itself. We use "depends on !" to exclude the few SoCs we don't support (yet). The Allwinner V3s does not enable USB (PHY) support at the moment, even though it should work: let the PHY default to "n" to keep the current behaviour. Also the MUSB USB driver directly calls some functions from the PHY driver, so let the former depend on the PHY driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Tested-by: Sam Edwards <CFSworks@gmail.com>
2023-07-20stm32mp15: Avoid writing symbols in SPLSimon Glass1-0/+1
These boards use SPL in a mkimage entry and apparently access the symbol containing the image position of U-Boot, but put U-Boot in another image. This means that binman is unable to fill in the symbol correctly in the SPL binary. This doesn't matter at present since mkimage doesn't support symbol writing. But with the upcoming conversion to a section, it will. So add a property to disable symbol writing. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-07-20arm: mx5: Correct mxc_set_clock function prototypeTom Rini1-1/+1
With gcc-13.1 we get a warning about enum vs int here, so correct the declaration to match the implementation. Signed-off-by: Tom Rini <trini@konsulko.com>
2023-07-14arch: arm: npcm8xx: add cpu version and 4G ram supportJim Liu2-1/+12
Add npcm8xx A2 cpu version check and add 4G RAM support Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2023-07-14ARM: dts: npcm8xx: fix dts node errorJim Liu1-16/+17
The SHA and OTP should under the ahb node Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2023-07-13Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellTom Rini7-113/+348
- mvebu: Thecus: Misc enhancement and cleanup (Tony) - mvebu: Add AC5X Allied Telesis x240 board support incl NAND controller enhancements for this SoC (Chris)
2023-07-13arm: mvebu: Remove unused alias from RC AC5X dtsChris Packham1-1/+0
The sar-reg0 alias was left over from an earlier iteration of the patches adding support for this board. Remove the unused alias. Fixes: 6cc8b5db40 ("arm: mvebu: Add RD-AC5X board") Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2023-07-13arm: mvebu: Add Allied Telesis x240 boardChris Packham3-1/+221
The x240 and SE240 are a series of L2+ switches from Allied Telesis. There are a number of them in the range but as far as U-Boot is concerned all the CPU block components are the same so there's only one board defined. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2023-07-13mx23_olinuxino: Convert to CONFIG_DM_SERIALFabio Estevam2-1/+1
The conversion to CONFIG_DM_SERIAL is mandatory, so select this option. Signed-off-by: Fabio Estevam <festevam@denx.de>
2023-07-13mx23evk: Convert to CONFIG_DM_SERIALFabio Estevam2-1/+2
The conversion to CONFIG_DM_SERIAL is mandatory, so select this option. Signed-off-by: Fabio Estevam <festevam@denx.de>
2023-07-13mx28evk: Convert to CONFIG_DM_SERIALFabio Estevam2-1/+1
The conversion to CONFIG_DM_SERIAL is mandatory, so select this option. Signed-off-by: Fabio Estevam <festevam@denx.de>
2023-07-13arm64: dts: verdin-imx8mp: add ctrl_sleep_moci# hogAndrejs Cainikovs1-0/+8
Drive CTRL_SLEEP_MOCI# high at boot (SPL) using a GPIO hog, this signal may be used to control some power-rails on the carrier board, therefore it should be set to high when the module is booting. To do this as early as possible is generally a good idea and the issue was noticed on the Yavia carrier board where it is needed to power the I2C EEPROM on the carrier board. Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2023-07-13arm64: dts: verdin-imx8mm: add ctrl_sleep_moci# hogAndrejs Cainikovs1-0/+8
Drive CTRL_SLEEP_MOCI# high at boot (SPL) using a GPIO hog, this signal may be used to control some power-rails on the carrier board, therefore it should be set to high when the module is booting. To do this as early as possible is generally a good idea and the issue was noticed on the Yavia carrier board where it is needed to power the I2C EEPROM on the carrier board. Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2023-07-13verdin-imx8mm/verdin-imx8mp: synchronise device trees with linuxMarcel Ziswiler8-335/+309
Synchronise device trees with linux v6.5-rc1. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2023-07-13arm: dts: imx8mp-beacon-kit: Enable USB Power domainsAdam Ford1-2/+0
The USB Power domains should not have been removed as it causes the board to hang if the USB is started. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
2023-07-13arm: dts: imx8mp: Sync the DT with kernel 6.4-rc4Adam Ford2-119/+386
Several changes have been made to the device tree in the kernel, so update that as well as the corresponding imx8mp-u-boot.dtsi files to prevent breaking the booting. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
2023-07-13imx8mn-var-som: adjust PHY reset gpios according to hardware configurationHugo Villeneuve1-4/+0
For SOM with the EC configuration, the ethernet PHY is located on the SOM itself, and connected to the CPU ethernet controller. It has a reset line controlled via GPIO1_IO9. In this configuration, the PHY located on the carrier board is not connected to anything and is therefore not used. For SOM without EC configuration, the ethernet PHY on the carrier board is connected to the CPU ethernet controller. It has a reset line controlled via the GPIO expander PCA9534_IO5. The hardware configuration (EC) is determined at runtime by reading from the SOM EEPROM. To support both hardware configurations (EC and non-EC), adjust/fix the PHY reset gpios according to the hardware configuration read at runtime from the SOM EEPROM. This adjustement is done in U-Boot (OF_BOARD_FIXUP) and kernel (OF_BOARD_SETUP) device trees. Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
2023-07-13ARM: imx: romapi: Fix signed integer bitwise ops misuseMarek Vasut1-11/+21
Bitwise operations on signed integers are not defined, replace them with per-call checks. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Heiko Schocher <hs@denx.de>
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