aboutsummaryrefslogtreecommitdiff
path: root/arch/arm
AgeCommit message (Collapse)AuthorFilesLines
2023-07-20Merge tag 'dm-pull-20jul23' of ↵WIP/20Jul2023Tom Rini1-0/+1
https://source.denx.de/u-boot/custodians/u-boot-dm binman mkimage and template enhancements misc fixes
2023-07-20stm32mp15: Avoid writing symbols in SPLSimon Glass1-0/+1
These boards use SPL in a mkimage entry and apparently access the symbol containing the image position of U-Boot, but put U-Boot in another image. This means that binman is unable to fill in the symbol correctly in the SPL binary. This doesn't matter at present since mkimage doesn't support symbol writing. But with the upcoming conversion to a section, it will. So add a property to disable symbol writing. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-07-20arm: mx5: Correct mxc_set_clock function prototypeTom Rini1-1/+1
With gcc-13.1 we get a warning about enum vs int here, so correct the declaration to match the implementation. Signed-off-by: Tom Rini <trini@konsulko.com>
2023-07-14arch: arm: npcm8xx: add cpu version and 4G ram supportJim Liu2-1/+12
Add npcm8xx A2 cpu version check and add 4G RAM support Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2023-07-14ARM: dts: npcm8xx: fix dts node errorJim Liu1-16/+17
The SHA and OTP should under the ahb node Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2023-07-13Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellTom Rini7-113/+348
- mvebu: Thecus: Misc enhancement and cleanup (Tony) - mvebu: Add AC5X Allied Telesis x240 board support incl NAND controller enhancements for this SoC (Chris)
2023-07-13arm: mvebu: Remove unused alias from RC AC5X dtsChris Packham1-1/+0
The sar-reg0 alias was left over from an earlier iteration of the patches adding support for this board. Remove the unused alias. Fixes: 6cc8b5db40 ("arm: mvebu: Add RD-AC5X board") Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2023-07-13arm: mvebu: Add Allied Telesis x240 boardChris Packham3-1/+221
The x240 and SE240 are a series of L2+ switches from Allied Telesis. There are a number of them in the range but as far as U-Boot is concerned all the CPU block components are the same so there's only one board defined. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2023-07-13mx23_olinuxino: Convert to CONFIG_DM_SERIALFabio Estevam2-1/+1
The conversion to CONFIG_DM_SERIAL is mandatory, so select this option. Signed-off-by: Fabio Estevam <festevam@denx.de>
2023-07-13mx23evk: Convert to CONFIG_DM_SERIALFabio Estevam2-1/+2
The conversion to CONFIG_DM_SERIAL is mandatory, so select this option. Signed-off-by: Fabio Estevam <festevam@denx.de>
2023-07-13mx28evk: Convert to CONFIG_DM_SERIALFabio Estevam2-1/+1
The conversion to CONFIG_DM_SERIAL is mandatory, so select this option. Signed-off-by: Fabio Estevam <festevam@denx.de>
2023-07-13arm64: dts: verdin-imx8mp: add ctrl_sleep_moci# hogAndrejs Cainikovs1-0/+8
Drive CTRL_SLEEP_MOCI# high at boot (SPL) using a GPIO hog, this signal may be used to control some power-rails on the carrier board, therefore it should be set to high when the module is booting. To do this as early as possible is generally a good idea and the issue was noticed on the Yavia carrier board where it is needed to power the I2C EEPROM on the carrier board. Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2023-07-13arm64: dts: verdin-imx8mm: add ctrl_sleep_moci# hogAndrejs Cainikovs1-0/+8
Drive CTRL_SLEEP_MOCI# high at boot (SPL) using a GPIO hog, this signal may be used to control some power-rails on the carrier board, therefore it should be set to high when the module is booting. To do this as early as possible is generally a good idea and the issue was noticed on the Yavia carrier board where it is needed to power the I2C EEPROM on the carrier board. Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2023-07-13verdin-imx8mm/verdin-imx8mp: synchronise device trees with linuxMarcel Ziswiler8-335/+309
Synchronise device trees with linux v6.5-rc1. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2023-07-13arm: dts: imx8mp-beacon-kit: Enable USB Power domainsAdam Ford1-2/+0
The USB Power domains should not have been removed as it causes the board to hang if the USB is started. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
2023-07-13arm: dts: imx8mp: Sync the DT with kernel 6.4-rc4Adam Ford2-119/+386
Several changes have been made to the device tree in the kernel, so update that as well as the corresponding imx8mp-u-boot.dtsi files to prevent breaking the booting. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
2023-07-13imx8mn-var-som: adjust PHY reset gpios according to hardware configurationHugo Villeneuve1-4/+0
For SOM with the EC configuration, the ethernet PHY is located on the SOM itself, and connected to the CPU ethernet controller. It has a reset line controlled via GPIO1_IO9. In this configuration, the PHY located on the carrier board is not connected to anything and is therefore not used. For SOM without EC configuration, the ethernet PHY on the carrier board is connected to the CPU ethernet controller. It has a reset line controlled via the GPIO expander PCA9534_IO5. The hardware configuration (EC) is determined at runtime by reading from the SOM EEPROM. To support both hardware configurations (EC and non-EC), adjust/fix the PHY reset gpios according to the hardware configuration read at runtime from the SOM EEPROM. This adjustement is done in U-Boot (OF_BOARD_FIXUP) and kernel (OF_BOARD_SETUP) device trees. Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
2023-07-13ARM: imx: romapi: Fix signed integer bitwise ops misuseMarek Vasut1-11/+21
Bitwise operations on signed integers are not defined, replace them with per-call checks. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Heiko Schocher <hs@denx.de>
2023-07-13configs: imx8m: Prepare imx8m-venice boards for HAB supportTim Harvey1-0/+9
In order to enable HAB, FSL_CAAM, ARCH_MISC_INIT and SPL_CRYPTO should be enabled in Kconfig like other i.MX8M boards. This also needs to occur in the SPL so enable CONFIG_SPL_BOARD_INIT and add a void spl_board_init function which calls arch_misc_init to probe the CAAM driver. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-07-13imx: priblob: Update to use structureMaximus Sun1-3/+7
Use structure to avoid define CAAM_SCFGR for each platform Signed-off-by: Maximus Sun <maximus.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13imx: imx8m: add CAAM_BASE_ADDRPeng Fan1-0/+1
Add CAAM_BASE_ADDR which will be used by priblob.c Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13imx: imx8: ahab: sha256: enable image verification using ARMv8 crypto extensionGaurav Jain1-4/+24
add support for SHA-256 secure hash algorithm using the ARM v8 SHA-256 instructions for verifying image hash. Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13imx: ahab: Update AHAB for iMX8 and iMX8ULPYe Li4-123/+103
Abstract common interfaces for AHAB authentication operations. Then share some common codes for AHAB and SPL container authentication Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13imx: parse-container: Use malloc for container processingNitin Garg1-11/+27
If the container has image which conflicts with spl_get_load_buffer address, there are processing failures. Use malloc instead of spl_get_load_buffer. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Nitin Garg <nitin.garg@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13imx: imx8m: clock: not configure reserved SRC registerPeng Fan1-1/+0
i.MX8M[M,N,P] SRC not has 0x1004 offset register, so drop it. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13imx: imx8: bootaux: Add i.MX8 M4 boot supportYe Li5-5/+192
1. Implement bootaux for the M4 boot on i.MX8QM and QXP. Users need to download M4 image to any DDR address first. Then use the "bootaux <M4 download DDR address> [M4 core id]" to boot CM4_0 or CM4_1, the default core id is 0 for CM4_0. Since current M4 only supports running in TCM. The bootaux will copy the M4 image from DDR to its TCML. 2. Implment bootaux for HIFI on QXP command: bootaux 0x81000000 1 Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13imx: bootaux: Fix bootaux issue when running on ARM64Ye Li1-3/+3
The bootaux uses ulong to read private data and write to M4 TCM, this cause problem on ARM64 platform where the ulong is 8bytes. Fix it by using u32 to replace ulong. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13imx: bootaux: change names of MACROs used to boot MCU on iMX devicesPeng Fan5-18/+18
The current bootaux supports i.MX8M and i.MX93, but the name "_M4_" implies that the SoCs have Cortex-M4. Actually i.MX8MM/Q use Cortex-M4, i.MX8MN/P use Cortex-M7, i.MX93 use Cortex-M33, so use "_MCU_" in place of "_M4_" to simplify the naming. Signed-off-by: faqiang.zhu <faqiang.zhu@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13imx: iamge-container: support secondary containerPeng Fan1-7/+87
Add the support for loading image from secondary container set on iMX8QM B0, iMX8QXP C0. Using the SCFW API to get container set index, if it is the secondary boot, get the offset from fuse and apply to offset of current container set beginning for loading. Also override the emmc boot partition to check secondary boot and switch to the other boot part. This patch is modified from NXP downstream: imx8: Fix the fuse used by secondary container offset imx: container: Skip container set check for ROM API imx8: spl: Support booting from secondary container set Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13imx: image-container: Fix container header checkingYe Li1-1/+1
Checking container header tag and version is wrong, it causes to fail to bypass invalid container Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13imx: hab: Fix coverity issue in HAB event decodingYe Li1-19/+22
Fix below coverity issues caused by get_idx function where "-1" is compared with uint8_t "element" 343336 Unsigned compared with neg 343337 Operands don't affect result Additional, this function returns "-1" will cause overflow to event string array. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13imx: imx8ulp: start the ELE RNG at bootPeng Fan1-0/+1
On the imx8ulp A1 SoC, the ELE RNG needs to be manually started. Signed-off-by: Clement Faure <clement.faure@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13imx: cmd_dek: add ELE DEK Blob generation supportClement Faure2-0/+91
Add ELE DEK Blob generation for the cmd_dek command. Signed-off-by: Clement Faure <clement.faure@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13imx: cmd_dek: Fix Uninitialized pointer readYe Li1-1/+2
Fix Coverity (CID 21143558). When tee_shm_register returns failure, the shm_input pointer is invalid, should not free it. Same issue also exists on registering shm_output. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13imx: ele_api: add DEK Blob generationPeng Fan1-1/+1
- Add crc computation. - Add ele_generate_dek_blob API for encrypted boot support. Signed-off-by: Clement Faure <clement.faure@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13imx: ele_api: support program secure fuse and return lifecyclePeng Fan2-0/+76
Add two ELE API: ele_return_lifecycle_update and ele_write_secure_fuse Add two cmd: ahab_return_lifecycle and ahab_sec_fuse_prog Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13imx: ele_ahab: use hextoulPeng Fan1-1/+1
Use hextoul which looks a bit simpler. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13imx: parse-container: fix build warningPeng Fan1-2/+2
Fix build warning: warning: format ‘%x’ expects argument of type ‘unsigned int’, but argument 3 has type ‘u64’ {aka ‘long long unsigned int’} [-Wformat=] printf("can't find memreg for image %d load address 0x%x, error %d\n", warning: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 3 has type ‘sc_faddr_t’ {aka ‘long long unsigned int’} [-Wformat=] debug("memreg %u 0x%lx -- 0x%lx\n", mr, start, end); Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13imx: use generic name ele(EdgeLockSecure Enclave)Peng Fan12-76/+77
Per NXP requirement, we rename all the NXP EdgeLock Secure Enclave code including comment, folder and API name to ELE to align. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13imx: mach: correct SCU API usagePeng Fan5-101/+94
The return value is int type, not sc_err_t(u8), correct the usage. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13arm: mvebu: ac5: Define mvebu_get_nand_clock()Chris Packham1-0/+6
The NF_CLK for the AC5 SoC runs at 400MHz. There's no strapping or gating require so just add a mvebu_get_nand_clock() that returns this value. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2023-07-13arm: mvebu: ac5: Add nand-controller nodeChris Packham1-0/+9
The AC5/AC5X SoC has a NAND flash controller. Add this to the SoC device tree. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2023-07-13arm: mvebu: Enable gpio-fan for Thecus N2350 boardTony Dinh1-0/+15
Add gpio-fan in the DTS and enable the GPIO in board file to start the fan during boot. Note that this patch depends on https://patchwork.ozlabs.org/project/uboot/patch/20230606214539.4229-1-mibodhi@gmail.com/ Signed-off-by: Tony Dinh <mibodhi@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2023-07-13arm: mvebu: Clean up Thecus N2350 board DTSTony Dinh1-112/+98
- Update the Thecus N2350 DTS to conform with latest device-tree binding and styles. - Correct typo in mdio node. Signed-off-by: Tony Dinh <mibodhi@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Pali Rohár <pali@kernel.org>
2023-07-11board: gateworks: venice: add imx8mp-gw7905-2x supportTim Harvey6-0/+988
The Gateworks imx8mp-venice-gw7905-2x consists of a SOM + baseboard. The GW702x SOM contains the following: - i.MX8M Plus SoC - LPDDR4 memory - eMMC Boot device - Gateworks System Controller (GSC) with integrated EEPROM, button controller, and ADC's - PMIC - SOM connector providing: - eQoS GbE MII - 1x SPI - 2x I2C - 4x UART - 2x USB 3.0 - 1x PCI - 1x SDIO (4-bit 3.3V) - 1x SDIO (4-bit 3.3V/1.8V) - GPIO The GW7905 Baseboard contains the following: - GPS - microSD - off-board I/O connector with I2C, SPI, GPIO - EERPOM - PCIe clock generator - 1x full-length miniPCIe socket with PCI/USB3 (via mux) and USB2.0 - 1x half-length miniPCIe socket with USB2.0 and USB3.0 - USB 3.0 HUB - USB Type-C with USB PD Sink capability and peripheral support - USB Type-C with USB 3.0 host support Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2023-07-11imx8mn-var-som: read eth MAC address from EEPROMHugo Villeneuve2-0/+14
Read ethernet MAC address from EEPROM located on the SOM. Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
2023-07-11arm: dts: imx8mn-var-som: fix PHY detection bug by adding deassert delayHugo Villeneuve1-1/+7
While testing the ethernet interface on a Variscite symphony carrier board using an imx8mn SOM with an onboard ADIN1300 PHY (EC hardware configuration), the ethernet PHY is not detected. The ADIN1300 datasheet indicate that the "Management interface active (t4)" state is reached at most 5ms after the reset signal is deasserted. The device tree in Variscite custom git repository uses the following property: phy-reset-post-delay = <20>; Add a new MDIO property 'reset-deassert-us' of 20ms to have the same delay inside the ethphy node. Adding this property fixes the problem with the PHY detection. Note that this SOM can also have an Atheros AR8033 PHY. In this case, a 1ms deassert delay is sufficient. Add a comment to that effect. Fixes: c4c1ed68c1e8 ("imx8mn_var_som: Add support for Variscite VAR-SOM-MX8M-NANO board") Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
2023-07-11imx8mn-var-som: fix non-applied PHY reset-gpios propertiesHugo Villeneuve1-0/+1
Select DM_ETH_PHY so that the reset-gpios property of the ethphy node can be used. Also select DM_PCA953X, which is needed for resetting the ethernet PHY on the carrier board via the PCA9534 I/O expander. Commit 4e5114daf9eb ("imx8mn: synchronise device tree with linux") did synchronise device tree with linux, which in effect removed obsolete PHY reset properties and replaced them with new mdio DM properties. But the commit didn't activate DM_ETH_PHY or DM_PCA953X. Fixes: 4e5114daf9eb ("imx8mn: synchronise device tree with linux") Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
2023-07-11imx8mn-var-som: read and print SoM infos from eeprom on startupHugo Villeneuve3-0/+16
Enable support to read and display configuration/manufacturing infos from 4Kbit EEPROM located on SOM board. Note: CONFIG_DISPLAY_BOARDINFO is automatically selected for ARM arch. Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
2023-07-11imx8m: soc.c: demote some printfs to debugRasmus Villemoes1-2/+2
Getting Found /vpu_g1@38300000 node Modify /vpu_g1@38300000:status disabled Found /vpu_g2@38310000 node Modify /vpu_g2@38310000:status disabled etc. on the console on every boot is needlessly verbose. Demote the "Found ..." lines to debug(), which is consistent with other instances in soc.c. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
generated by cgit v1.1 at 2024-08-17 12:54:30 +0000