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2023-06-12Merge tag 'xilinx-for-v2023.10-rc1' of ↵WIP/12Jun2023-nextTom Rini15-14/+42
https://source.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2023.10-rc1 global: - Use proper U-Boot project name Fix sparse warnings in zynqmp-clk, zynqmp handoff, board cmd: - Cover incorrect 0 length entries Versal NET: - Add bootmode logic - Support SPP production version - Add loadpdi command ZynqMP: - Clear pmufw node command ID handling - Change power domain behavior around zynqmp_pmufw_node() - Fix zynqmp cmd return values and pmufw command - Fix R5 tcm init and modes mmc: - Sync Versal NET emmc DT binding pcie: - Add support for ZynqMP PCIe root port video: - Add support for ZynqMP DP tools: - Fix debug message in relocate-rela
2023-06-12Merge tag v2023.07-rc4 into nextTom Rini111-1829/+5438
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-06-12arm64: versal: Add missing prototypesAlgapally Santosh Sagar1-4/+4
Add missing prototypes to fix the below sparse warnings 1. warning: no previous prototype for 'set_r5_halt_mode' [-Wmissing-prototypes] 2. warning: no previous prototype for 'set_r5_tcm_mode' [-Wmissing-prototypes] 3. warning: no previous prototype for 'release_r5_reset' [-Wmissing-prototypes] 4.warning: no previous prototype for 'enable_clock_r5' [-Wmissing-prototypes] Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20230609090531.31794-3-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-06-12arm64: versal: Add missing prototype for initialize_tcmAlgapally Santosh Sagar1-0/+1
Add the missing prototype pointed by below sparse warning warning: no previous prototype for 'initialize_tcm' [-Wmissing-prototypes] Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20230609090531.31794-2-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-06-12arm64: zynqmp: Fix lockstep mode cpu release functionalityVenkatesh Yadav Abbarapu1-0/+4
For lockstep mode, cpu_release function is expecting to execute on R5 core 0, if there is attempt to pass other than R5 core 0, through an error saying "Lockstep mode should run on R5 core 0 only". Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Link: https://lore.kernel.org/r/20230608032152.980-3-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-06-12global: Use proper project name U-BootMichal Simek10-10/+10
Use proper project name in comments, Kconfig, readmes. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Qu Wenruo <wqu@suse.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/0dbdf0432405c1c38ffca55703b6737a48219e79.1684307818.git.michal.simek@amd.com
2023-06-12arm64: versal-net: Add support for SPP production versionMichal Simek1-0/+1
Production version restarting platform version field from 0 that's why add new calculation to be able to use different DT for these platforms. Requested DT names for production silicons for IPP/SPP and EMU platform are versal-net-ipp-rev2.0.dts and versal-net-emu-rev2.0.dts. If platform version increase numbers revision can be even higher. As of today platform version is 2 that's why expected is rev2.2. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/691e166b3cf2643d7edf482bda5500163eecb35a.1684311689.git.michal.simek@amd.com
2023-06-12mach-zynqmp: handoff: Add missing headerAlgapally Santosh Sagar1-0/+1
Add missing prototype to fix the sparse warning. warning: no previous prototype for 'bl2_plat_get_bl31_params' [-Wmissing-prototypes] Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com> Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Link: https://lore.kernel.org/r/20230519113816.22083-3-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-06-12arm64: versal-net: Detect and display bootmodeAshok Reddy Soma1-0/+21
Read boodmode register using versal_net_get_bootmode() in board_late_init and prepare corresponding distro boot command sequence based on it. versal_net_get_bootmode() will be changed to use smc calls later, but for now directly reads the register. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20230516144753.30869-1-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-06-10ARM: dts: renesas: Add compatible properties to LAN8710A Ethernet PHYsGeert Uytterhoeven1-0/+2
Add compatible values to Ethernet PHY subnodes representing SMSC LAN8710A PHYs on RZ/A1 and R-Mobile A1 boards. This allows software to identify the PHY model at any time, regardless of the state of the PHY reset line. Ported from Linux kernel commit 1c65ef1c71e473c00f2a7a1b9c140f0b4862f282 . Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/247dc2074dae149af07b6d014985ad30eb362eda.1631174218.git.geert+renesas@glider.be --- Cc: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Michal Simek <michal.simek@amd.com> Cc: Nishanth Menon <nm@ti.com> Cc: Ramon Fried <rfried.dev@gmail.com>
2023-06-09dt: fwu: developerbox: enable fwu banks and mdata regionsJassi Brar1-3/+46
Specify Bank-0/1 and fwu metadata mtd regions. Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2023-06-08ARM: renesas: Add R8A77980 V3HSK board and CPLD codeValentine Barshak3-0/+49
Add board code for the R8A77980 V3HSK board. Add CPLD sysreset driver to the R-Car V3H SK board. Extracted from a larger patch by Valentine Barshak. Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> [Marek: Sync configs and board code with V3H Condor, squash CPLD driver in]
2023-06-08ARM: dts: renesas: Add R8A77980 V3HSK DTsValentine Barshak1-0/+292
Import R8A77980 V3HSK DTs from Linux 6.1.31, commit d2869ace6eeb ("Linux 6.1.31"). Extracted from a larger patch by Valentine Barshak. Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Sync with 6.1.31
2023-06-08ARM: renesas: Add R8A77970 V3MSK board and CPLD codeValentine Barshak3-0/+72
Add board code for the R8A77970 V3MSK board. Add CPLD sysreset driver to the R-Car V3M SK board. Extracted from a larger patch by Valentine Barshak. Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> [Marek: Sync configs and board code with V3M Eagle, squash CPLD driver in]
2023-06-08ARM: dts: renesas: Add R8A77970 V3MSK DTsValentine Barshak1-0/+303
Import R8A77970 V3MSK DTs from Linux 6.1.31, commit d2869ace6eeb ("Linux 6.1.31"). Extracted from a larger patch by Valentine Barshak. Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Sync with 6.1.31
2023-06-08ARM: rmobile: Identify R-Car D3 R8A77995 r1.1 SoCHai Pham1-2/+4
Add support to identify R8A77995 r1.1 SoC. Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> [Marek: Slight update to commit message, spell out the SoC model]
2023-06-08ARM: rmobile: Identify R-Car M3-W R8A7796 r1.1/1.2 SoCHiroyuki Yokoyama1-0/+7
r8a7796 cpu revision v1.2 has the same information as revision v1.1. This patch fixes revision display at startup to "rev 1.1/1.2". Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> [Marek: Slight update to commit message, spell out the SoC model]
2023-06-08efi_loader: add the number of image entries in efi_capsule_update_infoMasahisa Kojima1-2/+2
The number of image array entries global variable is required to support EFI capsule update. This information is exposed as a num_image_type_guids variable, but this information should be included in the efi_capsule_update_info structure. This commit adds the num_images member in the efi_capsule_update_info structure. All board files supporting EFI capsule update are updated. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-06-07sunxi: Fix typo in include guardSam Edwards1-1/+1
Signed-off-by: Sam Edwards <CFSworks@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2023-06-07sunxi: dts: arm/arm64: update devicetree files from Linux-v6.4-rc2Andre Przywara20-37/+259
Sync the devicetree files from the official Linux kernel tree, v6.4-rc2. This is covering both 64-bit and 32-bit Allwinner SoCs with Arm Ltd. cores, we skip the new RISC-V bits for now, as sunxi RISC-V support is still work in progress. Among smaller cosmetic changes, this adds a SATA regulator node which we need in U-Boot to get rid of hard-coded GPIOs. Also this updates the Allwinner F1C100s DTs, enabling USB support, and also adds the DTs for two new boards. As before, this omits the non-backwards compatible changes to the R_INTC controller, to remain compatible with older kernels. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-06-01arm: mach-k3: am625_init: Add Erratum WA for RTC startupWIP/2023-06-01-assorted-platform-updatesNishanth Menon1-0/+46
In the first silicon revision of the am62x family of SoCs, the hardware wakeup event cannot be used if software is unable to unlock the RTC device within one second after boot. To work around this limitation unlock RTC as soon as possible in the boot flow to maximize our chance of linux being able to use this device. Add the erratum i2327 workaround to initialize the RTC. Signed-off-by: Nishanth Menon <nm@ti.com> [bb@ti.com: rebased from 2021.01 and expanded commit and code messages] Signed-off-by: Bryan Brattlof <bb@ti.com>
2023-06-01arm: mach-k3: arm64-mmu: do not map ATF and OPTEE regions in A53 MMUKamlesh Gurudasani1-5/+59
ATF and OPTEE regions may be firewalled from non-secure entities. If we still map them for non-secure A53, speculative access may happen, which will not cause any faults and related error response will be ignored, but it's better to not to map those regions for non-secure A53 as there will be no actual access at all. Create separate table as ATF region is at different locations for am64 and am62/am62a. Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>
2023-06-01arm: mach-k3: j7200: clk-data.c: Add main_uart1 clock dataBhavya Kapoor1-2/+5
Add main_uart1 clocks in clk-data.c for J7200. Now, main_uart1 clocks will be set up while booting the J7200 SoC. Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
2023-06-01arm: mach-k3: j7200: dev-data.c: Add main_uart1 device dataBhavya Kapoor1-1/+2
Add device data for main_uart1 in dev-data.c for J7200. Now, main_uart1 will be powered on while booting the J7200 SoC. Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
2023-06-01arch: arm: mach-k3: j721e: add support for UDA FSUdit Kumar1-1/+1
When selecting UDA partition for booting. MMC read mode was selected as RAW. Due to growing/changing size of u-boot and tispl images. It will be better change to FS in case of UDA FS instead of adjusting offsets with new change. Signed-off-by: Udit Kumar <u-kumar1@ti.com>
2023-06-01arm: mach-k3: j721s2: clk-data.c: Add main_uart5 clock dataBhavya Kapoor1-2/+5
Add main_uart5 clocks in clk-data.c for J721S2. Now, main_uart5 clocks will be set up while booting the J721S2 SoC. Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com>
2023-06-01arm: mach-k3: j721s2: dev-data.c: Add main_uart5 device dataBhavya Kapoor1-1/+2
Add device data for main_uart5 in dev-data.c for J721S2. Now, main_uart5 will be powered on while booting the J721S2 SoC. Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com>
2023-06-01arm: mach-k3: j721e: clk-data.c: Add main_uart2 clock dataBhavya Kapoor1-2/+5
Add main_uart2 clocks in clk-data.c for J721E. Now, main_uart2 clocks will be set up while booting the J721E SoC. Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
2023-06-01arm: mach-k3: j721e: dev-data.c: Add main_uart2 device dataBhavya Kapoor1-1/+2
Add device data for main_uart2 in dev-data.c for J721E. Now, main_uart2 will be powered on while booting the J721E SoC. Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
2023-06-01arm: mach-k3: common: reorder removal of firewallsManorit Chawdhry2-20/+42
K3 devices have some firewalls set up by ROM that we usually remove so that the development is easy in HS devices. While removing the firewalls disabling a background region before disabling the foreground regions keeps the firewall in a state where all the transactions will be blacklisted until all the regions are disabled. This causes a race for some other entity trying to access that memory region before all the firewalls are disabled and causes an exception. Since there is no guarantee on where the background regions lie based on ROM configurations or no guarantee if the background regions will allow all transactions across the memory spaces, iterate the loop twice removing the foregrounds first and then backgrounds. Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-06-01Revert "arm: mach-k3: common: don't reconfigure background firewalls"Manorit Chawdhry2-8/+1
This reverts commit b8ebf24e7f4afb5093a31bdf122e1ed0781e5c3c. This patch seems to be fundamentally wrong and requires a different way on how the background firewalls should be configured so revert the patch Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-06-01arm64: Remove duplicated symbolsLeo Yan1-2/+0
When build U-boot with clang with using commands: $ make HOSTCC=clang xenguest_arm64_defconfig $ make HOSTCC=clang CROSS_COMPILE=aarch64-linux-gnu- \ CC="clang -target aarch64-linux-gnueabi" -j8 The compiler reports error: /tmp/start-acdf31.s:330:1: error: symbol '_start' is already defined _start: ^ Because the symbol '_start' has been defined twice, one is defined in arch/arm/cpu/armv8/start.S, another is defined in the header boot0-linux-kernel-header.h. To fix building failure, this patch removes the symbol '_start' from boot0-linux-kernel-header.h. Signed-off-by: Leo Yan <leo.yan@linaro.org>
2023-05-31arm: set alignment properly for asm funcsSam Edwards1-2/+2
ARM requires a 4-byte alignment on all ARM code (though this requirement is relaxed to 2-byte for some THUMB code) and we should be explicit about that here. GAS has its own fix for this[1] that forces proper alignment on any section containing assembled instructions, but this is not universal: Clang's and other gaslike assemblers lack this implicit alignment. Whether or not this is considered a bug in those assemblers, it is better to ask directly for what we want. [1]: https://sourceware.org/bugzilla/show_bug.cgi?id=12931 Signed-off-by: Sam Edwards <CFSworks@gmail.com>
2023-05-31arm: use asm-generic/unaligned.hJens Wiklander1-19/+2
Arm duplicates the content of asm-generic/unaligned.h, so use that file directly instead. Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-05-31include: Remove unused header filesTom Rini15-848/+0
As part of various code clean-ups we have on occasion missed removing unused header files. None of these files are referenced anywhere else at this point. Signed-off-by: Tom Rini <trini@konsulko.com>
2023-05-31arm: uniphier: fix header inclusion guardAndre Przywara1-1/+1
It seems like the header inclusion guard for some Uniphier DDR PHY header was misspelled. Make the preprocessor symbol for the #ifndef and #define lines the same, so that the double inclusion protection works as expected. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2023-05-31imx: fix header inclusion guardsAndre Przywara3-3/+3
It seems like the header inclusion guards for some IMX related headers were misspelled or got out of sync. Make the preprocessor symbols for the #ifndef and #define lines the same, so that the double inclusion protection works as expected. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2023-05-31arm: Remove ti816x_evm board and ti816x SoC supportTom Rini23-2186/+3
This platform is currently unmaintained and untested, so remove it. Further, as it is the only TI816X SoC example, remove related files as well. Signed-off-by: Tom Rini <trini@konsulko.com>
2023-05-30arm: apple: Add initial Apple M2 Pro/Max supportMark Kettenis1-3/+106
Apple's M2 Pro/Max SoC are somewhat similar to the M1 Pro/Max but need a tweaked memory map. USB, NVMe, UART and WDT are working with the existing drivers. Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
2023-05-30arm: mach-k3: security: separate out validating binary logicManorit Chawdhry3-8/+30
K3 GP devices allows booting the secure binaries on them by bypassing the x509 header on them. ATF and OPTEE firewalling required the rproc_load to be called before authentication. This change caused the failure for GP devices that strips off the headers. The boot vector had been set before the headers were stripped off causing the runtime stripping to fail and stripping becoming in-effective. Separate out the secure binary check on GP/HS devices so that the boot_vector could be stripped before calling rproc_load. This allows keeping the authentication later when the cluster is on along with allowing the stripping of the binaries in case of gp devices. Fixes: 1e00e9be62e5 ("arm: mach-k3: common: re-locate authentication for atf/optee") Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-05-30arm: mach-k3: Increase SYSFW max image sizeDave Gerlach1-2/+1
When booting with HS silicon, the system firmware image is 278270, which is slightly larger than currently allocated amount. This can cause unexpected behavior if this overlap interferes with other things in memory, so increase this with a slightly margin added as well to avoid any boot issues that can appear after system firmware gets loaded. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com> Reviewed-by: Dhruva Gole <d-gole@ti.com>
2023-05-30Kconfig: j721e: Change K3_MCU_SCRATCHPAD_BASE to non firewalled regionManorit Chawdhry1-1/+2
In non-combined boot flow for K3, all the firewalls are locked by default until sysfw comes up. Rom configures some of the firewall for its usage along with the SRAM for R5 but the PSRAM region is still locked. The K3 MCU Scratchpad for j721e was set to a PSRAM region triggering the firewall exception before sysfw came up. The exception started happening after adding multi dtb support that accesses the scratchpad for reading EEPROM contents. The commit changes R5 MCU scratchpad for j721e to an SRAM region. Old Map: ┌─────────────────────────────────────┐ 0x41c00000 │ SPL │ ├─────────────────────────────────────┤ 0x41c40000 (approx) │ STACK │ ├─────────────────────────────────────┤ 0x41c85b20 │ Global data │ │ sizeof(struct global_data) = 0xd8 │ ├─────────────────────────────────────┤ gd->malloc_base = 0x41c85bfc │ HEAP │ │ CONFIG_SYS_MALLOC_F_LEN = 0x70000 │ ├─────────────────────────────────────┤ CONFIG_SPL_BSS_START_ADDR │ SPL BSS │ (0x41cf5bfc) │ CONFIG_SPL_BSS_MAX_SIZE = 0xA000 │ └─────────────────────────────────────┘ CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX                 (0x41cffbfc) New Map: ┌─────────────────────────────────────┐ 0x41c00000 │ SPL │ ├─────────────────────────────────────┤ 0x41c40000 (approx) │ EMPTY │ ├─────────────────────────────────────┤ 0x41c81920 │ STACK │ │ SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000 │ ├─────────────────────────────────────┤ 0x41c85920 │ Global data │ │ sizeof(struct global_data) = 0xd8 │ ├─────────────────────────────────────┤ gd->malloc_base = 0x41c859f0 │ HEAP │ │ CONFIG_SYS_MALLOC_F_LEN = 0x70000 │ ├─────────────────────────────────────┤ CONFIG_SPL_BSS_START_ADDR │ SPL BSS │ (0x41cf59f0) │ CONFIG_SPL_BSS_MAX_SIZE = 0xA000 │ ├─────────────────────────────────────┤ 0x41cff9fc │ NEW MCU SCRATCHPAD │ │ SYS_K3_MCU_SCRATCHPAD_SIZE = 0x200 │ └─────────────────────────────────────┘ CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX                 (0x41cffbfc) Fixes: ab977c8b91b4 ("configs: j721s2_evm_r5: Enable support for building multiple dtbs into FIT") Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com> [n-francis@ti.com: SRAM allocation addressing diagram] Signed-off-by: Neha Francis <n-francis@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com>
2023-05-30arm: k3: config.mk: Add missing dependencies on tispl.bin HSAndrew Davis1-0/+2
When building for secure devices using non-buildman based image generation the signed tispl.bin file is called tispl.bin_HS. Also build the unsigned tispl.bin file as expected. Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-05-25Merge tag 'u-boot-imx-20230525' of ↵WIP/25May2023Tom Rini37-1616/+1163
https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20230525 ------------------- - i.MX93 series - Fixes CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/16412
2023-05-21imx9: Calculate DDR size from DDRC settingYe Li1-4/+17
To avoid using static setting for ECC enabled DDR size, switch to calculate DDR size from DDRC setting Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21ddr: imx93: update the ddr init to support mult setpointsJacky Bai2-2/+21
Update the DDR init flow for multi-setpoint support on i.MX93. A new fsp_cfg struct need to be added in the timing file to store the diff part of the DDRC and DRAM MR register for each setpoint. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21ddr: imx93: Add 625M bypass clock supportJacky Bai1-0/+3
Add 625M bypass clock that may be used DRAM 625M bypass mode support. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21ddr: imx9: Add workaround for DDRPHY rank-to-rank errataYe Li1-0/+2
According to DDRPHY errata, the Rank-to-Rank Spacing and tphy_rdcsgap specification does not include the Critical Delay Difference (CDD) to properly define the required rank-to-rank read command spacing after executing PHY training firmware. Following the errata workaround, at the end of data training, we get all CDD values through the MessageBlock, then re-configure the DDRC timing of WWT/WRT/RRT/RWT with comparing MAX CDD values. Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com>
2023-05-21arm: dts: imx93: add tmuPeng Fan1-0/+48
Add tmu nodes and thermal zone Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21arm: dts: imx93: sync device tree with LinuxPeng Fan4-652/+528
Sync device tree with next-20230426 Signed-off-by: Peng Fan <peng.fan@nxp.com>
generated by cgit v1.1 at 2024-09-06 19:34:22 +0000