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2014-12-22Exynos5800: The Peach-Pi board does not have a Parade video bridgeSjoerd Simons1-5/+0
Unlike the Peach-Pit board, there is no parade edp to lvds bridge on the Pi. So drop it from device-tree Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-12-22Odroid-XU3: Add support for Odroid-XU3Hyungwon Hwang3-1/+51
This patch adds support for Odroid-XU3. Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com> Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Tested-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-12-18ARM: UniPhier: select CONFIG_SPLMasahiro Yamada1-0/+1
Now UniPhier platform is only supported with SPL. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-18ARM: UniPhier: remove unnecessary ifdef conditionalMasahiro Yamada1-4/+0
init_page_table is only set on SPL. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-18ARM: UniPhier: fix property names of aliases nodes of device treesMasahiro Yamada4-15/+15
The property name of the "aliases" node should be "serial*" to assign a desired number for the device sequence number. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-16Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini8-43/+78
2014-12-11Merge git://git.denx.de/u-boot-dmTom Rini9-7/+616
2014-12-11Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini1-0/+5
Conflicts: board/freescale/mx6sxsabresd/mx6sxsabresd.c Signed-off-by: Tom Rini <trini@ti.com>
2014-12-11Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini15-5/+393
2014-12-11dm: i2c: tegra: Convert to driver modelSimon Glass4-7/+21
This converts all Tegra boards over to use driver model for I2C. The driver is adjusted to use driver model and the following obsolete CONFIGs are removed: - CONFIG_SYS_I2C_INIT_BOARD - CONFIG_I2C_MULTI_BUS - CONFIG_SYS_MAX_I2C_BUS - CONFIG_SYS_I2C_SPEED - CONFIG_SYS_I2C This has been tested on: - trimslice (no I2C) - beaver - Jetson-TK1 It has not been tested on Tegra 114 as I don't have that board. Acked-by: Heiko Schocher <hs@denx.de> Signed-off-by: Simon Glass <sjg@chromium.org>
2014-12-11ARM: tegra: Add support for nyan-big boardAllen Martin3-0/+376
Nyan-big is a Tegra124 clamshell board that is very similar to venice2, but it has a different panel, the sdcard cd and wp sense are flipped, and it has a different revision of the AS3722 PMIC. This is the Acer Chromebook 13 CB5-311-T7NN (13.3-inch HD, NVIDIA Tegra K1, 2GB). The display is not currently supported, so it should boot on other nyan-based Chromebooks also, but only the device tree for nyan-big is provided here. The device tree file is from Linux but with features removed which are unlikely to be supported in U-Boot soon (regulators, pinmux). Also the addresses are updated to 32-bit. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> (rebase, change to 'nyan-big', fix pinmux that resets nyan-big)
2014-12-11tegra: dts: Sync tegra124.dtsi with linux kernelSimon Glass1-0/+114
Sync this up with Linux v3.18-rc5. Exclude features that are unlikely to supported in U-Boot soon (regulators, pinmux). Also the addresses are updated to 32-bit. Otherwise it is the same. Also bring in the dt-bindings for pinctrl. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com>
2014-12-11dts: Bring in Chrome OS keyboard device tree definitionSimon Glass1-0/+105
This will be used by nyan-big, but bring it in in a separate patch since it will be common to other boards. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-12-11kconfig: ls102xa: Change the prompt messagesAlison Wang1-2/+2
As NOR/NAND/SD boot are all supported on LS1021AQDS/TWR boards, the prompt message "Support ls1021aqds_nor" in Kconfig is not clear. This patch changes it to "Support ls1021aqds". Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11ARM: ls102xa: Setting device's stream id for SMMUs.Xiubo Li1-0/+17
LS1 has 4 SMMUs for address translation of the masters. All the SMMUs' stream IDs are 8-bit. The address translation depends on the stream ID of the incoming transaction. Each master has unique stream ID assigned to it and is configurable through SCFG registers. The stream ID for the masters is identical and share the same register field of STREAM ID registers. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11ARM: ls102xa: allow all the peripheral access permission as R/W.Xiubo Li2-0/+119
The Central Security Unit (CSU) allows secure world software to change the default access control policies of peripherals/bus slaves, determining which bus masters may access them. This allows peripherals to be separated into distinct security domains. Combined with SMMU configuration of the system masters privileges, these features provide protection against indirect unauthorized access to data. For now we configure all the peripheral access permissions as R/W. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11ls102xa: changing a few targets' configurations.Xiubo Li2-0/+5
Enable hypervisors utilizing the ARMv7 virtualization extension on the LS1021A-QDS/TWR boards with the A7 core tile, we add the required configuration variable. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11ls1021a: adding a secondary core boot address and kick functionsXiubo Li1-0/+18
Define the board specific smp_set_cpu_boot_addr() function to set the start address for secondary cores in the LS1021A specific manner. Define the board specific smp_kick_all_cpus() functioin to boot a secondary core. Here the BRR contains control bits for enabling boot for each core. On exiting HRESET or PORESET, the RCW BOOT_HO field optionally allows for logical core 0 to be released for booting or to remain in boot holdoff. All other cores remain in boot holdoff until their corresponding bit is set. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11ARM: HYP/non-sec: Fix the ARCH Timer frequency setting.Xiubo Li1-2/+2
For some SoCs, the system clock frequency may not equal to the ARCH Timer's frequency. This patch uses the CONFIG_TIMER_CLK_FREQ instead of CONFIG_SYS_CLK_FREQ, then the system clock macro and arch timer macor could be set separately and without interfering each other. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11ARM: HYP/non-sec: add the pen address BE mode support.Xiubo Li1-0/+3
For some SoCs, the pen address register maybe in BE mode and the CPUs are in LE mode. This patch adds BE mode support for smp pen address. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11arm: ls102xa: Add NAND boot support for LS1021AQDS boardAlison Wang2-0/+7
This patch adds NAND boot support for LS1021AQDS board. SPL framework is used. PBL initialize the internal RAM and copy SPL to it, then SPL initialize DDR using SPD and copy u-boot from NAND flash to DDR, finally SPL transfer control to u-boot. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11arm: ls102xa: Add QSPI boot support for LS1021AQDS/TWR boardAlison Wang1-0/+1
This patch adds QSPI boot support for LS1021AQDS/TWR board. The QSPI boot image need to be programmed into the QSPI flash first. Then the booting will start from QSPI memory space. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11arm: ls102xa: Add SD boot support for LS1021AQDS boardAlison Wang3-0/+54
This patch adds SD boot support for LS1021AQDS board. SPL framework is used. PBL initialize the internal RAM and copy SPL to it, then SPL initialize DDR using SPD and copy u-boot from SD card to DDR, finally SPL transfer control to u-boot. Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Jason Jin <jason.jin@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11kconfig: ls1021a: add SUPPORT_SPLAlison Wang1-0/+2
Add SUPPORT_SPL feature for SD and NAND boot on LS1021AQDS and LS1021ATWR. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11arm: spl: Add I2C linker list in generic .ldsAlison Wang1-0/+3
On LS1, DDR is initialized by reading SPD through I2C interface in SPL code. For I2C, ll_entry_count() is called, and it returns the number of elements of a linker-generated array placed into subsection of .u_boot_list section specified by _list argument. So add I2C linker list in the generic .lds to fix the issue about using I2C in SPL. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11arm: ls102xa: Update PCIe dts node statusMinghuan Lian2-0/+16
The patch changes PCIe dts node status to 'disabled' if the corresponding controller is disabled according to serdes protocol. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11arm: ls102xa: clear EPU registers for deep sleepchenhui zhao5-0/+143
After wakeup from deep sleep, Clear EPU registers as early as possible to prevent from possible issue. It's also safe to clear at normal boot. Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11arm: ls102xa: fixed a bus frequency setting errorTang Yuantian1-1/+1
The bus frequency in SOC node should be clock frequency of platform. That is not true if it is devided by 2. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-10Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini6-15/+28
2014-12-10Merge branch 'rmobile' of git://git.denx.de/u-boot-shTom Rini7-0/+215
2014-12-10arm: rmobile: Add mmc.h for sh_mmcif of rmobileNobuhiro Iwamatsu1-0/+14
R-Mobile and R-Car ARM SoCs use sh_mmcif as MMC host driver. This adds arch-rmobile/mmc.h that defines mmcif_mmc_init(). Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-12-09stv0991: enable ethernet supportVikas Manocha6-0/+100
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
2014-12-09stv0991: Add basic stv0991 architecture supportVikas Manocha15-0/+607
stv0991 architecture support added. It contains the support for following blocks - Timer - uart Signed-off-by: Vikas Manocha <vikas.manocha@st.com> [trini: Add arch/arm/cpu/armv7/Makefile hunk] Signed-off-by: Tom Rini <trini@ti.com>
2014-12-08Merge branch 'master' of git://git.denx.de/u-boot-tiTom Rini10-22/+45
2014-12-08Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini17-107/+558
2014-12-09ARM: UniPhier: detect the number of flash banks at run-timeMasahiro Yamada4-40/+108
Some UniPhier boards are equipped with an expansion slot that some optional SRAM/NOR-flash cards can be attached to. So, run-time detection of the number of flash banks would be more user-friendly. Until this commit, UniPhier boards have achieved this by (ab)using board_flash_wp_on() because the boot failed if flash_size got zero. Fortunately, this problem was solved by commit 70879a92561a (flash: do not fail even if flash_size is zero). Now it is possible to throw away such a tricky workaround. This commit also enables CONFIG_SYS_MAX_FLASH_BANKS_DETECT for further refactoring. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-09ARM: UniPhier: extend register area of init page table for PH1-sLD3Masahiro Yamada1-1/+6
0x20000000-0x2fffffff: assigned to ARM mpcore (sLD3 only) 0xf0000000-0xffffffff: assigned to Denali NAND controller (sLD3 only) Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-09ARM: UniPhier: add device tree sources for PH1-sLD3Masahiro Yamada3-0/+186
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-09ARM: UniPhier: add more device nodes to device treeMasahiro Yamada6-15/+220
Add I2C controller and NAND controller devices. Fix indentation too. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-08Kbuild: introduce Makefile in arch/$ARCH/Daniel Schwierzeck1-0/+29
Introduce a Makefile under arch/$ARCH/ and include it in the top Makefile (similar to Linux kernel). This allows further refactoringi like moving architecture-specific code out of global makefiles, deprecating config variables (CPU, CPUDIR, SOC) or deprecating arch/$ARCH/config.mk. In contrary to Linux kernel, U-Boot defines the ARCH variable by Kconfig, thus the arch Makefile can only included conditionally after the top config.mk. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-08ARM: rpi: rename rpi_b to rpiStephen Warren1-3/+3
The U-Boot port runs on a variety of RPi models, not just the B. So, rename the port to something slightly more generic. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2014-12-08ARM: rpi_b: detect board revisionStephen Warren1-0/+33
Detect the board revision early during boot, and print the decoded model name. Eventually, this information can be used for tasks such as: - Allowing/preventing USB device mode; some models have a USB device on- board so only host mode makes sense. Others connect the SoC directly to the USB connector, so device-mode might make sense. - The on-board USB hub/Ethernet requires different GPIOs to enable it, although luckily the default appears to be fine so far. - The compute module contains an on-board eMMC device, so we could store the environment there. Other models use an SD card and so don't support saving the environment (unless we store it in a file on the FAT boot partition...) Set $fdtfile based on this information. At present, the mainline Linux kernel doesn't contain a separate DTB for most models, but I hope that will change soon. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2014-12-08ARM: UniPhier: merge UniPhier config headers into a single fileMasahiro Yamada1-3/+1
Some configurations have been moved to Kconfig and the difference among the config headers of UniPhier SoC variants is getting smaller and smaller. Now is a good time to merge them into a single file. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-08ARM: UniPhier: move support card select to KconfigMasahiro Yamada1-0/+23
There are two kinds of expansion boards which are often used for the UniPhier platform and they are only exclusively selectable. It can be better described by the "choice" menu of Kconfig. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-08ARM: UniPhier: move CONFIG_UNIPHIER_SMP to KconfigMasahiro Yamada1-0/+4
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-08ARM: UniPhier: use boot_is_swapped() macro for readabilityMasahiro Yamada1-10/+10
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-07ARM: UniPhier: remove Denali NAND controller fixup codeMasahiro Yamada1-38/+0
This ugly work-around code is unnecessary since commit f09eb52b3ffc (mtd: denali: set some registers after nand_scan_ident()). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-06socfpga: correctly increment freeze_controller_base addressDinh Nguyen2-5/+2
Correctly increment the base address of the freeze controller. And since SYSMGR_FRZCTRL_VIOCTRL_SHIFT is not needed, remove it from the include file. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Vince Bridgers <vbridger@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Cc: Wolfgang Denk <wd@denx.de>
2014-12-06socfpga: add missing struct member fifo_triple_byteDinh Nguyen1-0/+1
socfpga_scan_manager structure was missing a data member. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Vince Bridgers <vbridger@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Cc: Wolfgang Denk <wd@denx.de>
2014-12-06arm: socfpga: Add missing DW master SPI clock prototyp to clock_manager.hStefan Roese1-0/+1
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
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