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2020-08-11arm: dts: k3-j7200-common-proc-board: Enable CPSW2G portVignesh Raghavendra2-0/+58
Enable CPSW2G port to support networking in U-Boot Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-08-11ARM: dts: k3-j7200-mcu-wakeup: Add CPSW2G supportVignesh Raghavendra1-0/+116
Add MCU NAVSS, UDMA and CPSW2G DT nodes. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-08-11ARM: dts: k3-j7200: Add HyperBus and HyperFlash nodesVignesh Raghavendra3-2/+64
J7200 SoM has Cypress HyperFlash connected to HyperBus interface, add DT entries for the same. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-08-11ARM: dts: k3-j7200: Add wkup gpio nodeVignesh Raghavendra2-0/+23
Add wkup_gpio0 node required for detecting whether board mux is set HyperFlash. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-08-11arm: dts: k3-j7200: Add USB related DT entriesVignesh Raghavendra4-0/+80
Add USB related DT entries to enable USB device mode. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-08-11arm: dts: k3-j7200: Add R5 specific dts supportDave Gerlach3-1/+2396
Add the basic a72 basic dts for j7200. Following nodes were supported: - UART - MMC SD - I2C - TISCI communication - LPDDR with 1600MTs configuration. Signed-off-by: Andrew F. Davis <afd@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2020-08-11arm: dts: k3-j7200: Add dts supportLokesh Vutla7-1/+863
Add the basic a72 dts for j7200. Following nodes were supported: - UART - MMC SD - I2C - TISCI communication Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Vishal Mahaveer <vishalm@ti.com> Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-08-11arm: mach-k3: j7200: Detect if ROM has already loaded sysfwLokesh Vutla3-1/+12
Detect if sysfw is already loaded by ROM and pass this information to sysfw loader. Based on this information sysfw loader either loads the sysfw image from boot media or just receives the boot notification message form sysfw. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Suman Anna <s-anna@ti.com>
2020-08-11arm: mach-k3: j7200: Add support for storing extended boot info from ROMLokesh Vutla3-2/+15
Starting J7200 SoC, ROM supports for loading sysfw directly from boot image. ROM passes this information on number of images that are loaded to bootloader at certain location. Add support for storing this information before it gets corrupted. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Suman Anna <s-anna@ti.com>
2020-08-11arm: mach-k3: j7200: Add support for SOC detectionLokesh Vutla3-0/+12
The J7200 SoC is a part of the K3 Multicore SoC architecture platform. It is targeted for automotive gateway, vehicle compute systems, Vehicle-to-Vehicle (V2V) and Vehicle-to-Everything (V2X) applications. The SoC aims to meet the complex processing needs of modern embedded products. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, two clusters of lockstep capable dual Cortex-R5F MCUs and a Centralized Device Management and Security Controller (DMSC). * Configurable L3 Cache and IO-coherent architecture with high data throughput capable distributed DMA architecture under NAVSS. * Integrated Ethernet switch supporting up to a total of 4 external ports in addition to legacy Ethernet switch of up to 2 ports. * Upto 1 PCIe-GEN3 controller, 1 USB3.0 Dual-role device subsystems, 20 MCANs, 3 McASP, eMMC and SD, OSPI/HyperBus memory controller, I3C and I2C, eCAP/eQEP, eHRPWM among other peripherals. * One hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL management. See J7200 Technical Reference Manual (SPRUIU1, June 2020) for further details: https://www.ti.com/lit/pdf/spruiu1 Add support for detection J7200 SoC Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com>
2020-08-11arm: mach-k3: j721e: Fix unlocking control module registersLokesh Vutla1-2/+2
In main control mmr there is no partition 4 and partition 6 is available only on J721e. Fix the same in ctrl_mmr_unlock function Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Suman Anna <s-anna@ti.com>
2020-08-11arm: mach-k3: j721e: Add detection for j721eLokesh Vutla5-0/+18
Add an api soc_is_j721e(), and use it to enable certain functionality that is available only on j721e. This detection is needed when DT is not available. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com>
2020-08-11arm: mach-k3: sysfw-loader: Add support for rom loading sysfw imageLokesh Vutla4-21/+43
Starting J7200 SoC, ROM supports for loading sysfw directly from boot image. In such cases, SPL need not load sysfw from boot media, but need to receive boot notification message from sysfw. So separate out remoteproc calls for system controller from sysfw loader and just receive the boot notification if sysfw is already loaded. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Suman Anna <s-anna@ti.com>
2020-08-11arm: mach-k3: Move mmr_unlock to a common locationLokesh Vutla4-20/+11
mmr_unlock api is common for all k3 devices. Move it to a common location. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Suman Anna <s-anna@ti.com>
2020-08-11arm: mach-k3: Fix platform hang when SPL_MULTI_DTB_FIT is not enabledJean-Jacques Hiblot1-1/+7
If SPL_MULTI_DTB_FIT is not enabled, then CONFIG_SPL_OF_LIST is not defined And in turn tispl.bin ends up not embedding any DTB. Fixing it by using CONFIG_DEFAULT_DEVICE_TREE if SPL_OF_LIST is empty. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-08-11board: ti: j721e: Probe eeprom only when CONFIG_TI_I2C_BOARD_DETECT is definedLokesh Vutla1-1/+2
Guard all eeprom probe with TI_I2C_BOARD_DETECT to avoid reading eeprom when eeprom is not available Reviewed-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2020-08-11arm: dts: k3-am654-base-board: Add support for USB0 in SPLFaiz Abbas1-0/+27
Add nodes for USB0 in SPL to enable USB host boot mode Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-08-11arm: dts: k3-am654-r5-base-board: Add USB0 nodesFaiz Abbas1-0/+35
Add USB0 nodes and set them to host mode to support USB host and peripheral boot modes Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-08-11arm: mach-k3: am6_init: Add support for USB boot modeFaiz Abbas3-1/+9
Add support for identifying USB host and device boot modes Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-08-11arm: mach-k3: am6_init: Do USB fixups to facilitate host and device boot modesFaiz Abbas1-0/+40
U-boot only supports either USB host or device mode for a node at a time in dts. To support both host and dfu bootmodes, set "peripheral" as the default dr_mode but fixup property to "host" if host bootmode is detected. This needs to happen before the dwc3 generic layer binds the usb device to a host or device driver. Therefore, add an fdtdec_setup_board() implementation to fixup the dt based on the boot mode. Also use the same fixup function to set the USB-PCIe Serdes mux to PCIe in both the host and device cases. This is required for accessing the interface at USB 2.0 speeds. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-08-11arm: mach-k3: am6_init: Gate mmc related configurations with the appropriate ↵Faiz Abbas1-1/+4
config Gate mmc related system related configurations with DM_MMC to avoid build errors when MMC is not enabled Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-08-11arm: mach-k3: sysfw-loader: Add support to load SYSFW from USBFaiz Abbas1-0/+11
Add support for loading system firmware from a USB mass storage device Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-08-11armv7R: K3: am654: Use full malloc in SPL both pre and post relocFaiz Abbas1-0/+18
In order to be able to use things like file system drivers early on in SPL (before relocation) in a memory-constrained environment when DDR is not yet available we cannot use the simple malloc scheme which does not implement the freeing of previously allocated memory blocks. To address this issue go ahead and enable the use of the full malloc by manually initializing the required functionality inside board_init_f by creating a full malloc pool inside the pre-relocation malloc pool. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-08-11arm: dts: k3-j721e: Fix interconnect node namesSuman Anna1-2/+2
The various CBASS interconnect nodes on K3 J721E SoCs are defined using the node name "interconnect". This is not a valid node name as per the dt-schema. Fix these node names to use the standard name used for SoC interconnects, "bus". Signed-off-by: Suman Anna <s-anna@ti.com>
2020-08-11arm: dts: k3-am65: Fix interconnect node namesSuman Anna1-3/+3
The various CBASS interconnect nodes on K3 AM65x SoCs are defined using the node name "interconnect". This is not a valid node name as per the dt-schema. Fix these node names to use the standard name used for SoC interconnects, "bus". Signed-off-by: Suman Anna <s-anna@ti.com>
2020-08-11ARM: omap3: evm: Complete DM_ETH and DM_USB migrationsDerald D. Woods3-0/+23
This commit completes the migrations for DM_ETH and DM_USB. The board is now consistent with omap3_beagle and other remaining OMAP3 boards. Cc: Tom Rini <trini@konsulko.com> Cc: Adam Ford <aford173@gmail.com> Signed-off-by: Derald D. Woods <woods.technical@gmail.com>
2020-08-11arm: mach-k3: Clean non-coherent lines out of L3 cacheAndrew F. Davis2-0/+25
When switching on or off the ARM caches some care must be taken to ensure existing cache line allocations are not left in an inconsistent state. An example of this is when cache lines are considered non-shared by and L3 controller even though the lines are shared. To prevent these and other issues all cache lines should be cleared before enabling or disabling a coherent master's cache. ARM cores and many L3 controllers provide a way to efficiently clean out all cache lines to allow for this, unfortunately there is no such easy way to do this on current K3 MSMC based systems. We could explicitly clean out every valid external address tracked by MSMC (all of DRAM), or we could attempt to identify only the set of addresses accessed by a given boot stage and flush only those specifically. This patch attempts the latter. We start with cleaning the SPL load address. More addresses can be added here later as they are identified. Note that we perform a flush operation for both the flush and invalidate operations, this is not a typo. We do this to avoid the situation that some ARM cores will promote an invalidate to a clean+invalidate, but only emit the invalidation operation externally, leading to a loss of data. Signed-off-by: Andrew F. Davis <afd@ti.com> Tested-by: Faiz Abbas <faiz_abbas@ti.com>
2020-08-11arm: dts: k3: Add RTI watchdogsJan Kiszka2-0/+27
Add DT entries for main domain watchdog0 and 1 instances on the J721e well as RTI1-based watchdog on the AM65x. RTI0 does not work for this purpose on the AM65x, so leave it out. On AM65x, we mark the power-domain as shared because RTI firmware such as https://github.com/siemens/k3-rti-wdt may request it as well in order to prevent accidental shutdown of the watchdog. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2020-08-07board: presidio: add LED supportJway Lin1-0/+31
Add LED support for Cortina Access Presidio Engineering Board Signed-off-by: Jway Lin <jway.lin@cortina-access.com> Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com> Reviewed-by: Simon Glass <sjg@chromium.org> CC: Simon Glass <sjg@chromium.org>
2020-08-06arm: mvebu: Update CRS305-1G-4S board flash layoutLuka Kovacic1-5/+5
Update the MikroTik CRS305-1G-4S flash layout to support redundant UBI partitions. Additionally enable the UBI commands in crs305-1g-4s_defconfig. Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Jakov Petrina <jakov.petrina@sartura.hr> Reviewed-by: Stefan Roese <sr@denx.de>
2020-08-06arm: mvebu: Add CRS328-4C-20S-4S boardLuka Kovacic5-0/+185
MikroTik CRS328-4C-20S-4S board has a switch chip with an integrated Marvell Prestera 98DX3236 CPU. This commit includes two board variants, namely the factory default one and a Bit variant. The Bit board variant has a bigger Macronix flash. Add basic U-Boot, UART and SPI flash support. Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Jakov Petrina <jakov.petrina@sartura.hr> Reviewed-by: Stefan Roese <sr@denx.de>
2020-08-06arm: mvebu: Add CRS326-24G-2S boardLuka Kovacic5-0/+185
MikroTik CRS326-24G-2S board has a switch chip with an integrated Marvell Prestera 98DX3236 CPU. This commit includes two board variants, namely the factory default one and a Bit variant. The Bit board variant has a bigger Macronix flash. Add basic U-Boot, UART and SPI flash support. Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Jakov Petrina <jakov.petrina@sartura.hr> Reviewed-by: Stefan Roese <sr@denx.de>
2020-08-06arm: mvebu: Add CRS305-1G-4S Bit boardLuka Kovacic2-0/+44
MikroTik CRS305-1G-4S Bit board has a switch chip with an integrated Marvell Prestera 98DX3236 CPU. The Bit board variant is added, which has a bigger Macronix flash. Add basic U-Boot, UART and Winbond SPI flash support. Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Jakov Petrina <jakov.petrina@sartura.hr> Reviewed-by: Stefan Roese <sr@denx.de>
2020-08-05ARM: add Kconfig option for PSCI 0.1Icenowy Zheng1-0/+4
We still have some platforms that only implements functionalities in PSCI 0.1 (e.g. Allwinner ARMv7 SoCs). Add a Kconfig option for exporting only PSCI 0.1. The code to export PSCI 0.1 is still available and gets activated by this patch. In addition, default ARCH_SUNXI U-Boot PSCI implementation to export PSCI 0.1, to fix poweroff/reboot regression on Allwinner multi-core ARMv7 SoCs. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2020-08-04arm: Add SPL build check to SPL early bss clearBrian Moyer1-5/+5
SPL_CLEAR_BSS is called regardless of build type if CONFIG_SPL_EARLY_BSS is defined. Add a guard for CONFIG_SPL_BUILD to fix. Signed-off-by: Brian Moyer <bdm310@gmail.com>
2020-08-04Merge tag 'u-boot-imx-20200804' of ↵Tom Rini16-95/+436
https://gitlab.denx.de/u-boot/custodians/u-boot-imx For 2020.10 ----------- - fixes for Toradex board - fix warnings from previous PR - HAB: reset instead of panic after failure - new board: MYiR Tech MYS-6ULX - mx6cuboxi: use OF_PLATDATA - further changes for DM Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/714513163
2020-08-03mediatek: Drop dm.h header fileSimon Glass1-1/+1
This header file should not be included in other header files. Remove it and use a forward declaration instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-03thermal: Drop dm.h header fileSimon Glass1-0/+1
This header file should not be included in other header files. Remove it and use a forward declaration instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-03sf: Drop dm.h header file from spi_flash.hSimon Glass2-0/+2
This header file should not be included in other header files. Remove it and use a forward declaration instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-03ARM: imx: hab: panic on authentication failureMarek Vasut1-4/+2
Instead of hang()ing the system and thus disallowing any automated recovery possibility from a HAB authentication failure, panic() . The panic() function can be configured to hang() the system after printing an error message, however the default is to reset the system instead. This allows redundant boot to work correctly. In case the primary or secondary image cannot be authenticated, the system reboots and bootrom can try to start the other one. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2020-08-03imx: Add MYiR Tech MYS-6ULX supportParthiban Nallathambi6-0/+295
MYS-6ULX is single board computer (SBC) comes with eMMC or NAND based on imx6ULL SoC from NXP and provision for expansion board. This commit adds support only for SBC with NAND. CPU: Freescale i.MX6ULL rev1.1 528 MHz (running at 396 MHz) CPU: Commercial temperature grade (0C to 95C) at 45C Reset cause: WDOG Model: MYiR i.MX6ULL MYS-6ULX Single Board Computer with NAND Board: MYiR MYS-6ULX 6ULL Single Board Computer DRAM: 256 MiB NAND: 256 MiB MMC: FSL_SDHC: 0 In: serial@2020000 Out: serial@2020000 Err: serial@2020000 Net: FEC0 Working: - Eth0 - MMC/SD - NAND - UART 1 - USB host Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
2020-08-01efi_loader: use CONFIG_STACK_SIZE in the UEFI sub-systemHeinrich Schuchardt1-17/+0
The Kconfig symbol CONFIG_STACK_SIZE is used both by ARM and Microblaze with the same meaning. Move it to menu 'General setup' so that we can use it for all architectures. Use the value of CONFIG_STACK_SIZE instead of a hard coded 16 MiB value for reserving memory in the UEFI sub-system. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-07-29Merge tag 'dm-pull-28jul20' of git://git.denx.de/u-boot-dmTom Rini20-119/+178
Use binman instead of one of the Rockchip build scripts Refactor to allow any arch to create SPI-flash images New button uclass
2020-07-29Merge https://gitlab.denx.de/u-boot/custodians/u-boot-stmTom Rini25-183/+1572
- fix SPL boot issue due to early dbgmcu_init() call - fix SPL boot issue due to dcache memory region configuration - add support of CONFIG_ENV_IS_IN_MMC - add specific SD/eMMC partition for U-Boot enviromnent - enable env in SPL - use "env info -q" to remove log during boot - remove env location override for dh_stm32mp1 - update management of misc_read - check result of find_mmc_device in stm32prog - use regulator_set_enable_if_allowed for disabling vdd supply in usbphyc - enable CMD_ADTIMG flag to handle Android images - device tree alignment with Linux Kernel v5.8-rc1 - remove hnp-srp-disable for usbotg on dk1 - add reset support to uart nodes on stm32mp15x - use correct weak function name spl_board_prepare_for_linux - use cd-gpios for ST and DHSOM boards - add seeed studio odyssey-stm32mp157c board support - move ethernet PHY into SoM DT - add DHSOM based DRC02 board support
2020-07-29arch: arm: use dt and UCLASS_SYSCON to get gic lpi detailsRayagonda Kokatanur4-36/+61
Use device tree and UCLASS_SYSCON driver to get Generic Interrupt Controller (GIC) lpi address and maximum GIC redistributors count. Also update Kconfig to select REGMAP and SYSCON when GIC_V3_ITS is enabled. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-29arch: arm: use dt and UCLASS_IRQ to get gic detailsRayagonda Kokatanur1-7/+66
Use device tree and UCLASS_IRQ driver to get following Generic Interrupt Controller (GIC) details, -GIC Distributor interface (GICD) base address and -GIC Redistributors (GICR) base address. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-29gpio: do not include <asm/arch/gpio.h> on TARGET_BCMNS3Rayagonda Kokatanur1-1/+2
As no gpio.h is defined for this architecture, to avoid compilation failure, do not include <asm/arch/gpio.h> for arch bcmns3. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-29board: ns3: define ddr memory layoutRayagonda Kokatanur1-0/+23
Add both DRAM banks memory information and the corresponding MMU page table mappings. Signed-off-by: Bharat Kumar Reddy Gooty <bharat.gooty@broadcom.com> Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-29board: ns3: add api to save boot parameters passed from BL31Abhishek Shah2-0/+35
Add API to save boot parameters passed from BL31 Use assembly implementation of save_boot_params instead of c function. Because generally ATF does not set up SP_EL2 on exiting. Thus, usage of a C function immediately after exiting with no stack setup done by ATF explicitly, may cause SP_EL2 to be not sane, which in turn causes a crash if this boot was not lucky to get an SP_EL2 in valid range. Replace C implementation with assembly one which does not use stack this early, and let u-boot to set up its stack later. Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com> Signed-off-by: Rajesh Ravi <rajesh.ravi@broadcom.com> Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com> Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-29arm: cpu: armv8: add L3 memory flush supportRayagonda Kokatanur3-0/+95
Add L3 memory flush support for NS3. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Reviewed-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-07-15 23:18:43 +0000