aboutsummaryrefslogtreecommitdiff
path: root/arch/arm/mach-sunxi
AgeCommit message (Collapse)AuthorFilesLines
2023-04-12sunxi: arm64: boot0.h: runtime check for RVBAR addressAndre Przywara1-0/+14
Some SoCs of the H616 family use a die variant, that puts some CPU power and reset control registers at a different address. There are examples of two instances of the same board, using different die revisions of the otherwise same H313 SoC. We need to write to a register in that block *very* early in the SPL boot, to switch the core to AArch64. Since the devices are otherwise indistinguishable, let the SPL code read that die variant and use the respective RVBAR address based on that. That is a bit tricky, since we need to do that in hand-coded AArch32 machine language, shared by all 64-bit SoCs. To avoid build dependencies in this mess, we always provide two addresses to choose from, and just give identical values for all other SoCs. This allows the same code to run on all 64-bit SoCs, and controls this switch behaviour purely from Kconfig. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-04-12sunxi: boot0.h: allow RVBAR MMIO address customisationAndre Przywara1-0/+12
To switch the ARMv8 Allwinner SoCs into the 64-bit AArch64 ISA, we need to program the 64-bit start code address into an MMIO mapped register that shadows the architectural RVBAR register. This address is SoC specific, with just two versions out there so far. Now a third address emerged, on a *variant* of an existing SoC (H616). Change the boot0.h start code to make this address a Kconfig selectable option, to allow easier maintenance. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-04-12sunxi: Add TPR2 parameter for H616 DRAM driverJernej Skrabec3-24/+74
It turns out that some H616 and related SoCs (like H313) need TPR2 parameter for proper working. Add it. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12sunxi: Parameterize some of H616 DDR3 timingsJernej Skrabec1-4/+5
Currently twr2rd, trd2wr and twtp are constants, but according to vendor driver they are calculated from other values. Do that here too, in preparation for later introduction of new parameter. While at it, introduce constant for t_wr_lat, which was incorrectly calculated from tcl before. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12sunxi: Parameterize "unknown feature" in H616 DRAM driverJernej Skrabec2-11/+42
Part of the code, previously known as "unknown feature", also doesn't have constant values. They are derived from TPR0 parameter in vendor DRAM code. Let's move that code to separate function and introduce TPR0 parameter here too, to ease adding new boards. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Acked-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12sunxi: Parameterize bit delay code in H616 DRAM driverJernej Skrabec2-49/+158
These values are highly board specific and thus make sense to add parameter for them. To ease adding support for new boards, let's make them same as in vendor DRAM settings. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Acked-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12sunxi: Make bit delay function in H616 DRAM code voidJernej Skrabec1-3/+1
Mentioned function result is always true and result isn't checked anyway. Let's make it void. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12sunxi: Always configure ODT on H616 DRAMJernej Skrabec2-3/+2
Vendor H616 DRAM code always configure part which we call ODT configuration. Let's reflect that here too. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12sunxi: Convert H616 DRAM options to single settingJernej Skrabec2-129/+106
Vendor DRAM settings use TPR10 parameter to enable various features. There are many mores features that just those that are currently mentioned. Since new will be added later and most are not known, let's reuse value from vendor DRAM driver as-is. This will also help adding support for new boards. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12sunxi: parameterize H616 DRAM ODT valuesJernej Skrabec2-22/+52
While ODT values for same memory type are similar, they are not necessary the same. Let's parameterize them and make parameter same as in vendor DRAM settings. That way it will be easy to introduce new board support. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12sunxi: cosmetic: Fix H616 DRAM driver code styleJernej Skrabec1-37/+37
Fix code style for pointer declaration. This is just cosmetic change to avoid checkpatch errors in later commits. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12sunxi: Fix write to H616 DRAM CR registerJernej Skrabec1-1/+1
Vendor DRAM code actually writes to whole CR register and not just sets bit 31 in mctl_ctrl_init(). Just to be safe, do that here too. Acked-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-01-23sunxi: eMMC: support TOC0 on boot partitionsAndre Przywara1-2/+9
To determine whether we have been booted from an eMMC boot partition, we replay some of the checks that the BROM must have done to successfully load the SPL. This involves a checksum check, which currently relies on the SPL being wrapped in an "eGON" header. If a board has secure boot enabled, the BROM will only accept the "TOC0" format, which is internally very different, but uses the same checksumming algorithm. Actually the only difference for calculating the checksum is that the size of the SPL is stored at a different offset. Do a header check to determine whether we deal with an eGON or TOC0 format, then set the SPL size accordingly. The rest of the code is unchanged. This fixes booting from an eMMC boot partition on devices with secure boot enabled, like the Remix Mini PC. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Samuel Holland <samuel@sholland.org>
2023-01-21sunxi: remove CONFIG_MMC?_CD_PINAndre Przywara1-27/+0
For legacy reasons we were defining the card detect GPIO for all sunxi boards in each board's defconfig. There is actually no need for a card-detect check in the SPL code (which consequently has been removed already), and also in U-Boot proper we have DM code to query the CD GPIO name from the device tree. That means we don't have any user of that information left, so can remove the definitions from the defconfigs. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Samuel Holland <samuel@sholland.org> Tested-by: Samuel Holland <samuel@sholland.org>
2023-01-21sunxi: fel: drop redundant "control register" save/restoreAndre Przywara1-1/+0
For some reasons shrouded in mystery, the code saving the FEL state was saving the SCTLR register twice, with the second copy trying to justify itself by using its ancient "control register" alias name. Drop the redundant second copy, both from the fel_stash data structure, and also the code saving and restoring it. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Samuel Holland <samuel@sholland.org> Tested-by: Samuel Holland <samuel@sholland.org>
2022-12-21Merge tag 'v2023.01-rc4' into nextTom Rini2-6/+6
Prepare v2023.01-rc4 Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-14sunxi: board: annotate #endif linesAndre Przywara2-6/+6
The legacy Allwinner code is cluttered with #ifdef's, some of them even nested, which makes the code hard to read and error prone. Eventually we will get rid of most of them, but for now let's at least annotate the #endif lines with the corresponding symbol the bracket started with. Reviewed-by: Samuel Holland <samuel@sholland.org> Tested-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-12-05global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_*Tom Rini3-17/+17
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-31Rename CONFIG_SYS_TEXT_BASE to CONFIG_TEXT_BASESimon Glass2-2/+2
The current name is inconsistent with SPL which uses CONFIG_SPL_TEXT_BASE and this makes it imposible to use CONFIG_VAL(). Rename it to resolve this problem. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-10-30video: Rename CONFIG_DM_VIDEO to CONFIG_VIDEOSimon Glass1-3/+3
Now that all the old code is gone, rename this option. Driver model migration is now complete. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-10-19suniv: add UART1 supportAndre Przywara1-0/+4
Some boards with the Allwinner F1C100s family SoCs use UART1 for its debug UART, so define the pins for the SPL and the pinmux name and mux value for U-Boot proper. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2022-10-19suniv: move SKIP_LOWLEVEL_INIT_ONLY into KconfigAndre Przywara1-0/+2
So far we stated the lack of a lowlevel() init function for the Allwinner F1C100s board by defining the respective SKIP_* symbol in the board's defconfig. However we don't expect any *board* to employ such low level code, so expect this to be never used for the ARMv5 Allwinner SoCs. Select the appropriate symbols in the Kconfig, so that we can remove them from the defconfig, and avoid putting them in future defconfigs for other boards. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2022-10-19sunxi: Kconfig: introduce SUNXI_MINIMUM_DRAM_MBAndre Przywara1-0/+12
Traditionally we assumed that every Allwinner board would come with at least 256 MB of DRAM, and set our DRAM layout accordingly. This affected both the default load addresses, but also U-Boot's own address expectations (like being loaded at 160 MB). Some SoCs come with co-packaged DRAM, but only provide 32 or 64MB. So far we special-cased those *chips*, as there was only one chip per DRAM size. However new chips force us to take a more general approach. Introduce a Kconfig symbol, which provides the minimum DRAM size of the board. If nothing else is specified, we use 256 MB, and default to smaller values for those co-packaged SoCs. Then select the different DRAM maps according to this new symbol, so that different SoCs with the same DRAM size can share those definitions. Inspired by an idea from Icenowy. This is just refactoring: compiled for all boards before and after this patch: the binaries were identical. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2022-10-19sunxi: fix SUNIV build when enabling D-CacheIcenowy Zheng1-1/+1
The enable_caches function in architecture-specific board code is only necessary for V7A CPUs, code for both V8A and ARM926 have already declared this function. Only provide our implementation of enable_caches() for V7A CPUs. Signed-off-by: Icenowy Zheng <uwu@icenowy.me> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-10-18sunxi: SPL SPI: Add SPI boot support for the Allwinner H616 SoCAndre Przywara2-13/+16
The H616 SoC uses the same SPI IP as the H6, also shares the same clocks and reset bits. The only real difference is a slight change in the pin assignment: the H6 uses PC5, the H616 PC4 instead. This makes for a small change in our spi0_pinmux_setup() routine. Apart from that, just extend the H6 #ifdef guards to also cover the H616, using the shared CONFIG_SUN50I_GEN_H6 symbol. Also use this symbol for the Kconfig dependency. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Ivan Shishkin <s45rus@gmail.com>
2022-09-29treewide: Drop image_header_t typedefSimon Glass1-2/+2
This is not needed and we should avoid typedefs. Use the struct instead and rename it to indicate that it really is a legacy struct. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-23board_f: Fix types for board_get_usable_ram_top()Pali Rohár1-1/+1
Commit 37dc958947ed ("global_data.h: Change ram_top type to phys_addr_t") changed type of ram_top member from ulong to phys_addr_t but did not changed types in board_get_usable_ram_top() function which returns value for ram_top. So change ulong to phys_addr_t type also in board_get_usable_ram_top() signature and implementations. Fixes: 37dc958947ed ("global_data.h: Change ram_top type to phys_addr_t") Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-07-18sunxi: Move INITIAL_USB_SCAN_DELAY to driver KconfigSamuel Holland1-9/+0
This option is used only by the phy-sun4i-usb driver, which does not inherently depend on the ARM architecture. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-07-18sunxi: lcd: Move range from kconfig description to definition.Michal Suchanek1-1/+2
KConfig has range option, use it instead of notice in the option descrition. Signed-off-by: Michal Suchanek <msuchanek@suse.de> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-06-28spl: Move SPL_LDSCRIPT defaults to one placeTom Rini1-4/+0
We want to keep all of the default values for SPL_LDSCRIPT in the same place both for overall clarity as well as not polluting unrelated config files. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-05-24sunxi: Remove obsolete Kconfig selectionsSamuel Holland1-3/+0
ARCH_SUNXI selects DM_SERIAL, so the condition can never be satisfied. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-05-24sunxi: board: Fix UART PortF pinmux setupAndre Przywara1-6/+7
When CONFIG_UART0_PORT_F is defined, we try to configure two PortF pins (usually used for the SD card) as UART0. Some SoCs use the mux value of 3 for this, while others use 4. The combination of Kconfig symbols we currently use was not quite right: we mis-configure the A31, A64, H6 and H616. Going through the list in the pinctrl driver, there are only a few older SoCs that use a value of 4, so revert the #ifdef clause, and name those explicitly, instead of the other way around. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Samuel Holland <samuel@sholland.org>
2022-05-23ARM: dts: sunxi: A13/A31/A23/A33: Sync from Linux v5.18-rc1Samuel Holland1-1/+1
Copy the devicetree source for the A10s/A13/GR8, A31(s), and A23/A33/R16 SoCs and all existing boards from the Linux v5.18-rc1 tag. These changes are combined into one commit due to interdependencies: - The unit addresses were removed from bitbanged I2C buses, which drives a Kconfig default change. This affects sun5i-a13-utoo-p66.dts and sun6i-a31-colombus.dts. - The pinctrl nodes were renamed, including some used by the shared header sunxi-reference-design-tablet.dtsi. To maintain ABI compatibility with existing LTS kernels, one change moving some IP blocks to the r_intc interrupt controller is excluded. This effectively reverts Linux commits 994e5818392c and 9fdef3c3d8c2. This commit renames the file sun8i-r16-nintendo-nes-classic-edition.dts to sun8i-r16-nintendo-nes-classic.dts to match the Linux tree. This commit also adds the following new board devicetrees: - sun5i-a13-licheepi-one.dts - sun5i-a13-pocketbook-touch-lux-3.dts - sun5i-gr8-evb.dts - sun8i-a23-ippo-q8h-v1.2.dts - sun8i-a23-ippo-q8h-v5.dts - sun8i-a33-et-q8-v1.6.dts - sun8i-a33-ippo-q8h-v1.2.dts - sun8i-r16-nintendo-super-nes-classic.dts As with the other SoCs, updates of note are conversion of GPIO pull-up from pinconf to GPIO flags and renaming the detection GPIO properties in the USB PHY nodes. Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-04-05sunxi: eMMC: Improve automatic boot source detectionAndre Przywara1-0/+83
When the Allwinner BROM loads the SPL from an eMMC boot partition, it sets the boot source byte to the same value as when booting from the user data partition. This prevents us from determining the boot source to load U-Boot proper from the proper partition for sure. The generic SPL MMC code already looks at the enabled boot partition number, to load U-Boot proper from the same partition, but this fails if there is nothing bootable in this partition, as the BROM then silently falls back to the user data partition, which the SPL misses. To learn about the actual boot source anyway, we repeat the algorithm the BROM used to select the boot partition in the first place: - Test EXT_CSD[179] to check if an eMMC boot partition is enabled. - Test EXT_CSD[177] to check for valid MMC interface settings. - Check if BOOT_ACK is enabled. - Check the beginning of the first sector for a valid eGON signature. - Load the whole SPL. - Recalculate the checksum to verify the SPL is valid. If one of those steps fails, we bail out and continue loading from the user data partition. Otherwise we load from the selected boot partition. Since the boot source is needed twice in the boot process, we cache the result of this test to avoid doing this costly test multiple times. This allows the very same image file to be put onto an SD card, into the eMMC user data partition or into the eMMC boot partition, and safely loads the whole of U-Boot from there. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04sunxi: clock: H6: Adjust PLL LDO before clock setupJernej Skrabec1-0/+7
BSP boot0 adjust PLL LDO regulator before clocks are initialized. Let's do that. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04sunxi: clock: H6/H616: Add resistor calibrationJernej Skrabec1-2/+7
BSP boot0 executes resistor calibration before clocks are initialized. Let's do that. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04sunxi: prcm: Add a few registersJernej Skrabec3-6/+13
H6 and H616 SPL code has a few writes to unknown PRCM registers. Now that we know what they are, let's replace magic offsets with proper register names. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04sunxi: H3: fix non working console on uart2Angelo Dureghello1-0/+4
Fix non working console on uart2, that seems releated to both Allwinner H2+ and H3. Signed-off-by: Angelo Dureghello <angelo.dureghello@timesys.com> [Andre: remove H2+, rearrange pin setup order] Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04sunxi: Support building a SPL as a TOC0 imageSamuel Holland1-0/+2
Now that mkimage can generate TOC0 images, and the SPL can interpret them, hook up the build infrastructure so the user can choose which image type to build. Since the absolute load address is stored in the TOC0 header, that information must be passed to mkimage. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04sunxi: Support SPL in both eGON and TOC0 imagesSamuel Holland2-11/+32
SPL uses the image header to detect the boot device and to find the offset of the next U-Boot stage. Since this information is stored differently in the eGON and TOC0 image headers, add code to find the correct value based on the image type currently in use. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04sunxi: Remove options and setup code for I2C2-I2C4Samuel Holland1-22/+0
These options are not currently enabled anywhere. Any new users should use DM clocks and pinctrl. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-03-26sunxi: Fix old GMAC pinmux setupAndre Przywara1-1/+0
Commit 5bc4cd05d7d4 ("sunxi: move non-essential code out of s_init()") moved the call to eth_init_board() from s_init() into board_init_f(). This means it's now only called from the SPL, which makes sense for most of the other moved low-level functions. However the GMAC pinmux and clock setup in eth_init_board() was not happy about that, so it broke the sun7i GMAC. Since Ethernet is of no use in the SPL anyway, just move the call into board_init(), which is only run in U-Boot proper. This fixes Ethernet operation for the A20 SoCs, which broke in v2022.04-rc1, with the above mentioned commit. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Tested-by: Petr Štetiar <ynezz@true.cz> [a20-olinuxino-lime2]
2022-03-12Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-spiWIP/12Mar2022Tom Rini1-3/+0
- sunXi SPI fixups (Andre) - bcm iproc qspi (Rayagonda)
2022-03-10sunxi: Kconfig: Fix up SPI configurationAndre Przywara1-3/+0
Commit 7945caf22c44 ("arm: sunxi: Enable SPI/SPI-FLASH support for A64") selected CONFIG_SPI by default on all Allwinner A64 boards, even though only 4 out of the 14 A64 boards have a SPI flash chip. All other SoCs had to manually select DM_SPI and friends, even though they are a platform property (the sunxi SPI driver is DM_SPI only). Clean this up to allow easy selection of SPI flash support in U-Boot proper, by selecting DM_SPI and DM_SPI_FLASH *if* CONFIG_SPI is selected, for *all* Allwinner SoCs. This simplifies the defconfig for two Libretech boards already. Also remove the forced CONFIG_SPI from the A64 Kconfig, instead let the four boards which allow SPI booting select this explicitly. Any board wishing to support SPI flash in U-Boot proper now just defines CONFIG_SPI and CONFIG_SPI_FLASH_<vendor> in its defconfig, Kconfig takes care of the rest. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2022-03-03mach-sunxi: Enable SPI boot for SUNIV and licheepi nanoJesse Taube1-1/+1
Enable SPI boot in SPL on SUNIV architecture and use it in the licheepi nano that uses the F1C100s. Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-03-03mach-sunxi: Add SPL SPI boot for SUNIVJesse Taube1-7/+17
The SUNIV SoCs come with a sun6i-style SPI controller at the base address of sun4i SPI controller. The module clock of the SPI controller is missing which leaves us running directly from the AHB clock, which is set to 200MHz. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> [Icenowy: Original implementation] Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> [Jesse: adaptation to Upstream U-Boot] Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-03-03mach-sunxi: Add boot device detection for SUNIV/F1C100sJesse Taube1-27/+37
In contrast to other Allwinner SoCs the F1C100s BROM does not store a boot source indicator in the eGON header in SRAM. This leaves the SPL guessing where we were exactly booted from, and for instance trying the SD card first, even though we booted from SPI flash. By inspecting the BROM code and by experimentation, Samuel found that the top of the BROM stack contains unique pointers for each of the boot sources, which we can use as a boot source indicator. This patch removes the existing board_boot_order bodge and replace it with a proper boot source indication function. The only caveat is that this only works in the SPL, as the SPL header gets overwritten with the exception vectors, once U-Boot proper takes over. Always return MMC0 as the boot source, when called from U-Boot proper, as a placeholder for now, until we find another way. Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> Suggested-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-02-04mach-sunxi: Add support for SUNIV architectureIcenowy Zheng5-31/+105
Add support for the suniv architecture, which is newer ARM9 SoCs by Allwinner. The design of it seems to be a mixture of sun3i, sun4i and sun6i. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-02-04sunxi: Add F1C100s DRAM initial supportIcenowy Zheng3-0/+426
Add support for F1C100s internal dram controller. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-02-04mach-sunxi: Move timer code to mach folderJesse Taube2-0/+120
Both armv7 and arm926ejs use this timer code so move it to mach-sunxi. Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
generated by cgit v1.1 at 2024-09-16 04:36:20 +0000