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2023-07-21sunxi: H616: add LPDDR3 DRAM supportMikhail Kalashnikov1-0/+8
The H616 SoC has support for several types of DRAM: DDR3, LPDDR3, DDR4 and LPDDR4. At the moment, the driver only supports DDR3 memory. Let's extend the driver to support the LPDDR3 memory. All "magic" values obtained from the boot0. Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com> Acked-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-07-21sunxi: H616: add DRAM type selectionMikhail Kalashnikov1-1/+9
Allwinner H616 SoC supports several types of DRAM memory. To further integrate other types of memory, we need to add this delimitation. Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-07-21sunxi: Kconfig: rework PHY_USB_SUN4I selectionAndre Przywara1-11/+0
At the moment we use "select" in each Allwinner SoC's Kconfig section to include the USB PHY driver in the build. This means it cannot be disabled via Kconfig, although USB is not really a strictly required core functionality, and a particular board might not even include USB ports. Rework the Kconfig part by removing the "select" lines for each SoC's section, and instead letting it default to "y" in the PHY driver section itself. We use "depends on !" to exclude the few SoCs we don't support (yet). The Allwinner V3s does not enable USB (PHY) support at the moment, even though it should work: let the PHY default to "n" to keep the current behaviour. Also the MUSB USB driver directly calls some functions from the PHY driver, so let the former depend on the PHY driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Tested-by: Sam Edwards <CFSworks@gmail.com>
2023-04-12sunxi: arm64: boot0.h: runtime check for RVBAR addressAndre Przywara1-0/+14
Some SoCs of the H616 family use a die variant, that puts some CPU power and reset control registers at a different address. There are examples of two instances of the same board, using different die revisions of the otherwise same H313 SoC. We need to write to a register in that block *very* early in the SPL boot, to switch the core to AArch64. Since the devices are otherwise indistinguishable, let the SPL code read that die variant and use the respective RVBAR address based on that. That is a bit tricky, since we need to do that in hand-coded AArch32 machine language, shared by all 64-bit SoCs. To avoid build dependencies in this mess, we always provide two addresses to choose from, and just give identical values for all other SoCs. This allows the same code to run on all 64-bit SoCs, and controls this switch behaviour purely from Kconfig. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-04-12sunxi: boot0.h: allow RVBAR MMIO address customisationAndre Przywara1-0/+12
To switch the ARMv8 Allwinner SoCs into the 64-bit AArch64 ISA, we need to program the 64-bit start code address into an MMIO mapped register that shadows the architectural RVBAR register. This address is SoC specific, with just two versions out there so far. Now a third address emerged, on a *variant* of an existing SoC (H616). Change the boot0.h start code to make this address a Kconfig selectable option, to allow easier maintenance. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-04-12sunxi: Add TPR2 parameter for H616 DRAM driverJernej Skrabec1-0/+6
It turns out that some H616 and related SoCs (like H313) need TPR2 parameter for proper working. Add it. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12sunxi: Parameterize "unknown feature" in H616 DRAM driverJernej Skrabec1-0/+6
Part of the code, previously known as "unknown feature", also doesn't have constant values. They are derived from TPR0 parameter in vendor DRAM code. Let's move that code to separate function and introduce TPR0 parameter here too, to ease adding new boards. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Acked-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12sunxi: Parameterize bit delay code in H616 DRAM driverJernej Skrabec1-0/+18
These values are highly board specific and thus make sense to add parameter for them. To ease adding support for new boards, let's make them same as in vendor DRAM settings. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Acked-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12sunxi: Always configure ODT on H616 DRAMJernej Skrabec1-1/+1
Vendor H616 DRAM code always configure part which we call ODT configuration. Let's reflect that here too. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12sunxi: Convert H616 DRAM options to single settingJernej Skrabec1-32/+6
Vendor DRAM settings use TPR10 parameter to enable various features. There are many mores features that just those that are currently mentioned. Since new will be added later and most are not known, let's reuse value from vendor DRAM driver as-is. This will also help adding support for new boards. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-04-12sunxi: parameterize H616 DRAM ODT valuesJernej Skrabec1-0/+15
While ODT values for same memory type are similar, they are not necessary the same. Let's parameterize them and make parameter same as in vendor DRAM settings. That way it will be easy to introduce new board support. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-01-21sunxi: remove CONFIG_MMC?_CD_PINAndre Przywara1-27/+0
For legacy reasons we were defining the card detect GPIO for all sunxi boards in each board's defconfig. There is actually no need for a card-detect check in the SPL code (which consequently has been removed already), and also in U-Boot proper we have DM code to query the CD GPIO name from the device tree. That means we don't have any user of that information left, so can remove the definitions from the defconfigs. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Samuel Holland <samuel@sholland.org> Tested-by: Samuel Holland <samuel@sholland.org>
2022-10-30video: Rename CONFIG_DM_VIDEO to CONFIG_VIDEOSimon Glass1-3/+3
Now that all the old code is gone, rename this option. Driver model migration is now complete. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-10-19suniv: move SKIP_LOWLEVEL_INIT_ONLY into KconfigAndre Przywara1-0/+2
So far we stated the lack of a lowlevel() init function for the Allwinner F1C100s board by defining the respective SKIP_* symbol in the board's defconfig. However we don't expect any *board* to employ such low level code, so expect this to be never used for the ARMv5 Allwinner SoCs. Select the appropriate symbols in the Kconfig, so that we can remove them from the defconfig, and avoid putting them in future defconfigs for other boards. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2022-10-19sunxi: Kconfig: introduce SUNXI_MINIMUM_DRAM_MBAndre Przywara1-0/+12
Traditionally we assumed that every Allwinner board would come with at least 256 MB of DRAM, and set our DRAM layout accordingly. This affected both the default load addresses, but also U-Boot's own address expectations (like being loaded at 160 MB). Some SoCs come with co-packaged DRAM, but only provide 32 or 64MB. So far we special-cased those *chips*, as there was only one chip per DRAM size. However new chips force us to take a more general approach. Introduce a Kconfig symbol, which provides the minimum DRAM size of the board. If nothing else is specified, we use 256 MB, and default to smaller values for those co-packaged SoCs. Then select the different DRAM maps according to this new symbol, so that different SoCs with the same DRAM size can share those definitions. Inspired by an idea from Icenowy. This is just refactoring: compiled for all boards before and after this patch: the binaries were identical. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2022-10-18sunxi: SPL SPI: Add SPI boot support for the Allwinner H616 SoCAndre Przywara1-1/+1
The H616 SoC uses the same SPI IP as the H6, also shares the same clocks and reset bits. The only real difference is a slight change in the pin assignment: the H6 uses PC5, the H616 PC4 instead. This makes for a small change in our spi0_pinmux_setup() routine. Apart from that, just extend the H6 #ifdef guards to also cover the H616, using the shared CONFIG_SUN50I_GEN_H6 symbol. Also use this symbol for the Kconfig dependency. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Ivan Shishkin <s45rus@gmail.com>
2022-07-18sunxi: Move INITIAL_USB_SCAN_DELAY to driver KconfigSamuel Holland1-9/+0
This option is used only by the phy-sun4i-usb driver, which does not inherently depend on the ARM architecture. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-07-18sunxi: lcd: Move range from kconfig description to definition.Michal Suchanek1-1/+2
KConfig has range option, use it instead of notice in the option descrition. Signed-off-by: Michal Suchanek <msuchanek@suse.de> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-06-28spl: Move SPL_LDSCRIPT defaults to one placeTom Rini1-4/+0
We want to keep all of the default values for SPL_LDSCRIPT in the same place both for overall clarity as well as not polluting unrelated config files. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-05-24sunxi: Remove obsolete Kconfig selectionsSamuel Holland1-3/+0
ARCH_SUNXI selects DM_SERIAL, so the condition can never be satisfied. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-05-23ARM: dts: sunxi: A13/A31/A23/A33: Sync from Linux v5.18-rc1Samuel Holland1-1/+1
Copy the devicetree source for the A10s/A13/GR8, A31(s), and A23/A33/R16 SoCs and all existing boards from the Linux v5.18-rc1 tag. These changes are combined into one commit due to interdependencies: - The unit addresses were removed from bitbanged I2C buses, which drives a Kconfig default change. This affects sun5i-a13-utoo-p66.dts and sun6i-a31-colombus.dts. - The pinctrl nodes were renamed, including some used by the shared header sunxi-reference-design-tablet.dtsi. To maintain ABI compatibility with existing LTS kernels, one change moving some IP blocks to the r_intc interrupt controller is excluded. This effectively reverts Linux commits 994e5818392c and 9fdef3c3d8c2. This commit renames the file sun8i-r16-nintendo-nes-classic-edition.dts to sun8i-r16-nintendo-nes-classic.dts to match the Linux tree. This commit also adds the following new board devicetrees: - sun5i-a13-licheepi-one.dts - sun5i-a13-pocketbook-touch-lux-3.dts - sun5i-gr8-evb.dts - sun8i-a23-ippo-q8h-v1.2.dts - sun8i-a23-ippo-q8h-v5.dts - sun8i-a33-et-q8-v1.6.dts - sun8i-a33-ippo-q8h-v1.2.dts - sun8i-r16-nintendo-super-nes-classic.dts As with the other SoCs, updates of note are conversion of GPIO pull-up from pinconf to GPIO flags and renaming the detection GPIO properties in the USB PHY nodes. Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-04-04sunxi: Support building a SPL as a TOC0 imageSamuel Holland1-0/+2
Now that mkimage can generate TOC0 images, and the SPL can interpret them, hook up the build infrastructure so the user can choose which image type to build. Since the absolute load address is stored in the TOC0 header, that information must be passed to mkimage. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-04-04sunxi: Remove options and setup code for I2C2-I2C4Samuel Holland1-22/+0
These options are not currently enabled anywhere. Any new users should use DM clocks and pinctrl. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-03-12Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-spiWIP/12Mar2022Tom Rini1-3/+0
- sunXi SPI fixups (Andre) - bcm iproc qspi (Rayagonda)
2022-03-10sunxi: Kconfig: Fix up SPI configurationAndre Przywara1-3/+0
Commit 7945caf22c44 ("arm: sunxi: Enable SPI/SPI-FLASH support for A64") selected CONFIG_SPI by default on all Allwinner A64 boards, even though only 4 out of the 14 A64 boards have a SPI flash chip. All other SoCs had to manually select DM_SPI and friends, even though they are a platform property (the sunxi SPI driver is DM_SPI only). Clean this up to allow easy selection of SPI flash support in U-Boot proper, by selecting DM_SPI and DM_SPI_FLASH *if* CONFIG_SPI is selected, for *all* Allwinner SoCs. This simplifies the defconfig for two Libretech boards already. Also remove the forced CONFIG_SPI from the A64 Kconfig, instead let the four boards which allow SPI booting select this explicitly. Any board wishing to support SPI flash in U-Boot proper now just defines CONFIG_SPI and CONFIG_SPI_FLASH_<vendor> in its defconfig, Kconfig takes care of the rest. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2022-03-03mach-sunxi: Enable SPI boot for SUNIV and licheepi nanoJesse Taube1-1/+1
Enable SPI boot in SPL on SUNIV architecture and use it in the licheepi nano that uses the F1C100s. Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-02-04mach-sunxi: Add support for SUNIV architectureIcenowy Zheng1-1/+11
Add support for the suniv architecture, which is newer ARM9 SoCs by Allwinner. The design of it seems to be a mixture of sun3i, sun4i and sun6i. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-02-04sunxi: move Cortex SMPEN setting into start.SAndre Przywara1-2/+4
According to their TRMs, Cortex ARMv7 CPUs with SMP support require the ACTLR.SMPEN bit to be set as early as possible, before any cache or TLB maintenance operations are done. As we do those things still in start.S, we need to move the SMPEN bit setting there, too. This introduces a new ARMv7 wide symbol and code to set bit 6 in ACTLR very early in start.S, and moves sunxi boards over to use that instead of the custom code we had in our board.c file (where it was called technically too late). In practice we got away with this so far, because at this point all the other cores were still in reset, so any broadcasting would have been ignored anyway. But it is architecturally cleaner to do it early, and we move a core specific piece of code out of board.c. This also gets rid of the ARM_CORTEX_CPU_IS_UP kludge I introduced a few years back, and moves the respective logic into the new Kconfig entry. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-01-30sunxi: Add option to prevent booting on power plug-inChris Morgan1-0/+10
For sunxi boards with the AXP209, AXP221, AXP809, and AXP818 PMICs (plus possibly others, I only confirmed the datasheets for these), it is sometimes desirable to not boot whenever the device is plugged in. An example would be when using the NTC CHIP inside a PocketCHIP. This provides a configurable option to check if bit 0 of register 0 of the PMIC says it was powered because of a power button press (0) or a plug-in event (1). If the value is 1 and this option is selected, the device shuts down shortly after printing a message to console stating the reason why it's shutting down. Powering up the board with the power button is not affected. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> [Andre: reword to speak of boot, remove #ifdefs] Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-12sunxi: Enable DM_I2C for all sunxi boardsSamuel Holland1-3/+0
Now that the last users of legacy I2C (outside of SPL) have been resolved, we can enable DM_I2C at the sunxi architecture level. Reviewed-by: Heiko Schocher <hs@denx.de> Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-12sunxi: video: Convert panel I2C to use DM_I2CSamuel Holland1-15/+6
Two displays supported by the sunxi display driver (each one used by a single board) require initialization over I2C. Both previously used i2c_soft; replace this with the i2c-gpio instance that already exists in those boards' device trees (sun5i-a13-utoo-p66 and sun6i-a31-colombus). Since the i2c-gpio nodes are not referenced by any other node in the device trees (the device trees have no panel node), the I2C bus is selected by its node name. This panel initialization code was the only i2c_soft user, so the i2c_soft GPIO setup code can be removed now as well. Reviewed-by: Heiko Schocher <hs@denx.de> Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-12sunxi: pmic_bus: Use the DM PMIC interface when possibleSamuel Holland1-0/+2
The pmic_bus functions are used in both SPL (for regulator setup) and U-Boot proper (for regulator setup, SID access, GPIO, and poweroff). Currently, pmic_bus conflicts with DM_I2C because it uses the legacy I2C interface. This commit makes pmic_bus dual-compatible with either the legacy I2C functions or the newly-added PMIC_AXP driver (which uses DM_I2C). In turn, this allows platforms to start transitioning to DM_I2C in U-Boot proper, without breaking boards that still depend on the legacy I2C interface for other reasons. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-12i2c: Add a DM_I2C driver for the sun8i RSB controllerSamuel Holland1-11/+7
This bus controller is used to communicate with an X-Powers AXP PMIC. Currently, various drivers access PMIC registers through a platform- specific non-DM "pmic_bus" interface, which depends on the legacy I2C framework. In order to convert those drivers to use DM_PMIC, this bus needs a DM_I2C driver. Refactor the rsb functions to take the base address as a parameter, and implement both the existing interface (which is still needed in SPL) and the DM_I2C interface on top of them. The register for switching between I2C/P2WI/RSB mode is the same across all PMIC variants, so move that to the common header. There are only a couple of pairs of hardware/runtime addresses used across all PMIC variants. So far the code expected only the "primary" pair, but some PMICs like the AXP305 and AXP805 use the secondary pair, so add support for that to the DM driver as well. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-12i2c: Add a DM_I2C driver for the sun6i P2WI controllerSamuel Holland1-12/+2
This bus controller is used to communicate with an X-Powers AXP PMIC. Currently, various drivers access PMIC registers through a platform- specific non-DM "pmic_bus" interface, which depends on the legacy I2C framework. In order to convert those drivers to use DM_PMIC, this bus needs a DM_I2C driver. Refactor the p2wi functions to take the base address as a parameter, and implement both the existing interface (which is still needed in SPL) and the DM_I2C interface on top of them. The register for switching between I2C/P2WI/RSB mode is the same across all PMIC variants. Move that to the common header, so it can be used by both interface implementations. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-12sunxi: pmic_bus: Fix Kconfig dependenciesSamuel Holland1-1/+2
AXP_PMIC_BUS enables communication with a specific AXP PMIC at a PMIC-dependent I2C/P2WI/RSB bus address. It is automatically selected as a dependency of the PMIC driver. It should not be selectable by the user when no PMIC is chosen. AXP_GPIO uses the pmic_bus functions, and also depends on a specific PMIC header to pick up register definitions. Both of these changes have no impact on any existing configs, since the code does not compile if the dependencies are not met. Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-12sunxi: Select SUN8I_RSB more carefullySamuel Holland1-2/+3
SUN8I_RSB should not be selected by MACH_SUN8I, because the hardware is not present in half of those SoCs (H3/H5, R40, and V3s). Move the selection to the SoCs where the hardware actually exists. As it currently stands, selecting that option also requires using it in some way, which is not the case for one A80 board. Since we have only three A80 boards in total, we select it their via their defconfigs. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Samuel Holland <samuel@sholland.org> [Andre: fixing up Sunchip_CX-A99 build] Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-11sunxi: Simplify MMC pinmux selectionSamuel Holland1-17/+4
Only one board, Yones Toptech BD1078, actually uses a non-default MMC pinmux. All other uses of these symbols select the default value or an invalid value. To simplify things, remove support for the unused pinmux options, and convert the remaining option to a Boolean. This allows the pinmux to be chosen by the preprocessor, instead of having the code parse a string at runtime (for a build-time option!). Not only does this reduce code size, but it also allows this Kconfig option to be used in a table-driven DM pinctrl driver. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-08-31Kconfig: Remove all default n/no optionsMichal Simek1-13/+0
default n/no doesn't need to be specified. It is default option anyway. Signed-off-by: Michal Simek <michal.simek@xilinx.com> [trini: Rework FSP_USE_UPD portion] Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-30Convert CONFIG_SYS_I2C_LEGACY to Kconfig and add CONFIG_[ST]PL_SYS_I2C_LEGACYTom Rini1-0/+7
First, we convert CONFIG_SYS_I2C_LEGACY to Kconfig. Next, as you cannot have SYS_I2C_LEGACY and DM_I2C at the same time, introduce CONFIG_SPL_SYS_I2C_LEGACY so that we can enable the legacy option only in SPL. Finally, for some PowerPC cases we also need CONFIG_TPL_SYS_I2C_LEGACY support. Convert all of the existing users to one or more symbols. Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-10mmc: sunxi: Enable "new timing mode" on all new SoCsAndre Przywara1-0/+3
All SoCs since the Allwinner A64 (H5, H6, R40, H616) feature the so called "new timing mode", so enable this in Kconfig for those SoCs. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-07-10sunxi: H616: Enable full 4GB of DRAMAndre Przywara1-2/+2
The H616 is our first supported Allwinner SoC which goes beyond the 4GB address space "barrier", by having more than 32 address bits. Lift the preliminary 3GB DRAM limit for the H616, and update the page table setup on the way, to actually map that last GB as well. As not all devices are actually capable of dealing with more than 32 bits (the DMA in the EMAC for instance), we also limit U-Boot's own DRAM usage to 4GB on the way. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-05-13arm: sunxi: add support for DIP detection to CHIP boardKory Maincent1-0/+9
Add the extension_board_scan specific function to scan the information of the EEPROM on one-wire and fill the extension struct. Add the Kconfig symbol to enable the needs to detect DIPs. Signed-off-by: Kory Maincent <kory.maincent@bootlin.com> Reviewed-by: Maxime Ripard <maxime@cerno.tech> Acked-by: Andre Przywara <andre.przywara@arm.com>
2021-04-16sunxi: video: select dw-hdmi in Kconfig, not MakefileJernej Skrabec1-0/+1
Currently sunxi Makefile manually specifies full path to dw-hdmi common code. However, that is not needed because it can be selected in Kconfig instead. Select proper symbol in Kconfig and drop path from Makefile. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-03-03video: sunxi_display: Convert to DM_VIDEOJagan Teki1-4/+5
DM_VIDEO migration deadline is already expired, but around 80 Allwinner boards are still using video in a legacy way: ===================== WARNING ====================== This board does not use CONFIG_DM_VIDEO Please update the board to use CONFIG_DM_VIDEO before the v2019.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/migration.rst for more info. ==================================================== Convert the legacy video driver over to the DM_VIDEO framework. This is a minimal conversion: it doesn't use the DT for finding its resources, nor does it use DM clocks or DM devices for the outputs (LCD, HDMI, CVBS). Tested in Bananapi M1+ Plus 1920x1200 HDMI out. (Jagan) Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> [Andre: rebase and smaller fixes] Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-25sunxi: Add support for H616 SoCJernej Skrabec1-1/+10
H616 is very similar to H6 so most of the infrastructure can be reused. However, two big differences are that it doesn't have functional SRAM A2 which is usually used for TF-A and it doesn't have ARISC co-processor. It also needs bigger SPL size - 48 KiB. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-01-25sunxi: Add H616 DRAM supportJernej Skrabec1-0/+43
Allwinner H616 supports many types of DRAM. Most notably it supports LPDDR4. However, all commercially available boards at this time use only DDR3, so this commit adds only DDR3 support. Controller and MBUS are very similar to H6 but PHY is completely unknown. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Acked-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-01-25sunxi: Add support for I2C on H6 like SoCsJernej Skrabec1-1/+1
I2C support, especially R_I2C port, will be needed in future. Upcoming support for H616 will need R_I2C to adjust DRAM voltage. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-01-25sunxi: Introduce common symbol for H6 like SoCsJernej Skrabec1-6/+13
It turns out that there are at least 2 other SoCs which have basically the same memory map, similar clocks and other features as H6. It's very likely that we'll see more such SoCs in the future. In order to ease porting to new SoCs and lower ifdef clutter, introduce common symbol for them. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-01-11sunxi: board: add a config option to fixup a Bluetooth addressAndre Heider1-0/+11
Some Bluetooth controllers, like the BCM4345C5 of the Orange Pi 3, ship with the controller default address. Add a config option to fix it up so it can function properly. Signed-off-by: Andre Heider <a.heider@gmail.com> Tested-by: Ondrej Jirman <megous@megous.com> Acked-by: Maxime Ripard <mripard@kernel.org> [rebased] Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2020-11-17sunxi: add V3/S3 supportIcenowy Zheng1-2/+1
Allwinner V3/Sochip S3 uses the same die with Allwinner V3s/S3L, but V3 comes with no co-packaged DDR (DDR3 is usually used externally), and S3L comes with co-packaged DDR3. Add support for Allwinner V3/S3 chips by add SoC names to original V3s choice, and allow to select DDR3. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
generated by cgit v1.1 at 2024-07-18 01:07:51 +0000