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2022-04-12iopoll: Extend read_poll_timeout macro to support variable parametersAriel D'Alessandro1-9/+11
This macro currently supports only one parameter. Based on Linux iopoll, let's extend read_poll_timeout common API to allow multiple variable parameters. Signed-off-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com>
2022-04-08spi: cadence_qspi: Migrate CONFIG_CQSPI_REF_CLK to KconfigTom Rini1-0/+1
This is a little tricky since SoCFPGA has code to determine this as runtime. Introduce a guard variable for platforms to select if they have a static value to use. Then for ARCH_SOCFPGA, call cm_get_qspi_controller_clk_hz() and otherwise continue the previous behavior. Cc: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-04-05Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxiTom Rini2-2/+2
A big part is the DM pinctrl driver, which allows us to get rid of quite some custom pinmux code and make the whole port much more robust. Many thanks to Samuel for that nice contribution! There are some more or less cosmetic warnings about missing clocks right now, I will send the trivial fixes for that later. Another big chunk is the mkimage upgrade, which adds RISC-V and TOC0 (secure images) support. Both features are unused at the moment, but I have an always-secure board that will use that once the DT lands in the kernel. On top of those big things we have some smaller fixes, improving the I2C DM support, fixing some H6/H616 early clock setup and improving the eMMC boot partition support. The gitlab CI completed successfully, including the build test for all 161 sunxi boards. I also boot tested on a A64, A20, H3, H6, and F1C100 board. USB, SD card, eMMC, and Ethernet all work there (where applicable).
2022-04-04spl: mmc: extend spl_mmc_boot_mode() to take mmc argumentAndre Przywara2-2/+2
Platforms can overwrite the weak definition of spl_mmc_boot_mode() to determine where to load U-Boot proper from. For most of them this is a trivial decision based on Kconfig variables, but it might be desirable the probe the actual device to answer this question. Pass the pointer to the mmc struct to that function, so implementations can make use of that. Compile-tested for all users changed. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Ley Foon Tan <ley.foon.tan@inte.com> (for SoCFPGA) Acked-by: Lokesh Vutla <lokeshvutla@ti.com> (for OMAP and K3) Reviewed-by: Simon Glass <sjg@chromium.org>
2022-04-01keymile: Move sourcing of common KconfigTom Rini1-2/+0
The way board/keymile/Kconfig is written protects the options there from being parsed on non-keymile platforms. We cannot however safely source this file from multiple locations. This does not manifest as a problem currently as there are no choice statements inside of this file (nor the sub-Kconfig files it sources). However, moving some target selection to one of these files exposes the underlying problem. Rework things so that we have this file sourced in arch/Kconfig. Cc: Holger Brunck <holger.brunck@hitachienergy.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Holger Brunck <holger.brunck@hitachienergy.com>
2022-03-02armv8: Fix and simplify branch_if_master/branch_if_slaveAndre Przywara1-1/+1
The branch_if_master macro jumps to a label if the CPU is the "master" core, which we define as having all affinity levels set to 0. To check for this condition, we need to mask off some bits from the MPIDR register, then compare the remaining register value against zero. The implementation of this was slighly broken (it preserved the upper RES0 bits), overly complicated and hard to understand, especially since it lacked comments. The same was true for the very similar branch_if_slave macro. Use a much shorter assembly sequence for those checks, use the same masking for both macros (just negate the final branch), and put some comments on them, to make it clear what the code does. This allows to drop the second temporary register for branch_if_master, so we adjust all call sites as well. Also use the opportunity to remove a misleading comment: the macro works fine on SoCs with multiple clusters. Judging by the commit message, the original problem with the Juno SoC stems from the fact that the master CPU *can* be configured to be from cluster 1, so the assumption that the master CPU has all affinity values set to 0 does not hold there. But this is already mentioned above in a comment, so remove the extra comment. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-12-17arm: socfpga: arria10: Enable double peripheral RBF configurationTien Fong Chee3-0/+52
Double peripheral RBF configuration are needed on some devices or boards to stabilize the IO configuration system. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Sin Hui Kho <sin.hui.kho@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2021-12-17arm: socfpga: arria10: Reset MPFE NoC after program periph / combined RBFTien Fong Chee5-6/+195
This patch triggers warm reset to recover the MPFE NoC from corruption due to high frequency transient clock output from HPS EMIF IOPLL at VCO startup after peripheral RBF is programmed. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Sin Hui Kho <sin.hui.kho@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2021-12-17arm: socfpga: arria10: Setting image magic value to romcode initswstate regTien Fong Chee2-2/+11
The romcode_initswstate register need to be set with FSBL_IMAGE_IS_VALID value if the current FSBL image is found valid, otherwise BootROM will look for next subsequent valid FSBL image when warm reset is triggered. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Sin Hui Kho <sin.hui.kho@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2021-09-30WS cleanup: remove SPACE(s) followed by TABWolfgang Denk1-8/+8
Signed-off-by: Wolfgang Denk <wd@denx.de>
2021-09-16Merge tag 'v2021.10-rc4' into nextTom Rini1-1/+1
Prepare v2021.10-rc4 Signed-off-by: Tom Rini <trini@konsulko.com> # gpg: Signature made Tue 14 Sep 2021 06:58:32 PM EDT # gpg: using RSA key 1A3C7F70E08FAB1707809BBF147C39FF9634B72C # gpg: Good signature from "Thomas Rini <trini@konsulko.com>" [ultimate] # Conflicts: # board/Arcturus/ucp1020/spl.c # cmd/mvebu/Kconfig # common/Kconfig.boot # common/image-fit.c # configs/UCP1020_defconfig # configs/sifive_unmatched_defconfig # drivers/pci/Kconfig # include/configs/UCP1020.h # include/configs/sifive-unmatched.h # lib/Makefile # scripts/config_whitelist.txt
2021-09-08lib: Drop SHA512_ALGO in lieu of SHA512Alexandru Gagniuc1-1/+1
SHA512_ALGO was used as a "either SHA512 or SHA384", although the implementations of these two algorithms share a majority of code. From a Kconfig interface perspective, it makes sense to present two distinct options. This requires #ifdefing out the SHA512 implementation from sha512.c. The latter doesn't make any sense. It's reasonable to say in Kconfig that SHA384 depends on SHA512, and seems to be the more polite way to handle the selection. Thus, automatically select SHA512 when SHA384 is enabled. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2021-09-04mmc: Rename MMC_SUPPORT to MMCSimon Glass3-3/+3
Rename these options so that CONFIG_IS_ENABLED can be used with them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> [trini: Fixup some incorrect renames] Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-25arm: socfpga: Enable Intel N5X device buildSiew Chin Lim2-6/+43
Add defconfig for N5X to support legacy, ATF and VAB boot flow. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-08-25arm: socfpga: Add SPL for Intel N5X deviceSiew Chin Lim1-0/+94
Add SPL for N5X. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-08-25ddr: altera: Add SDRAM driver for Intel N5X deviceTien Fong Chee2-1/+15
The DDR subsystem in Diamond Mesa is consisted of controller, PHY, memory reset manager and memory clock manager. Configuration settings of controller, PHY and memory reset manager is come from DDR handoff data in bitstream, which contain the register base addresses and user settings from tool. Configuration settings of memory clock manager is come from the HPS handoff data in bitstream, however the register base address is defined in device tree. The calibration is fully done in HPS, which requires IMEM and DMEM binaries loading to PHY SRAM for running this calibration, both IMEM and DMEM binaries are also part of bitstream, this bitstream would be loaded to OCRAM by SDM, and configured by DDR driver. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2021-08-25arm: socfpga: Changed misc_s10.c to misc_soc64.cSiew Chin Lim2-8/+8
Rename to common file name to used by all SOC64 devices. No functionality change. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-08-25arm: socfpga: Add clock manager for Intel N5X deviceSiew Chin Lim3-0/+94
Add clock manager for N5X. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-08-25arm: socfpga: Move cm_get_mpu_clk_hz function declaration to clock_manager.hSiew Chin Lim5-5/+1
Move cm_get_mpu_clk_hz function declaration from individual device's clock manager header file to common clock_manager.h. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-08-25arm: socfpga: Get clock manager base address for Intel N5X deviceSiew Chin Lim1-0/+3
Add N5X clock manager to socfpga_get_managers_addr function. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-08-24arm: socfpga: Add handoff data support for Intel N5X deviceTien Fong Chee3-48/+140
N5X support both HPS handoff data and DDR handoff data. Existing HPS handoff functions are restructured to support both existing devices and N5X device. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2021-08-24arm: socfpga: Add base address for Intel N5X deviceSiew Chin Lim1-1/+2
Reuse base_addr_soc64.h for Intel N5X device, the address is the same as Agilex. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-08-24arm: socfpga: Changed base_addr_s10.h to base_addr_soc64.hSiew Chin Lim1-4/+4
Rename to common file name to used by all SOC64 devices and change "_S10_" to "_SOC64_" in base_addr_soc64.h. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-08-24arm: socfpga: Move linux_qspi_enable from bootcommand to board_prep_linux ↵Siew Chin Lim1-8/+9
function Move 'linux_qspi_enable' from bootcommand to board_prep_linux function when OS booted from FIT image for Stratix 10 and Agilex. This flow is common for all Intel SOC64 devices. U-Boot will update 'fdt_addr' environment value based on FIT image in board_prep_linux function, and 'linux_qspi_enable' will refer to 'fdt_addr' environment value to retrieve the device tree node. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-08-02global: Convert simple_strtoul() with hex to hextoul()Simon Glass2-3/+3
It is a pain to have to specify the value 16 in each call. Add a new hextoul() function and update the code to use it. Add a proper comment to simple_strtoul() while we are here. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-06-11common: fit: Update board_fit_image_post_process() to pass fit and node_offsetLokesh Vutla1-1/+2
board_fit_image_post_process() passes only start and size of the image, but type of the image is not passed. So pass fit and node_offset, to derive information about image to be processed. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-05-24treewide: Convert macro and uses of __section(foo) to __section("foo")Marek Behún1-1/+1
This commit does the same thing as Linux commit 33def8498fdd. Use a more generic form for __section that requires quotes to avoid complications with clang and gcc differences. Remove the quote operator # from compiler_attributes.h __section macro. Convert all unquoted __section(foo) uses to quoted __section("foo"). Also convert __attribute__((section("foo"))) uses to __section("foo") even if the __attribute__ has multiple list entry forms. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-04-08arm: socfpga: smc: Add function to get usercodeSiew Chin Lim2-0/+18
Add function to send mailbox command via SMC to get usercode from SDM. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2021-04-08arm: socfpga: Changed to store QSPI reference clock in kHzSiew Chin Lim4-11/+58
Changed to store QSPI reference clock in kHz instead of Hz in boot scratch cold0 register for Stratix10 and Agilex. This patch is in preparation for Intel N5X SDRAM driver support. Reserved 4 bits for Intel N5X SDRAM driver, and there will be 28 bits to store QSPI reference clock. Due to limited bits, QSPI reference clock frequency is converted to kHz from Hz. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2021-04-08arm: socfpga: Move Stratix10 and Agilex clock manager common codeSiew Chin Lim7-19/+13
Move duplicated function cm_get_qspi_controller_clk_hz to clock_manager.c. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2021-04-08arm: socfpga: Restructure Stratix10 and Agilex handoff codeSiew Chin Lim6-82/+126
Restructure Stratix10 and Agilex handoff code to used by all SOC64 devices, in preparation to support handoff for Diamond Mesa. Remove wrap_pinmux_config_s10.c. Add wrap_handoff_soc64.c which contains the generic function to parse the handoff data. Update system_manager_soc64.c to use generic handoff function in wrap_handoff_soc64.c. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2021-04-08arm: socfpga: Rearrange sequence of macros in handoff_soc64.hSiew Chin Lim1-10/+12
Rearrange sequence of macros in handoff_soc64.h without any functionality change. In preparation for Stratix10 and Agilex handoff function restructuring. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-04-08arm: socfpga: Changed system_manager_s10.c to system_manager_soc64.cSiew Chin Lim2-2/+2
Rename to common file name to used by all SOC64 devices. No functionality change. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-04-08arm: socfpga: Changed wrap_pll_config_s10.c to wrap_pll_config_soc64.cSiew Chin Lim2-2/+2
Rename to common file name to used by all SOC64 devices. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-04-08arm: socfpga: Rename Stratix10 and Agilex handoff common macrosSiew Chin Lim5-57/+57
Rename handoff_s10.h to handoff_soc64.h. Changed macros prefix from S10_HANDOFF to SOC64_HANDOFF. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-04-08arm: socfpga: Move Stratix10 and Agilex SPL common codeSiew Chin Lim4-33/+27
Move Stratix10 and Agilex SPL common code to spl_soc64.c. We are in preparation for new n5x device support. No functional change in this patch. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2021-03-29Merge tag 'v2021.04-rc5' into nextWIP/29Mar2021-nextTom Rini1-1/+2
Prepare v2021.04-rc5
2021-03-23arm: socfpga: Only do 'is OS booted from FIT' checking when VAB is enabledSiew Chin Lim1-1/+2
Check CONFIG_SOCFPGA_SECURE_VAB_AUTH before perform 'is OS booted from FIT' checking in board_prep_linux function. And, fix typo of CONFIG_SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE. CONFIG_FIT will be enabled in both ATF and VAB boot flow, thus, board_prep_linux function will always be called by both ATF and VAB boot flow. board_pre_linux function will do 'is OS booted from FIT' checking, and it will be called before board_fit_image_post_process function. VAB boot flow expects the OS is always booted from FIT and with VAB signed cerfiticate because the VAB authentication is implemented in board_fit_image_post_process function. So, VAB needs the 'is OS booted from FIT' checking in board_pre_linux function. However, for ATF boot flow, it is not a requirement that the OS must always booted from FIT. The OS can be booted from individual Image and kernel dtb file. Thus, we should not do 'if OS is booted from FIT' checking in board_prep_linux function. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2021-03-15Merge tag 'v2021.04-rc4' into nextTom Rini9-8/+350
Prepare v2021.04-rc4
2021-03-08arm: socfpga: cmd: Support 'vab' commandSiew Chin Lim2-0/+35
Support 'vab' command to perform vendor authentication. Command format: vab addr len Authorize 'len' bytes starting at 'addr' via vendor public key Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-03-08arm: socfpga: soc64: Support Vendor Authorized Boot (VAB)Siew Chin Lim6-4/+308
Vendor Authorized Boot is a security feature for authenticating the images such as U-Boot, ARM trusted Firmware, Linux kernel, device tree blob and etc loaded from FIT. After those images are loaded from FIT, the VAB certificate and signature block appended at the end of each image are sent to Secure Device Manager (SDM) for authentication. U-Boot will validate the SHA384 of the image against the SHA384 hash stored in the VAB certificate before sending the image to SDM for authentication. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2021-03-08arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64Siew Chin Lim3-4/+7
Create common macro TARGET_SOCFPGA_SOC64 for Stratix10 and Agilex. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-03-02reset: Remove addr parameter from reset_cpu()Harald Seiler1-1/+1
Historically, the reset_cpu() function had an `addr` parameter which was meant to pass in an address of the reset vector location, where the CPU should reset to. This feature is no longer used anywhere in U-Boot as all reset_cpu() implementations now ignore the passed value. Generic code has been added which always calls reset_cpu() with `0` which means this feature can no longer be used easily anyway. Over time, many implementations seem to have "misunderstood" the existence of this parameter as a way to customize/parameterize the reset (e.g. COLD vs WARM resets). As this is not properly supported, the code will almost always not do what it is intended to (because all call-sites just call reset_cpu() with 0). To avoid confusion and to clean up the codebase from unused left-overs of the past, remove the `addr` parameter entirely. Code which intends to support different kinds of resets should be rewritten as a sysreset driver instead. This transformation was done with the following coccinelle patch: @@ expression argvalue; @@ - reset_cpu(argvalue) + reset_cpu() @@ identifier argname; type argtype; @@ - reset_cpu(argtype argname) + reset_cpu(void) { ... } Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-02-02common: Drop asm/global_data.h from common headerSimon Glass16-0/+16
Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
2021-01-15arm: socfpga: soc64: Enable FIT image generation using binmanSiew Chin Lim1-0/+2
Enable BINMAN when using Arm-Trusted-Firmware (ATF) to generate FIT images. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-01-15arm: socfpga: soc64: Skip handoff data access in SSBLChee Hong Ang1-1/+2
SPL already setup the Clock Manager with the handoff data from OCRAM. When the Clock Manager's driver get probed again in SSBL, it shall skip the handoff data access in OCRAM. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2021-01-15arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to mbox_reset_cold()Chee Hong Ang1-0/+5
mbox_reset_cold() will invoke ATF's PSCI service when running in non-secure mode (EL2). Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2021-01-15arm: socfpga: soc64: Add ATF support for Reset Manager driverChee Hong Ang1-0/+13
In non-secure mode (EL2), Reset Manager driver calls the SMC/PSCI service provided by ATF to enable/disable the SOCFPGA bridges. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-01-15arm: socfpga: Add secure register access helper functions for SoC 64bitsSiew Chin Lim3-0/+109
These secure register access functions allow U-Boot proper running at EL2 (non-secure) to access System Manager's secure registers by calling the ATF's PSCI runtime services (EL3/secure). Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2021-01-15arm: socfpga: soc64: Add SMC helper function for Intel SOCFPGA (64bits)Chee Hong Ang3-0/+71
invoke_smc() allow U-Boot proper running in non-secure mode (EL2) to invoke SMC call to ATF's PSCI runtime services such as System Manager's registers access, 2nd phase bitstream FPGA reconfiguration, Remote System Update (RSU) and etc. smc_send_mailbox() is a send mailbox command helper function which invokes the ATF's PSCI runtime service (function ID: INTEL_SIP_SMC_MBOX_SEND_CMD) to send mailbox messages to Secure Device Manager (SDM). Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
generated by cgit v1.1 at 2024-09-05 09:35:13 +0000