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path: root/arch/arm/mach-socfpga/include
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2017-05-18arm: socfpga: Add misc support for Arria 10Ley Foon Tan1-0/+6
2017-05-18arm: socfpga: Add pinmux for Arria 10Ley Foon Tan1-0/+17
2017-05-18arm: socfpga: Add sdram header file for Arria 10Ley Foon Tan1-0/+380
2017-05-18arm: socfpga: Add system manager for Arria 10Ley Foon Tan2-11/+144
2017-05-18arm: socfpga: Add clock driver for Arria 10Ley Foon Tan2-0/+227
2017-05-18arm: socfpga: Add reset driver support for Arria 10Ley Foon Tan2-0/+149
2017-05-18arm: socfpga: Add A10 macrosLey Foon Tan1-1/+7
2017-05-18arm: socfpga: Restructure misc driverLey Foon Tan1-0/+25
2017-05-18arm: socfpga: Restructure system managerLey Foon Tan2-118/+132
2017-05-18arm: socfpga: Restructure reset manager driverLey Foon Tan2-41/+57
2017-05-18arm: socfpga: Restructure clock manager driverLey Foon Tan2-307/+331
2017-04-14ARM: socfpga: boot0 hook: remove macro from boot0 header fileChee, Tien Fong1-14/+10
2017-02-08arm: socfpga: set the mpuclk divider in the Altera group registerDinh Nguyen1-0/+3
2016-12-06ARM: socfpga: Add boot0 hook to prevent SPL corruptionMarek Vasut1-0/+28
2016-10-27ddr: altera: Configuring SDRAM extra cycles timing parametersChin Liang See1-1/+7
2016-04-10arm: socfpga: Nuke useless includeMarek Vasut1-12/+0
2015-12-22arm: socfpga: Define NAND reset bitMarek Vasut1-1/+2
2015-12-20arm: socfpga: fix up a questionable macro for SDMMCDinh Nguyen1-3/+7
2015-11-30ARM: socfpga: rename the cyclone5 and arria5 base address fileDinh Nguyen1-0/+0
2015-11-30ARM: socfpga: arria10: add base address map for Arria10Dinh Nguyen1-0/+45
2015-11-30arm: socfpga: reset: FIX address of tstscratch registerPhilipp Rosenberger1-0/+1
2015-11-03arm: socfpga: reset: correct dma, qspi, and sdmmc reset bit definesDinh Nguyen1-3/+3
2015-09-04mmc: dw_mmc: Probe the MMC from OFMarek Vasut1-1/+1
2015-08-23arm: socfpga: Make the pinmux table const u8Marek Vasut1-2/+1
2015-08-08arm: socfpga: scan: Add code to get FPGA IDDinh Nguyen1-0/+1
2015-08-08arm: socfpga: scan: Clean up horrible macrosMarek Vasut1-42/+0
2015-08-08arm: socfpga: scan: Clean up scan_chain_engine_is_idle()Marek Vasut1-9/+0
2015-08-08ddr: altera: sequencer: Wrap misc remaining macrosMarek Vasut1-0/+17
2015-08-08ddr: altera: sequencer: Wrap IO_* macrosMarek Vasut1-0/+19
2015-08-08ddr: altera: sequencer: Wrap RW_MGR_* macrosMarek Vasut1-0/+64
2015-08-08ddr: altera: sequencer: Wrap ac_rom_init and inst_rom_initMarek Vasut1-0/+3
2015-08-08ddr: altera: sequencer: Clean up mach/sdram.hMarek Vasut1-3/+1
2015-08-08ddr: altera: sdram: Introduce socfpga_sdram_get_config()Marek Vasut1-0/+42
2015-08-08ddr: altera: sdram: Clean up sdram_mmr_init_full() part 8Marek Vasut1-1/+1
2015-08-08ddr: altera: Wrap SOCFPGA_SDR_ADDRESS into SDR_PHYGRP.*ADDRESSMarek Vasut1-1/+1
2015-08-08arm: socfpga: system: Clean up pinmux_config.cMarek Vasut1-3/+2
2015-08-08arm: socfpga: system: Rework sysmgr_enable_warmrstcfgio()Marek Vasut1-1/+1
2015-08-08arm: socfpga: scan: Zap iocsr_scan_chain*_table()Marek Vasut1-9/+3
2015-08-08arm: socfpga: scan: Staticize scan_mgr_io_scan_chain_prg()Marek Vasut1-11/+0
2015-08-08arm: socfpga: clock: Clean up pll_config.hMarek Vasut1-1/+7
2015-08-08arm: socfpga: clock: Get rid of cm_config_t typedefMarek Vasut1-3/+3
2015-08-08arm: socfpga: reset: Add SDMMC, QSPI and DMA definesMarek Vasut1-0/+3
2015-08-08arm: socfpga: reset: Add function to reset add peripheralsMarek Vasut1-0/+1
2015-08-08arm: socfpga: reset: Replace ad-hoc reset functionsMarek Vasut1-7/+0
2015-08-08arm: socfpga: reset: Implement unified function to toggle resetMarek Vasut1-0/+2
2015-08-08arm: socfpga: reset: Start reworking the SoCFPGA reset managerMarek Vasut1-8/+39
2015-08-08arm: socfpga: reset: Add missing reset manager regsMarek Vasut1-0/+2
2015-08-08ddr: altera: Move struct sdram_prot_rule prototypeMarek Vasut1-13/+0
2015-08-08arm: socfpga: Move sdram_config.h to board dirMarek Vasut1-100/+0
2015-08-08driver/ddr/altera: Add DDR driver for Altera's SDRAM controllerDinh Nguyen2-12/+399
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