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2021-09-08lib: Drop SHA512_ALGO in lieu of SHA512Alexandru Gagniuc1-1/+1
SHA512_ALGO was used as a "either SHA512 or SHA384", although the implementations of these two algorithms share a majority of code. From a Kconfig interface perspective, it makes sense to present two distinct options. This requires #ifdefing out the SHA512 implementation from sha512.c. The latter doesn't make any sense. It's reasonable to say in Kconfig that SHA384 depends on SHA512, and seems to be the more polite way to handle the selection. Thus, automatically select SHA512 when SHA384 is enabled. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2021-08-25arm: socfpga: Enable Intel N5X device buildSiew Chin Lim1-1/+20
Add defconfig for N5X to support legacy, ATF and VAB boot flow. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-03-08arm: socfpga: soc64: Support Vendor Authorized Boot (VAB)Siew Chin Lim1-0/+15
Vendor Authorized Boot is a security feature for authenticating the images such as U-Boot, ARM trusted Firmware, Linux kernel, device tree blob and etc loaded from FIT. After those images are loaded from FIT, the VAB certificate and signature block appended at the end of each image are sent to Secure Device Manager (SDM) for authentication. U-Boot will validate the SHA384 of the image against the SHA384 hash stored in the VAB certificate before sending the image to SDM for authentication. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2021-03-08arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64Siew Chin Lim1-0/+5
Create common macro TARGET_SOCFPGA_SOC64 for Stratix10 and Agilex. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-01-15arm: socfpga: soc64: Enable FIT image generation using binmanSiew Chin Lim1-0/+2
Enable BINMAN when using Arm-Trusted-Firmware (ATF) to generate FIT images. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-01-15arm: socfpga: Disable "spin-table" method for booting LinuxChee Hong Ang1-2/+0
Standard PSCI function "CPU_ON" provided by ATF is now used by Linux kernel to bring up the secondary CPUs to enable SMP booting in Linux on SoC 64bits platform. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2020-10-09arm: socfpga: agilex: Enable FPGA Full Reconfiguration supportChee Hong Ang1-0/+1
Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM MailboxChee Hong Ang1-1/+1
Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-04-13arm: socfpga: arria10: Enable cache driver in SPLLey Foon Tan1-0/+1
Adding "u-boot,dm-pre-reloc" and enable CONFIG_SPL_CACHE to enable cache driver in SPL. This fixed error below in SPL: cache controller driver NOT found! Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-03-03ARM: socfpga: Add initial support for the ABB SECU boardHolger Brunck1-0/+10
Add initial support for the ABB SECU board, which is an ArriaV-based SoCFPGA system with ethernet and booting from Denali NAND. Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-01-07arm: socfpga: agilex: Enable Agilex SoC buildLey Foon Tan1-0/+16
Add build support for Agilex SoC. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-11-07arm: socfpga: gen5: fix ERR_PTR_OFFSETSimon Goldschmidt1-0/+3
The default implementation of ERR_PTR/PTR_ERR maps errno values at the and of the address range (e.g. -EINVAL/-22 gets 0xFFFFFFEA). For socfpga gen5 SPL, this doesn't really work, as the heap is nearly at the end of the 32 bit address range. This patch adjusts the ERR_PTR_OFFSET to map errno values into the range of the Boot ROM, which should not be used for valid pointers. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-10-09ARM: socfpga: vining_fpga: Rename VINING|FPGAMarek Vasut1-5/+5
The company Samtec was merged into Softing, migrate the board over to the new name and update copyright headers. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Silvio Fricke <silvio.fricke@softing.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-10-08spl: Convert CONFIG_SPL_SIZE_LIMIT to hexSimon Glass1-1/+1
This is currently a decimal value which is not as convenient or meaningful. Also U-Boot tends to use hex everywhere. Convert this option to hex and add a comment for the size_check macro. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the typo in the commit title] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08spl: Allow tiny printf() to be controlled in SPL and TPLSimon Glass1-2/+2
At present there is only one control for this and it is used for both SPL and TPL. But SPL might have a lot more space than TPL so the extra cost of a full printf() might be acceptable. Split the option into two, providing separate SPL and TPL controls. The TPL setting defaults to the same as SPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-06-14arm: socfpga: provide default SPL_SIZE_LIMIT for gen5Simon Goldschmidt1-0/+8
This provides an SPL_SIZE_LIMIT that makes the build check that the SPL binary loaded from flash fits into the SRAM (64 KiB) and leaves enough room for global data, heap and stack (512 bytes assumed stack usage). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-05-14arm: socfpga: Re-add support for Aries MCV SoM and MCVEV[KP] boardWolfgang Grandegger1-0/+7
Re-add support for Aries Embedded MCV SoM, which is CycloneV based and the associated MCVEVK and MCVEVP baseboard. The board can boot from eMMC. Ethernet and USB is supported. The Aries Embedded boards have been removed with commit 03b54997d568 ("board/aries: Remove"). I will now take care of them. The device-tree files are from mainline Linux commit e93c9c99a629 ("Linux v5.1)". Signed-off-by: Wolfgang Grandegger <wg@aries-embedded.de> CC: Marek Vasut <marex@denx.de> CC: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-05-06ddr: altera: Compile ALTERA SDRAM in SPL onlyLey Foon Tan1-2/+2
Compile ALTERA_SDRAM driver in SPL only. Rename ALTERA_SDRAM to SPL_ALTERA_SDRAM. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-04-25arm: socfpga: gen5: reduce SPL pre-reloc mallocSimon Goldschmidt1-0/+3
By enabling debug prints in malloc_simple, we can see that SPL for socfpga gen5 does by far not need the 8 KiB malloc pool currently allocated for SPL in pre-reloc phase. On socfpga_socrates, 1304 bytes are currently used (and this increases by ~200 bytes only for the sdram/reset fixes in socfpga-next). To prevent wasting precious SRAM space, let's reduce the initial heap used for SPL to 2 KiB. This is still some hundred bytes more than currently used. Also, the gen5 SPL enables stack and heap in DDR memory pretty early. Only the initial uclass/dm parsing, serial console and DDR initialization is done in the initial heap, so these 2 KiB should be enough for all boards. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
2019-04-25arm: socfpga: imply/default common config optionsSimon Goldschmidt1-0/+20
This commit moves common config options used in all socfpga boards to select/imply in Kconfig. This both cleans up the defconfig files as well as makes future changes easier. Options implied/defaulted for all sub-arches: - SPL, SPL_DM, USE_TINY_PRINTF, NR_DRAM_BANKS Options implied/defaulted for implied for A10 & gen5: - FPGA_SOCFPGA, SYS_MALLOC_F_LEN, SYS_TEXT_BASE Options implied/defaulted for gen5: - SPL_STACK_R, SPL_SYS_MALLOC_SIMPLE, SPL_STACK_R_ADDR Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
2018-12-20arm: socfpga: stratix10: Enable Stratix10 FPGA ReconfigurationAng, Chee Hong1-0/+1
Select CONFIG_FPGA_STRATIX10 for CONFIG_TARGET_SOCFPGA_STRATIX10. Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
2018-08-13ARM: socfpga: clk: Obtain handoff base clock via DMMarek Vasut1-0/+2
Bind fixed clock driver to the base clock instantiated in the handoff DT and use DM clock framework to get their clock rate. This replaces the ad-hoc DT parsing present thus far. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13ARM: socfpga: Remove adhoc ethernet reset and configurationMarek Vasut1-0/+5
Remove ad-hoc ethernet syscon registers configuration and reset support. Reset is now handled by the reset framework and the syscon registers are set in the dwmac_socfpga.c driver. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13ARM: socfpga: Enable DM I2C framework on A10Marek Vasut1-0/+1
Enable the DM I2C framework on Arria10, so that the DM capable Designware I2C driver can handle the reset via DM reset framework. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13ARM: socfpga: Enable DM reset framework on A10Marek Vasut1-0/+2
Enable the DM reset framework and DM reset driver on Arria10 both in U-Boot and in SPL. This lets U-Boot parse reset control from DT. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-07-30Kconfig: Sort bool, default, select and imply optionsMichal Simek1-2/+2
Another round of sorting Kconfig entries aplhabetically. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-12arm: socfpga: stratix10: Enable Stratix10 SoC buildLey Foon Tan1-0/+13
Add build support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Conflicts: arch/arm/Kconfig arch/arm/mach-socfpga/Kconfig
2018-07-02board/aries: RemoveTom Rini1-7/+0
The various Aries Embedded boards have been orphaned for a year and no one has come forward to take care of them. Remove. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-18configs: Add DDR Kconfig support for Arria 10Tien Fong Chee1-0/+1
This patch enables DDR Kconfig support for Arria 10. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
2018-05-18ARM: socfpga: Clean up Kconfig entriesMarek Vasut1-30/+0
Shuffle the default Kconfig entries around so it is not such a mess. No functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
2018-02-26ARM: socfpga: Add new CycloneV SoC Devboards DBM-SoC1 boardMarek Vasut1-0/+7
Add support for a new boards from devboards.de , the DBM-SoC1 . This board has one ethernet port, one USB OTG port and USB UART. Signed-off-by: Marek Vasut <marex@denx.de>
2017-05-22Convert CONFIG_SPL_BOARD_INIT to KconfigLey Foon Tan1-0/+1
This converts the following to Kconfig: CONFIG_SPL_BOARD_INIT Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> [trini: Update the Kconfig logic] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-05-18arm: socfpga: Enable build for Arria 10Ley Foon Tan1-0/+10
Update Kconfig and Makefile to enable Arria 10. Clean up Makefile and sorting *.o alphanumerically. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2017-04-25arm: socfpga: add cyclone5 based de10-nano boardDalon Westergreen1-0/+7
Add support for the Terasic DE10-Nano board. The board is based on the DE0-Nano-Soc board but adds a larger FPGA and an HDMI output. Signed-off-by: Dalon Westergreen <dwesterg@gmail.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
2017-04-14arm: socfpga: Convert Altera DDR SDRAM driver to use KconfigLey Foon Tan1-0/+1
Convert Altera DDR SDRAM driver to use Kconfig method. Enable ALTERA_SDRAM by default if it is on Gen5 target. Arria 10 will have different driver. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2017-04-14ARM: socfpga: Rename MCVEVKMarek Vasut1-5/+5
The board is now manufactured by Aries Embedded GmbH , rename it. Signed-off-by: Marek Vasut <marex@denx.de>
2017-02-17SPL: add support to boot from a partition typeDalon Westergreen1-0/+6
the socfpga bootrom supports mmc booting from either a raw image starting at 0x0, or from a partition of type 0xa2. This patch adds support for locating the boot image in the first type 0xa2 partition found. Assigned a partition number of -1 will cause a search for a partition of type CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE and use it to find the u-boot image Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
2017-01-24Kconfig: Migrate BOARD_LATE_INIT to a selectTom Rini1-0/+1
This option should not really be user selectable. Note that on PowerPC we currently only need BOARD_LATE_INIT when CHAIN_OF_TRUST is enabled so be conditional on that. Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> (for UniPhier)
2016-12-06socfpga: add support for Terasic DE1-SoC boardAnatolij Gustschin1-0/+7
Add CycloneV based Terasic DE1-SoC board. The board boots from SD/MMC. Ethernet and USB host is supported. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Marek Vasut <marex@denx.de>
2016-09-16Convert CONFIG_SPL_WATCHDOG_SUPPORT to KconfigSimon Glass1-0/+3
Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-09-16Convert CONFIG_SPL_SPI_SUPPORT to KconfigSimon Glass1-0/+3
Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-09-16Convert CONFIG_SPL_SPI_FLASH_SUPPORT to KconfigSimon Glass1-0/+3
Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-09-16Convert CONFIG_SPL_SERIAL_SUPPORT to KconfigSimon Glass1-0/+3
Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-09-16Convert CONFIG_SPL_NAND_SUPPORT to KconfigSimon Glass1-0/+3
Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-09-16Convert CONFIG_SPL_MMC_SUPPORT to KconfigSimon Glass1-0/+3
Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-09-16Convert CONFIG_SPL_LIBGENERIC_SUPPORT to KconfigSimon Glass1-0/+3
Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-09-16Convert CONFIG_SPL_LIBDISK_SUPPORT to KconfigSimon Glass1-0/+3
Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-09-16Convert CONFIG_SPL_LIBCOMMON_SUPPORT to KconfigSimon Glass1-0/+3
Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-06-08ARM: socfpga: Sort Kconfig entriesMarek Vasut1-4/+4
Just sort the board entries, no functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-06-08ARM: socfpga: add support for IS1 boardPavel Machek1-0/+6
This adds support for IS1 board. Pretty usual socfpga board, 256MB of RAM, does not have MMC, two SPI chips, one ethernet port, two additional ethernet ports connected to the FPGA. Signed-off-by: Pavel Machek <pavel@denx.de>
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