aboutsummaryrefslogtreecommitdiff
path: root/arch/arm/mach-rmobile
AgeCommit message (Collapse)AuthorFilesLines
2020-11-22pinctrl: renesas: r8a77951: Add R8A774E1 PFC supportBiju Das1-0/+1
Renesas RZ/G2H (r8a774e1) is pin compatible with R-Car H3 (r8a77951), however it doesn't have several automotive specific peripherals. Add a r8a77951 specific pin groups/functions along with common pin groups/functions for supporting both r8a77951 and r8a774e1 SoC. PFC changes are synced from mainline linux-5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-11-22pinctrl: renesas: r8a77965: Add R8A774B1 PFC supportBiju Das1-0/+1
Renesas RZ/G2N (r8a774b1) is pin compatible with R-Car M3-N (r8a77965), however it doesn't have several automotive specific peripherals. Add a r8a77965 specific pin groups/functions along with common pin groups/functions for supporting both r8a77965 and r8a774b1 SoC. PFC changes are synced from mainline linux-5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-10-20clk: renesas: Import R8A774C0 clock tables from Linux 5.9Lad Prabhakar1-0/+1
Import RZ/G2E (R8A774C0) clock tables from Linux 5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-10-20clk: renesas: Add R8A774E1 clock tablesBiju Das1-0/+1
This sync's the RZ/G2H clock tables with mainline linux 5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-10-20clk: renesas: Add R8A774B1 clock tablesBiju Das1-0/+1
This sync's the RZ/G2N clock tables with mainline linux 5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-10-20arm: renesas: Add config option for R8A774C0 SoCLad Prabhakar1-0/+3
Add config support for RZ/G2E (a.k.a R8A774C0) SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-10-20arm: renesas: Add config option for R8A774E1 SoCBiju Das1-0/+3
Add config support for RZ/G2H(a.k.a R8A774E1) SoC. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-10-20arm: renesas: Add config option for R8A774B1 SoCBiju Das1-1/+4
Add config support for RZ/G2N(a.k.a R8A774B1) SoC. Also fixed the alignment issue on R8A774A1 config. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-09-26arm: mach-rmobile: Mark the default s_init function as weakBiju Das1-0/+6
Mark the default s_init function as weak, so that SoC's can override it if needed, and it will still be discarded if unused. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-09-26arm: rmobile: Identify R8A7796 r1.3 SoCBiju Das1-2/+7
Add support to identify R8A7796 r1.3 SoC. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-07-28Makefile: Rename ALL-y to INPUTS-ySimon Glass1-1/+1
When binman is in use, most of the targets built by the Makefile are inputs to binman. We then need a final rule to run binman to produce the final outputs. Rename the variable to indicate this, and add a new 'inputs' target. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-25ARM: rmobile: Add Beacon EmbeddedWorks RZG2M Dev KitAdam Ford1-0/+6
The Beacon EmbeddedWorks kit is based on the R8A774A1 SoC also known as the RZ/G2M. The kit consists of a SOM + Baseboard and supports microSD, eMMC, Ethernet, a couple celular radios, two CAN interfaces, Bluetooth and WiFi. Signed-off-by: Adam Ford <aford173@gmail.com>
2020-07-25ARM: renesas: Add basic R8A774A1 SupportAdam Ford1-0/+3
In order to build boards based on the R8A774A1, there needs to be a config option from which to enable other drivers and/or flags for this SoC. Signed-off-by: Adam Ford <aford173@gmail.com>
2020-07-17treewide: convert bd_t to struct bd_info by coccinelleMasahiro Yamada1-1/+1
The Linux coding style guide (Documentation/process/coding-style.rst) clearly says: It's a **mistake** to use typedef for structures and pointers. Besides, using typedef for structures is annoying when you try to make headers self-contained. Let's say you have the following function declaration in a header: void foo(bd_t *bd); This is not self-contained since bd_t is not defined. To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h> #include <asm/u-boot.h> void foo(bd_t *bd); Then, the include direcective pulls in more bloat needlessly. If you use 'struct bd_info' instead, it is enough to put a forward declaration as follows: struct bd_info; void foo(struct bd_info *bd); Right, typedef'ing bd_t is a mistake. I used coccinelle to generate this commit. The semantic patch that makes this change is as follows: <smpl> @@ typedef bd_t; @@ -bd_t +struct bd_info </smpl> Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
2020-05-18common: Drop linux/bitops.h from common headerSimon Glass2-0/+2
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop linux/delay.h from common headerSimon Glass1-0/+1
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop init.h from common headerSimon Glass3-0/+3
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop net.h from common headerSimon Glass2-0/+2
Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org>
2019-12-02common: Move some cache and MMU functions out of common.hSimon Glass2-0/+2
These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02common: Move get_ticks() function out of common.hSimon Glass1-0/+1
This function belongs in time.h so move it over and add a comment. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-11-16ARM: rmobile: Temporarily disable PCI dma-ranges updateMarek Vasut1-1/+0
According to discussion in the Linux PCI list [1], the dma-ranges should be continuous and describe the entire inbound window which the controller can address and not take into account the possible DRAM holes. Temporarily disable this code which updates the dma-ranges until this meaning is sorted out. [1] PCI: rcar: Do not abort on too many inbound dma-ranges Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-10-08spl: Allow tiny printf() to be controlled in SPL and TPLSimon Glass2-8/+8
At present there is only one control for this and it is used for both SPL and TPL. But SPL might have a lot more space than TPL so the extra cost of a full printf() might be acceptable. Split the option into two, providing separate SPL and TPL controls. The TPL setting defaults to the same as SPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-11env: Move env_set() to env.hSimon Glass1-0/+1
Move env_set() over to the new header file. Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-09ARM: renesas: Add R8A77980 V3H Condor board codeMarek Vasut1-0/+7
Add board code for the R8A77980 V3H Condor board. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-08-09ARM: renesas: Add R8A77980 V3H platform codeMarek Vasut3-0/+7
Add a few bits of platform code to support R8A77980 V3H SoC. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-07-23ARM: renesas: Update Gen3 PCIe dma-ranges before bootMarek Vasut1-0/+1
Update "dma-ranges" DT property of all PCIe controllers in the system with the up-to-date DRAM layout. This allows the PCIe controller take full advantage of all the available DRAM. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-07-13configs: Make USE_TINY_PRINTF depend on SPL||TPL and be defaultTom Rini1-1/+0
The USE_TINY_PRINTF symbol only changes things within SPL and TPL builds, so make it depend on that support. Next, make it default as within these cases we should rarely have need of more advanced print formats outside of the debug context. To do this, in a few cases we need to correct our Kconfig dependencies as we had cases of non-SPL targets select'ing this symbol. Finally, in the case of a few boards we really do need the full printf functionality. Signed-off-by: Tom Rini <trini@konsulko.com>
2019-05-21ARM: rmobile: Add recovery SPL for R-Car Gen3Marek Vasut2-0/+84
Build an SPL which can be started via SCIF download mode on R-Car Gen3 and allows loading and executing U-Boot uImage with the next stage code. This is also useful for starting e.g. ATF BL2, which inits the hardware and returns to the U-Boot SPL, which can then load e.g. U-Boot proper. The H3, M3-W, M3-N SoCs have plenty of SRAM for storing the U-Boot SPL while the payload, e.g. ATF BL2, executes, so there is no problem here. However, E3 and D3 have much less SRAM, hence the loader uses a trick where it copies itself beyond the area used by BL2 and executes from there. That area is 32kiB large and not enough to hold U-Boot SPL, BSS, stack and malloc area, so the later two are placed at +0x4000 offset from start of SRAM, another area not used by ATF BL2. To make things even more complicated, the SCIF loader cannot load to the upper 32kiB of the SRAM directly, hence the copying approach. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-05-18CONFIG_SPL_SYS_[DI]CACHE_OFF: addTrevor Woerner1-1/+1
While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required. Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Trevor Woerner <trevor@toganlabs.com> [trini: Make the default depend on the setting for full U-Boot, update more zynq hardware] Signed-off-by: Tom Rini <trini@konsulko.com>
2019-05-07ARM: dts: renesas: Add RZ/A1 GR-Peach boardChris Brandt1-0/+7
Add board code and DTs for Renesas RZ/A1 SoC-based GR-Peach, which is a cheap development platform with RZ/A1H SoC. The DTs are imported from Linux 5.0.11, commit d5a2675b207d . Currently supported are UART, ethernet and RPC SPI. The board can be booted from RPC SPI by writing the u-boot.bin binary to the beginning of the SPI NOR, e.g. using the "sf" command. The board can also be booted via JTAG by setting text base to 0x20020000, loading u-boot.bin there via JTAG and executing it from that address. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-05-07ARM: dts: renesas: Add RZ/A1 platform codeChris Brandt4-0/+35
Add platform code and DTs for Renesas RZ/A1 R7S72100 SoC. Distinguishing feature of this SoC is that it has up to 10 MiB of on-SoC static RAM (SRAM). The DTs are imported from Linux 5.0.11, commit d5a2675b207d . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-05-04ARM: rmobile: Always select pin control drivers on Gen3Marek Vasut1-0/+3
To assure the pins on R-Car Gen3 SoCs are configured correctly, always select pin control drivers on Gen3 SoCs. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09pinctrl: renesas: Add R8A77965 pin control tablesMarek Vasut1-1/+1
Add pin control tables for R8A77965 from Linux 5.0 . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09clk: renesas: Add R8A77965 clock tablesMarek Vasut1-1/+1
Add clock tables for R8A77965 from Linux 5.0 , except for the crit, R and Z clock, which are neither used nor supported by the U-Boot clock framework yet. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09ARM: rmobile: Add dedicated R8A77965 SoC supportMarek Vasut1-0/+7
Add dedicated entry for R8A77965 M3N SoC. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09ARM: rmobile: Enable multi-DTB fit LZO compressionMarek Vasut1-0/+17
Enable LZO compression of the multi-DTB fitImages, since the U-Boot with multiple DTs enabled is becoming quite large and the DTs can be well compressed. The LZO compression saves almost 200 kiB on the Salvator-X(S) and ULCB targets. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09ARM: renesas: Save boot parameters passed in by ATFMarek Vasut1-0/+15
The ATF can pass additional information via the first four registers, x0...x3. The R-Car Gen3 with mainline ATF, register x1 contains pointer to a device tree with platform information. Save these registers for future use. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-02-25ARM: rmobile: Imply SoC per boardMarek Vasut1-4/+10
Imply all SoCs supported by a given board. This allows building single U-Boot binary for boards which can have multiple SoCs. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-02-25ARM: rmobile: Imply pinctrl drivers per SoCMarek Vasut2-0/+10
Imply preferred pin control driver per SoC, no functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-02-25ARM: rmobile: Imply clock drivers per SoCMarek Vasut2-0/+10
Imply preferred clock driver per SoC, no functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-12-07ARM: rmobile: Fix to enable icache early in Gen3Takeshi Kihara2-3/+5
This patch fixes the problem that u-boot will not start unless icache is enabled early. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2018-12-07ARM: rcar_gen3: fix protection area access errorTakeshi Kihara1-2/+10
This patch fixes the problem that "main memory domain AXI secure access protection error" occurs. Exclude the area (0x43f00000 to 0x47DFFFFF) set by DBSC from the map area. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2018-12-07ARM: rcar_gen3: fix protection area access error at Cortex-A53Hiroyuki Yokoyama1-1/+7
This patch fixes the problem that "main memory domain AXI secure access protection error" occurs when booting Cortex-A53. Exclude the area (0x43f00000 to 0x47DFFFFF) set by DBSC from the map area. Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2018-12-04ARM: rmobile: Set environment variable containing CPU typeMarek Vasut1-9/+32
Set environment variable 'platform' containing the CPU type. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-12-04ARM: rmobile: Enable MMC extensionsMarek Vasut1-0/+5
Enable extended MMC commands and GPT partition table support. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> --- V2: Rebase on u-boot/master
2018-11-02ARM: rmobile: Generate fitting mem_map on Gen3Marek Vasut2-1/+91
Patch "ARM: rmobile: Mark 4-64GiB as DRAM on Gen3" marked the entire 64bit DRAM space as cachable. On CortexA57, this might result in odd side effects, where the CPU tries to prefetch from those areas and if there is no DRAM backing them, CPU bus hang can happen. This patch fixes it by generating the mem_map structure based on the actual memory layout obtained from the DT, thus not marking areas without any DRAM behind them as cachable. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Fixes: c1ec34763811d ("ARM: rmobile: Mark 4-64GiB as DRAM on Gen3") Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-10-18ARM: rmobile: Drop PRR syscon driverMarek Vasut1-53/+8
The PRR syscon driver is available too late for Multi DTB build of U-Boot. Replace it with simple check whether a platform is Gen3 or not and produce an address of the PRR. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2018-10-18ARM: rmobile: Enable cache command on Gen3Hiroyuki Yokoyama1-0/+1
This patch enables the cache command, mostly for convenience of testing. Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2018-10-03ARM: rmobile: Enable PHY framework on Gen3Marek Vasut1-0/+1
Enable PHY framework on Gen3, this is required for USB EHCI PHY support. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-10-03ARM: rmobile: Mark 4-64GiB as DRAM on Gen3Marek Vasut1-0/+6
Mark area 0x1_0000_0000 - 0x10_0000_0000 as DRAM on Gen3 as the chip is capable of addressing that and U-Boot can make use of it. This patch prevents exception when accessing those areas. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
generated by cgit v1.1 at 2024-08-13 22:07:48 +0000