aboutsummaryrefslogtreecommitdiff
path: root/arch/arm/mach-imx
AgeCommit message (Collapse)AuthorFilesLines
2023-05-02arm: imx8m: remove unused and obsolete board_fix_fdt() in SOC contextHugo Villeneuve1-34/+0
It doesn't seem appropriate for arch/SOC to use a board-level functionality (CONFIG_OF_BOARD_FIXUP), because this prevents boards that need to do FDT fixup from using that feature. Also, this code is completely dead and useless (from comments by Rasmus Villemoes on the mailing list): - No in-tree imx8m-based board seems to set CONFIG_OF_BOARD_FIXUP - The nodes which that function wants to disable don't even exist in the U-Boot copy of imx8mp.dtsi. This code was introduced in commit 35bb60787b88. It seems to be some random import of code from downstream NXP U-Boot, with a commit message that makes no sense in upstream context. Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com> Acked-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
2023-05-02imx: fix get_boot_device() for imx8Tim Harvey1-0/+2
commit 787f04bb6a0a ("imx: add USB2_BOOT type") broke get_boot_device() for IMX8 which affects booting from SDP due to boot_instance being non-zero. Fix this by only using boot_instance for imx8ulp and imx9. Fixes: 787f04bb6a0a ("imx: add USB2_BOOT type") Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
2023-05-02imx6: clock: print real pixel clock rateDario Binacchi1-0/+2
Add debug messages to print the real pixel clock rate, which may not be the requested one. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-05-02imx6: clock: add support to get LCD pixel clock rateDario Binacchi1-0/+58
Add the get_lcd_clk() function to get the LCD pixel clock rate. The patch has been tested on imx6ul platform. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-05-02imx6: clock: improve calculations to get the PLL video rateDario Binacchi1-1/+5
During some tests to check the pixel clock rate in the transition from U-Boot to the Linux kernel, I noticed that with the same configuration of the registers the debug messages reported different rates. The same Linux kernel calculations are now used to get the PLL video rate. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
2023-05-02imx: support i.MX8QM DMSSE20 a1 boardOliver Graute1-0/+8
Add i.MX8QM DMSSE20 a1 board support U-Boot 2023.04-00030-g7be2f547b2 (Apr 21 2023 - 11:11:43 +0200) Model: Advantech iMX8QM DMSSE20 Board: DMS-SE20A1 8GB Build: SCFW 549b1e18, SECO-FW c9de51c0, ATF 5782363 Boot: USB DRAM: 8 GiB Core: 100 devices, 19 uclasses, devicetree: separate MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... OK In: serial@5a060000 Out: serial@5a060000 Err: serial@5a060000 Net: eth0: ethernet@5b040000 Warning: ethernet@5b050000 (eth1) using random MAC address - 32:05:0c:f9:5e:10 , eth1: ethernet@5b050000 Hit any key to stop autoboot: 0 Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com>
2023-05-02imx8mn: buffer overflow in low_drive_gpu_freq()Heinrich Schuchardt1-0/+2
Avoid a buffer overflow if assigned-clock-rates has less than two elements. Fixes: 98bcdf16356c ("imx8mn: Add low drive mode support for DDR4/LPDDR4 EVK") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-05-02board: mntre: imx8mq: Add MNT Reform 2 board supportPatrick Wildt1-0/+7
The MNT Reform 2 is a modular DIY laptop. In its initial version it is based on the BoundaryDevices i.MX8MQ SoM. Some parts have been lifted from BoundaryDevices official U-Boot downstream project. Signed-off-by: Patrick Wildt <patrick@blueri.se> Tested-by: Vagrant Cascadian <vagrant@debian.org> Tested-by: Vagrant Cascadian <vagrant@debian.org> Signed-off-by: Stefano Babic <sbabic@denx.de>
2023-04-04arm64: imx: Add support for imx8mp-beacon-kitAdam Ford1-0/+11
Beacon Embedded has an i.MX8M Plus development kit which consists of a SOM + baseboard. The SOM includes Bluetooth, WiFi, QSPI, eMMC, and one Ethernet PHY. The baseboard includes audio, HDMI, USB-C Dual Role port, USB Hub with five ports, a PCIe slot, and a second Ethernet PHY. The device trees are already queued for inclusion in Linux 6.3. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2023-04-04ARM: dts: imx: Add support for Data Modul i.MX8M Plus eDM SBCMarek Vasut1-0/+8
Add support for Data Modul i.MX8M Plus eDM SBC board. This is an evaluation board for various custom display units. Currently supported are serial console, ethernet, eMMC, SD, SPI NOR, USB. Signed-off-by: Marek Vasut <marex@denx.de>
2023-04-04arm: imx: add u-boot-nand.imx to boot from NAND without SPLLuca Ceresoli1-0/+6
U-Boot can be booted from NAND without SPL by prepending the DCD header to the actual U-Boot binary. However this requires prepending 1024 bytes to u-boot.imx (DCD + u-boot.bin). There is already a similar target to build spl/u-boot-nand-spl.imx, add the same option for no-SPL boot. Tested on i.MX6ULL. The resulting layout of u-boot-nand.imx is: - Offset 0x0000 (0 KiB): padding - Offset 0x0400 (1 KiB): DCD header - Offset 0x1000 (4 KiB): u-boot.bin Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
2023-03-30arm64: imx8mm: imx8mn: imx8mp: Drop FEC GPR[1] board workaroundMarek Vasut1-47/+0
The FEC interface mode is now configured in common board_interface_eth_init() and called by FEC MAC driver when appropriate. Drop the board side duplicates if the same functionality. Signed-off-by: Marek Vasut <marex@denx.de>
2023-03-30arm64: imx8mp: Drop EQoS GPR[1] board workaroundMarek Vasut1-47/+0
The EQoS interface mode is now configured in common board_interface_eth_init() and called by EQoS MAC driver when appropriate. Drop the board side duplicates if the same functionality. Signed-off-by: Marek Vasut <marex@denx.de>
2023-03-30ARM: imx: imx8mp: fix enable_i2c_clkRasmus Villemoes1-2/+2
In order for i2c_num==4 and 5 to stay invalid for non-imx8mp SOCs, the i2c_ccgr[] array must be sized by the number of initializers present, not with a hard-coded 6 which would implicitly initialize the last two elements with zeroes. Also, the bounds check is off-by-one. Fixes: c92c3a4453b8 "ARM: imx: imx8mp: Enable support for i2c5 and i2c6 on i.MX8MP" Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2023-03-30net: fec_mxc: Add board_interface_eth_init() for i.MX8M Mini/Nano/PlusMarek Vasut1-0/+46
Implement common board_interface_eth_init() and call it from the FEC driver to configure IOMUXC GPR[1] register according to the PHY mode obtained from DT. This supports all three interface modes supported by the i.MX8M Mini/Nano/Plus FEC and supersedes the current board-side configuration of the same IOMUX GPR[1] duplicated in the board files. Signed-off-by: Marek Vasut <marex@denx.de>
2023-03-30net: dwc_eth_qos: Add board_interface_eth_init() for i.MX8M PlusMarek Vasut1-1/+58
Implement common board_interface_eth_init() and call it from the DWMAC driver to configure IOMUXC GPR[1] register according to the PHY mode obtained from DT. This supports all three interface modes supported by the i.MX8M Plus DWMAC and supersedes current board-side configuration of the same IOMUX GPR[1] duplicated in the board files. Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Marek Vasut <marex@denx.de>
2023-03-30net: dwc_eth_qos: Add DM CLK support for i.MX8M PlusMarek Vasut1-41/+0
The DWMAC clock in i.MX8M Plus were so far configured via ad-hoc architecture code. Replace that with DM clock instead. This way, the driver claims all its required clock, enables and disables them, and even gets the CSR clock rate and sets the TX clock rate, without any need of architecture specific register fiddling. Drop the architecture specific code while at it too. The adjustment here is modeled after STM32MP15xx clock handling in this driver. Signed-off-by: Marek Vasut <marex@denx.de>
2023-03-30Revert "imx: imx8x: colibri: switch to binman"Andrejs Cainikovs1-1/+0
This reverts commit bdadc140a127b14a666d2007eddc3f65c8de7d5a. We do not want this, see [1]. [1] https://lore.kernel.org/all/56cf058164f331ce99ce75b0751b825ee2e07fc0.camel@toradex.com/ Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
2023-03-30imx: spl_imx_romapi: Get and print boot stageYe Li1-1/+21
Get and print boot stage through ROM API in SPL Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-29imx: ele_ahab: Remove OEM Secure World Closed printYe Li1-3/+0
The OEM Secure World Closed is not a valid lifecycle on iMX8ULP/iMX9. So remove it from lifecycle print. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-29imx: ele_ahab: confirm lifecycle before closing the partYe Li1-0/+10
Before moving the lifecycle to OEM closed, confirm the lifecycle is OEM open, otherwise cancel to move forward the lifecycle. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-29misc: sentinel: s400_api: Use new command request definitionsYe Li2-2/+2
Remove legacy command definitions, change to use new ELE_xxx command request. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-29imx: ahab: Move imx9 and imx8ulp AHAB support togetherYe Li4-347/+4
Use common file ele_ahab.c for i.MX9 and iMX8ULP AHAB support, since both of them use same sentinel ELE APIs Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-29imx93: ahab: Get and decode AHAB eventsYe Li1-26/+260
For ahab_status command, support to get and decode AHAB events Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-29imx8ulp_evk: Change to use DDR driverYe Li1-0/+1
Remove the DDR initialization codes from board and enable the iMX8ULP DDR driver. Signed-off-by: Ye Li <ye.li@nxp.com>
2023-03-29imx: imx8ulp: Update clocks to meet max rate restrictionsYe Li2-64/+57
Update PLL3/PLL4 PFD and USDHC clocks to meet maximum frequency restrictions. Detail clock rate changes in the patch: PLL3 PFD2: 389M -> 324M PLL3 PFD3: 336M -> 389M PLL3 PFD3: DIV1 336M -> 389M (OD), 194M (ND/LD) PLL3 PFD3: DIV2 336M -> 194M (OD), 97M (ND/LD) PLL4 PFD0: 792M -> 594M PLL4 PFD2: 792M -> 316.8M NIC_AP: 96M (ND) -> 192M, 48M (LD) -> 96M NIC_LPAV: 198 (ND) -> 192M, 99M (LD) -> 96M USDHC0: PLL3 PFD3 DIV1, 389M (OD), 194M (ND/LD) USDHC1: PLL3 PFD3 DIV2, 194M (OD), 97M (ND/LD) USDHC2: PLL3 PFD3 DIV2, 194M (OD), 97M (ND/LD) Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-29imx: imx8ulp: Configure XRDC PDAC and MSC for DBD owner=S400 onlyYe Li1-0/+41
This patch is used to support DBD owner fuse changed to S400 only. The XRDC PDAC2 for LPAV pbridge5 and MSC1/2/3 for GPIO and LPAV are not configured by S400 default setting. So these PDAC and MSC are invalid, only DBD owner can access the corresponding resources. We have to configure necessary PDAC and MSC for SPL before DDR initialization. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-29imx: imx8ulp: upower: make code cleanerPeng Fan1-12/+78
To clean the upower codes by aligning codes format, check err_code and add detail bits list for the memory magic number Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-03-29imx: imx8ulp: upower: replace magic number with macroPeng Fan1-1/+21
The swton indicates the logic switch, magic number 0xfff80 is hard to understand, so use macro. Some board design may not have MIPI_CSI voltage input connected per data sheet. In that case, the upower power on API may dead loop mu to wait response, however there is no response. So remove MIPI_CSI here, let linux power domain driver to runtime enable the power domain. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-03-29imx: imx8ulp: Clear dividers in PLL3DIV_PFD registersYe Li1-0/+3
At present, in cgc1_pll3_init we don't set the pll3pfd div values, just use the default 0. But on A1 part, ROM will set PLL3 pfd1div2 to 1 and pfd2div1 to 3. This finally causes some clocks' rate decreased, for example USDHC. So clear the PLL3DIV_PFD dividers to get correct rate. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-29imx: imx8ulp: Reconfigure MRC3 for SRAM0 accessYe Li1-0/+15
Some space in SRAM0 will be protected by S400 to allow RX SecPriv mode access only for boot purpose. Since SW will reuse the SRAM0 as SCMI buffer and SPL container loading buffer, need to reconfigure MRC3. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-29imx: imx8ulp: configure XRDC for DRAM access from S400Ye Li1-0/+5
Need to add DRAM access permission for S400, as S400 needs to access it When SPL calls image authentication Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-29imx: imx8ulp: Adjust handshake to sync TRDC and XRDC completionYe Li1-16/+88
To fit the DBD_EN fused part, we re-design the TRDC and XRDC assignment. M33 will be the TRDC owner and needs to configure TRDC. A35 is the XRDC owner, ATF will configure XRDC. The handshake between U-boot and M33 image is used to sync TRDC and XRDC configuration completion. Once the handshake is done, A35 and M33 can access the allowed resources in others domain. The handshake is needed when M33 is booted or DBD_EN fused, because both cases will enable the TRDC. If handshake is timeout, the boot will hang. We use SIM GPR0 to pass the info from SPL to u-boot, because before the handshake, u-boot can't access SEC SIM and FSB. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
2023-03-29imx: imx8ulp: Remove the TRDC configure from A35Ye Li1-18/+45
As M33 is responsible for TRDC configuration, the settings for A35 nonsecure world access and DMA0 access are moved to M33 image. So remove the codes to release TRDC and configure it. Just keep the configurations for reference. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
2023-03-29imx: imx8ulp: Set XRDC MRC4/5 for access DDR from APDYe Li1-0/+10
iMX8ULP A1 S400 ROM removes the setting for MRC4/5. So we have to set them in SPL to allow access to DDR from A35 and APD PER masters Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-29imx: imx8ulp: Limit the eMMC ROM API workaround to A0.1 partYe Li1-1/+2
Since A1 ROM has fixed the ROM API eMMC issue, we should only use the workaround for A0.1 part. Add a SOC revision check. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-29imx: imx8ulp: Get chip revision from SentinelYe Li1-3/+29
In both SPL and u-boot, after probing the S400 MU, get the chip revision, lifecycle and UID from Sentinel. Update get_cpu_rev to use the chip revision not hard coded it for A0 Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-29imx: imx8ulp: Fix MU device probe failureYe Li1-4/+2
Since latest DTS has added multiple MU nodes, using compatible string to find the device node is not proper. It finds the first node with the compatible string matched even the node is disabled. Signed-off-by: Ye Li <ye.li@nxp.com>
2023-03-22spl: Add function prototype for spl_mmc_get_uboot_raw_sectorTom Rini1-0/+1
We did not add a prototype for spl_mmc_get_uboot_raw_sector to include/spl.h before, so add and document one now. Correct the incorrect prototype in board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c and ensure that we have spl.h where we define a non-weak spl_mmc_get_uboot_raw_sector as well. Signed-off-by: Tom Rini <trini@konsulko.com>
2023-03-02imx9: Remove ARCH_MISC_INITTom Rini1-5/+0
We don't need an empty function, we can just not enable the hook we don't use. Cc: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-01-31configs: imx8m: Prepare imx8m-beacon boards for HAB supportAdam Ford1-0/+6
In order to enable HAB, FSL_CAAM, ARCH_MISC_INIT and SPL_CRYPTO should be enabled in Kconfig like other i.MX8M boards. Signed-off-by: Adam Ford <aford173@gmail.com>
2023-01-31arm: imx: imx8m: Add basic PSCI provider implementationMarek Vasut3-0/+297
Implement basic PSCI provider to let OS turn CPU cores off and on, power off and restart the system and determine PSCI version. This is sufficient to remove the need for the ATF BL31 blob altogether. To make use of this functionality, active the following Kconfig options: # CONFIG_PSCI_RESET is not set CONFIG_ARMV8_MULTIENTRY=y CONFIG_ARMV8_SET_SMPEN=y CONFIG_ARMV8_SPL_EXCEPTION_VECTORS=y CONFIG_ARMV8_EA_EL3_FIRST=y CONFIG_ARMV8_PSCI=y CONFIG_ARMV8_PSCI_CPUS_PER_CLUSTER=4 CONFIG_ARMV8_SECURE_BASE=0x970000 CONFIG_ARM_SMCCC=y CONFIG_SYS_HAS_ARMV8_SECURE_BASE=y Signed-off-by: Marek Vasut <marex@denx.de>
2023-01-31arm: imx: imx8m: Program CSU and TZASC if PSCI providerMarek Vasut1-0/+25
In case U-Boot is the PSCI provider, it is necessary to correctly program CSU and TZASC registers. Those are poorly documented, so push in the correct values. Signed-off-by: Marek Vasut <marex@denx.de>
2023-01-31arm: imx: imx8m: Map RAM as NS if PSCI providerMarek Vasut1-5/+11
In case U-Boot is a PSCI provider, map RAM explicitly as NS, otherwise secondary cores crash with SError when attempting to access RAM mapped as secure in EL2. Signed-off-by: Marek Vasut <marex@denx.de>
2023-01-31arm: imx: imx8m: Enable GICv3 support if PSCI providerMarek Vasut1-0/+1
In case U-Boot is a PSCI provider, enable GICv3 support as this is necessary to bring up secondary cores. Signed-off-by: Marek Vasut <marex@denx.de>
2023-01-31arm: imx: imx8m: Only use ROM pointers if not PSCI providerMarek Vasut1-4/+5
The ROM pointers are in fact populated by the ATF BL31 blob, in case U-Boot itself if the PSCI provider, there is no ATF BL31 blob, hence ignore the ROM pointers. Signed-off-by: Marek Vasut <marex@denx.de>
2023-01-31arm: imx: Drop custom lowlevel_initMarek Vasut2-24/+0
The custom lowlevel_init implementation is no longer necessary, since it is responsible for routing and trapping SErrors in U-Boot in EL2, which is implemented in common code since commit: 6c7691edd55 ("armv8: Always unmask SErrors") Signed-off-by: Marek Vasut <marex@denx.de>
2023-01-30imx8mm-phg: Add board supportFabio Estevam1-0/+8
Add the board support for the i.MX8MM Cloos PHG board. This board uses a imx8mm-tqma8mqml SoM from TQ-Group. imx8mm-phg.dts and imx8mm-tqma8mqml.dtsi are taken directly from Linux 6.2-rc3. Signed-off-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
2023-01-30mx7: clock: Use 60MHz for the I2C clocksFabio Estevam1-1/+1
When an I2C clock is enabled inside enable_i2c_clk() the clock rate is configured as PLL_SYS_MAIN_120M_CLK / 2 = 60MHz. Currently, the I2C clock is retrieved from I2C1_CLK_ROOT, which may not be the one that was enabled. As there is no clock driver for the imx7d, it is better to return 60MHz for the I2C clock. This provides a workaround for the imx7d-pico board, where I2C4 is connected to the PMIC. With this change, it is possible to convert the imx7d-pico board to DM_I2C and DM_PMIC. Signed-off-by: Fabio Estevam <festevam@denx.de>
2023-01-30ARM: imx: bootaux: Fix LTO -Wlto-type-mismatchMarek Vasut3-2/+15
Commit 56c2dbdabab5 ("imx: bootaux: cleanup code") introduces the following LTO related warning: " arch/arm/mach-imx/imx_bootaux.c:24:31: warning: type of ‘hostmap’ does not match original declaration [-Wlto-type-mismatch] 24 | const __weak struct rproc_att hostmap[] = { }; | ^ arch/arm/mach-imx/imx8m/soc.c:1590:24: note: array types have different bounds 1590 | const struct rproc_att hostmap[] = { | ^ arch/arm/mach-imx/imx8m/soc.c:1590:24: note: ‘hostmap’ was previously declared here ../aarch64-linux-gnu/bin/ld: warning: u-boot has a LOAD segment with RWX permissions " This is because the weak empty array of structures "hostmap" is eventually replaced by non-empty array of structures with different number of elements. Fix this by avoiding weak variable size array, instead use a weak function which returns single pointer to the array. Fixes: 56c2dbdabab5 ("imx: bootaux: cleanup code") Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
generated by cgit v1.1 at 2024-08-11 12:56:35 +0000