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2022-10-19rockchip: px30: support debug uart on UART0Quentin Schulz1-0/+19
UART0 can obviously also be used for debug uart in U-Boot, so let's add its support. Cc: Quentin Schulz <foss+uboot@0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-10-09imx: gpmi: Add register needed to control nand bus timingMichael Trimarchi1-0/+9
It is used as delay for gpmi write strobe. Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-10-06arm: nuvoton: Add support for Nuvoton NPCM845 BMCJim Liu2-0/+166
Add basic support for the Nuvoton NPCM845 EVB (Arbel). Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2022-09-27Merge tag 'u-boot-stm32-20220927' of ↵Tom Rini1-3/+3
https://source.denx.de/u-boot/custodians/u-boot-stm into next - Increase SYS_MALLOC_F_LEN for STM32 MCU's board - SPL fixes for STM32F7 MCUs - Device tree alignement with kernelv6.0-rc4 for MCU's board - Device tree alignement with kernelv6.0-rc3 for MPU's board - Update DDR node for STM32MP15 - Cleanup config file for STM32MP1 - Update for cmd_stm32key command - Fix compatible string to add partitions for STM32MP1 - Update for stm32programmer tool
2022-09-26Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-riscv ↵Tom Rini1-0/+5
into next
2022-09-26configs: stm32f769-disco: Fix internal flash sizePatrice Chotard1-3/+3
arch-stm32f7/stm32.h file is shared between STM32F746 and STM32F769 MCUs. But STM32F769 embeds 2MB of internal flash instead of 1MB for STM32F746. The flash layout is quite similar between the 2 SoCs : STM32F746 STM32F769 4 * 32KB sectors 4 * 32KB sectors 1 * 128KB sector 1 * 128KB sector 3 * 256KB sectors 7 * 256KB sectors Update sect_sz_kb[] structure and SYS_MAX_FLASH_SECT accordingly. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Tested-by: Waldemar Brodkorb <wbx@openadk.org>
2022-09-20ARM: imx: Deduplicate i.MX8M SNVS LPGPR unlockMarek Vasut1-0/+5
Pull this LPGPR unlock into common code, since it is used in multiple systems already. Signed-off-by: Marek Vasut <marex@denx.de>
2022-09-19Merge branch 'master' into nextTom Rini2-2/+8
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-09-18imx: imxrt1170-evk: Add support for the NXP i.MXRT1170-EVKJesse Taube1-0/+1
This commit adds board support for i.MXRT1170-EVK from NXP. This board is an evaluation kit provided by NXP for i.MXRT117x processor family. Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
2022-09-13arm: mvebu: Fix moving internal registersPali Rohár1-2/+7
Commit 5bb2c550b11e ("arm: mvebu: Move internal registers in arch_very_early_init() function") moved code from file cpu.c to lowlevel.c, which moves Marvell internal registers from address INTREG_BASE_ADDR_REG to SOC_REGS_PHY_BASE. But the steps describing how to do it correctly were documented only in older U-Boot versions and commit cefd764222ee ("arm: mvebu: Fix internal register config on A38x") probably unintentionally removed important details about MMU from code comments around. Commit 5bb2c550b11e ("arm: mvebu: Move internal registers in arch_very_early_init() function") implemented code movement according to (now incomplete) comments which resulted in semi-broken code. The result is that I-cache is currently disabled for all Armada 38x boards and maybe there are some other (unreported / undetected) issues. Reimplement it correctly. First flush all caches, then disable MMU and L2 cache and then move Marvell internal registers. There is no need to explicitly disable I-cache. After this change lzmadec command with lzma image of 0x7000000 bytes is doing decompression just 5 seconds. Before this change it was 30 seconds. To make lowlevel.S code more readable, extend asm/pl310.h header file to be compatible with assembler and use macros from this file. Fixes: 5bb2c550b11e ("arm: mvebu: Move internal registers in arch_very_early_init() function") Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <kabel@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-09-02Makefile: Allow LTO to be disabled for a buildSimon Glass1-1/+1
LTO (Link-Time Optimisation) is an very useful feature which can significantly reduce the size of U-Boot binaries. So far it has been made available for selected ARM boards and sandbox. However, incremental builds are much slower when LTO is used. For example, an incremental build of sandbox takes 2.1 seconds on my machine, but 6.7 seconds with LTO enabled. Add a NO_LTO parameter to the build, similar to NO_SDL, so it can be disabled during development if needed, for faster builds. Add some documentation about LTO while we are here. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-02arm: ARMv4 assembly compatibilitySergei Antonov1-2/+8
There is currently a problem that U-Boot can not work on ARMv4 because assembly imlementations of memcpy() and some other functions use "bx lr" instruction that is not available on ARMv4 ("mov pc, lr" should be used instead). A working preprocessor-based solution to this problem is found in arch/arm/lib/relocate.S. Move it to the "ret" macro in arch/arm/include/asm/assembler.h and change all "bx lr" code to "ret lr" in functions that may run on ARMv4. Linux source code deals with this problem in the same manner. v1 -> v2: Comment update. Pointed out by Andre Przywara. Signed-off-by: Sergei Antonov <saproj@gmail.com> CC: Samuel Holland <samuel@sholland.org> CC: Ye Li <ye.li@nxp.com> CC: Simon Glass <sjg@chromium.org> CC: Andre Przywara <andre.przywara@arm.com> CC: Marek Vasut <marex@denx.de> CC: Sean Anderson <sean.anderson@seco.com> CC: Tom Rini <trini@konsulko.com>
2022-08-20net: lpc32xx_eth.c ethernet driverTom Rini1-3/+0
This driver has not been converted to DM_ETH. The migration deadline passed 2 years ago. Cc: Trevor Woerner <twoerner@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Ramon Fried <rfried.dev@gmail.com>
2022-08-12Convert CONFIG_SYS_FSL_QMAN_V3 et al to KconfigTom Rini1-2/+0
This converts the following to Kconfig: CONFIG_FSL_NGPIXIS CONFIG_SYS_FSL_QMAN_V3 CONFIG_SYS_FSL_RAID_ENGINE CONFIG_SYS_FSL_RMU CONFIG_SYS_FSL_SINGLE_SOURCE_CLK CONFIG_SYS_FSL_SRIO_LIODN CONFIG_SYS_FSL_TBCLK_DIV CONFIG_SYS_FSL_USB1_PHY_ENABLE CONFIG_SYS_FSL_USB2_PHY_ENABLE CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY Signed-off-by: Tom Rini <trini@konsulko.com>
2022-08-12Convert CONFIG_SYS_FSL_NUM_CC_PLLS to KconfigTom Rini1-3/+0
This converts the following to Kconfig: CONFIG_SYS_FSL_NUM_CC_PLLS Signed-off-by: Tom Rini <trini@konsulko.com>
2022-08-12Convert CONFIG_SYS_FSL_MAX_NUM_OF_SEC to KconfigTom Rini7-17/+0
This converts the following to Kconfig: CONFIG_SYS_FSL_MAX_NUM_OF_SEC Signed-off-by: Tom Rini <trini@konsulko.com>
2022-08-12Remove CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR et alTom Rini3-14/+0
This removes the following symbols: CONFIG_SYS_FSL_DSPI_BE CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET CONFIG_SYS_FSL_DSP_DDR_ADDR CONFIG_SYS_FSL_DSP_M2_RAM_ADDR CONFIG_SYS_FSL_DSP_M3_RAM_ADDR CONFIG_SYS_FSL_ERRATUM_A008751 CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT CONFIG_SYS_FSL_ESDHC_NUM CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET CONFIG_SYS_FSL_ISBC_VER CONFIG_SYS_FSL_QSPI_LE CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR CONFIG_SYS_FSL_SRDS_NUM_PLLS CONFIG_SYS_FSL_WDOG_BE CONFIG_SYS_GP1DIR CONFIG_SYS_GP1ODR CONFIG_SYS_GP2DIR CONFIG_SYS_GP2ODR CONFIG_SYS_HALT_BEFOR_RAM_JUMP CONFIG_SYS_HMI_BASE FSL_QSPI_FLASH_NUM FSL_QSPI_FLASH_SIZE Signed-off-by: Tom Rini <trini@konsulko.com>
2022-08-04Convert CONFIG_SYS_FSL_CORES_PER_CLUSTER to KconfigTom Rini1-1/+0
This converts the following to Kconfig: CONFIG_SYS_FSL_CORES_PER_CLUSTER As part of this, correct the dependencies on SYS_FSL_THREADS_PER_CORE. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-08-04Convert CONFIG_FSL_MEMAC et al to KconfigTom Rini1-10/+0
This converts the following to Kconfig: CONFIG_FSL_MEMAC CONFIG_SYS_MEMAC_LITTLE_ENDIAN Signed-off-by: Tom Rini <trini@konsulko.com>
2022-08-04Convert CONFIG_SYS_FSL_CCSR_GUR_BE et al to KconfigTom Rini2-36/+0
This converts the following to Kconfig: CONFIG_SYS_FSL_CCSR_GUR_BE CONFIG_SYS_FSL_CCSR_SCFG_BE CONFIG_SYS_FSL_ESDHC_BE CONFIG_SYS_FSL_IFC_BE CONFIG_SYS_FSL_PEX_LUT_BE CONFIG_SYS_FSL_CCSR_GUR_LE CONFIG_SYS_FSL_CCSR_SCFG_LE CONFIG_SYS_FSL_ESDHC_LE CONFIG_SYS_FSL_IFC_LE CONFIG_SYS_FSL_PEX_LUT_LE Signed-off-by: Tom Rini <trini@konsulko.com>
2022-08-04Convert CONFIG_SYS_FMAN_V3 to KconfigTom Rini1-2/+0
This converts the following to Kconfig: CONFIG_SYS_FMAN_V3 Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-26board: freescale: imx93_evk: support ethernetPeng Fan1-0/+7
Add ethernet support Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26imx: imx93_evk: Set ARM clock to 1.7GhzPeng Fan1-1/+3
Set ARM clock to OD frequency 1.7Ghz, since we have set PMIC VDD_SOC to Overdrive voltage 0.9V Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26ddr: imx: Add i.MX9 DDR controller driverYe Li2-2/+130
Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26imx: imx9: clock: Add DDR clock supportYe Li1-0/+3
Implement the DDR driver clock interfaces for set DDR rate and bypass DDR PLL Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26imx: imx9: Add M33 release prepare functionPeng Fan1-0/+2
To support on-demand booting M33 image from A core. SPL needs to follow M33 kick up sequence to release M33 firstly, then set M33 CPUWAIT signal. ATF will clear CPUWAIT to kick M33 to run. The prepare function also works around the M33 TCM ECC issue by clean the TCM. Also enable sentinel handshake and WDOG1 clock for M33 stop and reset. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26imx: imx9: Add MIX power initPeng Fan2-0/+174
Add power init of MEDIAMIX, MLMIX and DDRMIX. And clear isolation of MIPI DSI/CSI, USBPHY after the power up. SPL should call the power init in its boot sequence before accessing above three MIX and USB. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26imx: imx9: Add gpio registers structureYe Li1-0/+20
Add GPIO registers structure for iMX93, so that we can enable lpgpio driver Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26misc: fuse: support to access fuse on i.MX93Alice Guo1-0/+2
i.MX93 fuse can be accessed through FSB and s400-api. Add mapping tables for i.MX93. The offset address of FSB accessing OTP shadow registers is different between i.MX8ULP and i.MX93, so use macro to define the offset address instead of hardcode. Signed-off-by: Alice Guo <alice.guo@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26misc: S400_API: Rename imx8ulp_s400_msg to sentinel_msgYe Li1-1/+1
Use more generic name for S40x msg structure Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26imx: imx9: Get the chip revision through S400 APIPeng Fan1-0/+3
Update the get chip revision methond to use S400 API, also record other information like lifecycle and UID to global data. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26imx: imx9: Add TRDC driver for TRDC initYe Li1-0/+19
Add TRDC driver to iMX9. The TRDC init splits to two phases: 1. Early init phase will release TRDC from Sentinel and open write permission to the memory where SPL image runs. Sentinel will set the memory to RX only after ROM authentication for the OEM closed part. 2. Init phase will configure TRDC to allow non-secure master to access DDR. So the peripherals can work in u-boot. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26misc: s400_api: introduce ahab_release_m33_troutPeng Fan1-0/+1
Introduce Sentinel API ahab_release_m33_trout to make sure sentinel release M33 trout and make sure M33 could boot. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26misc: S400_API: New API for FW status and chip infoPeng Fan1-0/+13
Add new API to get sentinel FW status and SoC chip info Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26misc: S400_API: Update release RDC APIYe Li1-1/+1
To support more RDC instances on i.MX93, update API to latest definition. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26misc: s4mu: Support iMX93 with Sentinel MUPeng Fan1-0/+30
Support iMX93 communicate with Sentinel Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26misc: imx: S400_API: Move S400 MU and API to a common placeYe Li3-3/+3
Since iMX9 uses S401 which shares the API with iMX8ULP. So move S400 MU driver and API to a common place and selected by CONFIG_IMX_SENTINEL Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26imx: imx9: support romapiPeng Fan2-4/+4
i.MX9 shares same ROM API with i.MX8ULP, so make the i.MX8ULP the function prototype common and usable by i.MX9. Also include mmc env functions that use ROM API. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26imx: imx9: disable watchdogYe Li1-0/+4
Disable all 3 wdogs on AIPS2 and unmask SRC reset trigger for WDOG3-5 Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26imx: imx9: Add function to initialize timerJian Li1-0/+1
Add timer_init to update ARM arch timer with correct frequency from system counter and enable system counter. Signed-off-by: Jian Li <jian.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26imx: imx9: Add CCM and clock API supportPeng Fan3-1/+510
Add clock API to support CCM root clock and LPCG setting Set the CCM AUTHEN register to allow non-secure world to set root clock and lpcg. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26imx: add basic i.MX9 supportPeng Fan8-1/+768
Add i.MX9 Kconfig and basic files for the new SoC Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26imx: add USB2_BOOT typePeng Fan1-0/+1
Add USB2_BOOT type for i.MX8ULP and i.MX9 Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26imx: move get_boot_device to common filePeng Fan1-0/+1
i.MX8MN/P/ULP supports ROM API, they have almost same get_boot_device implementation, so move to a common file. And when support i.MX9, no need to include the other function copy. Since sys_proto.h is included in imx_romapi.c, there will be build warning for i.MX8M because wdog_regs not defined, so include imx-regs.h in i.MX8M sys_proro.h Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26imx: move get_boot_device to common headerPeng Fan6-5/+2
Most i.MX implements get_boot_device, move it to common header to simplify code Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26imx: simplify dependency with SPL_BOOTROM_SUPPORTPeng Fan1-3/+0
For SoCs support ROM API, CONFIG_SPL_BOOTROM_SUPPORT is needed, so use this macro to guard the code to avoid extend the list. And drop the guard with structure definition, there is no need. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-25configs: imx8mm: Define CONFIG_SYS_UBOOT_BASE for i.MX8mMamta Shukla1-0/+1
The macro `CONFIG_SYS_UBOOT_BASE` is used by SPL loaders `"NOR"` and `"XIP"` to determine the base address of u-boot. For `"NOR"` on i.MX8MM it is the base address of QSPI0 plus the offset of the flattened image tree blob. Although `QSPI0_AMBA_BASE` is used to define CONFIG_SYS_UBOOT_BASE in multiple board header files for i.MX8MM, it is not specified. Specify offset of flattened image tree blob (needs to be set to same value as specified in 'binman' node), base address of QSPI0 and size of FlexSPI configuration block. Signed-off-by: Mamta Shukla <mamta.shukla@leica-geosystems.com> Signed-off-by: Thomas Haemmerle <thomas.haemmerle@leica-geosystems.com> Tested-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
2022-07-25imx8: add rom api wrappersRasmus Villemoes1-0/+4
The ROM API is thoroughly undocumented, but apparently passing the xor of the real arguments as an extra argument is required [1]. Also, we need to do the "save gd/restore gd" dance. These are both error-prone, and lead to a lot of code duplication. Since both imx8m[np] and imx8ulp SOCs have this, add a separate translation unit which is included precisely when the new CONFIG_IMX8_ROMAPI symbol is set, which provide convenience wrappers that take care of computing the xor value as well as doing the gd dance, and that thus have a more intuitive API. Subsequent patches will make use of these to reduce boilerplate. [1] One wonders, for example, if the check is only applied to the lower 32 bits, or if we're implicitly relying on all 64-bit pointer values we're passing effectively have 0 in the upper 32 bits. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2022-07-25imx8: sys_proto.h: change guard logic around ROM APIRasmus Villemoes1-1/+1
This exposes the struct rom_api, the g_rom_api variable declaration and the associated #defines to slightly fewer boards: namely, those IMX8M which are not IMX8MN or IMX8MP. But the latter two are the only IMX8M* ones where the g_rom_api variable is defined (in imx8m/soc.c), so that should be fine. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2022-07-11Merge branch 'next'Tom Rini25-3599/+155
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