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2021-04-11Merge branch '2021-04-11-remove-non-migrated-boards'WIP/11Apr2021Tom Rini9-1307/+0
- Remove a large number of boards that have not migrated to DM_MMC, for which the migration deadline with 2 years ago at v2019.04.
2021-04-10arm: Remove s32v234evb boardTom Rini9-1307/+0
This board has not been converted to CONFIG_DM_MMC by the deadline. Remove it. Cc: Eddy Petrișor <eddy.petrisor@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2021-04-10Rockchip: video: edp: Change interrupt polarity configurationArnaud Patard (Rtp)1-1/+3
The linux code is setting polarity configuration to 3 but uboot code is setting it to 1. Change the configuration to match the linux configuration Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org> Tested-by: Peter Robinson <pbrobinson@gmail.com>
2021-04-10rockchip: video: edp: Add rk3399 supportArnaud Patard (Rtp)1-2/+3
According to linux commit "drm/rockchip: analogix_dp: add rk3399 eDP support" (82872e42bb1501dd9e60ca430f4bae45a469aa64), rk3288 and rk3399 eDP IPs are nearly the same, the difference is in the grf register (SOC_CON6 versus SOC_CON20). So, change the code to use the right register on each IP. The clocks don't seem to be the same, the eDP clock is not at index 1 on rk3399, so don't try changing the clock at index 1 to rate 0 on rk3399. Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org> Tested-by: Peter Robinson <pbrobinson@gmail.com>
2021-04-10rockchip: video: vop: Use endpoint compatible string to find VOP modeArnaud Patard (Rtp)1-14/+1
The current code is using an hard coded enum and the of node reg value of endpoint to find out if the endpoint is mipi/hdmi/lvds/edp/dp. The order is different between rk3288, rk3399 vop little, rk3399 vop big. A possible solution would be to make sure that the rk3288.dtsi and rk3399.dtsi files have "expected" reg value or an other solution is to find the kind of endpoint by comparing the endpoint compatible value. This patch is implementing the more flexible second solution. Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org> Tested-by: Peter Robinson <pbrobinson@gmail.com>
2021-04-08imx: imx6ull: fix pinmux sel_input value for uart5 pinsYuichiro Goto1-4/+4
sel_input value for the following uart5 pins is different between i.MX6UL and i.MX6ULL: MX6_PAD_UART5_TX_DATA__UART5_DTE_RX MX6_PAD_UART5_RX_DATA__UART5_DCE_RX MX6_PAD_ENET1_RX_EN__UART5_DCE_RTS MX6_PAD_ENET1_TX_DATA0__UART5_DTE_RTS MX6_PAD_CSI_DATA02__UART5_DCE_RTS As sel_input value for the second one is fixed by the previous commit, fix the rest. Signed-off-by: Yuichiro Goto <goto@k-tech.co.jp>
2021-04-08imx8: Add DEK blob encapsulationClement Faure1-0/+11
Add DEK encapsulation support for imx8. The DEK blob is generated by the SECO through the SCFW API. Signed-off-by: Clement Faure <clement.faure@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-04-08caam: enable support for iMX7ULPFranck LENORMAND1-0/+12
Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-04-08mx6dq: hab: Fix chip version in hab.h codeBreno Lima2-1/+2
Since commit 8891410c729b ("MLK-19848 mx6dq: Fix chip version issue for rev1.3") it's not possible to call the HAB API functions on i.MX6DQ SoC Rev 1.3: Authenticate image from DDR location 0x12000000... undefined instruction pc : [<412c00dc>] lr : [<8ff560bc>] reloc pc : [<c8b6d0dc>] lr : [<178030bc>] sp : 8ef444a8 ip : 126e8068 fp : 8ff59aa8 r10: 8ffd51e4 r9 : 8ef50eb0 r8 : 006e8000 r7 : 00000000 r6 : 126ea01f r5 : 0000002b r4 : 126e8000 r3 : 412c00dd r2 : 00000001 r1 : 00000001 r0 : 00000063 Flags: nzCv IRQs off FIQs off Mode SVC_32 Resetting CPU ... resetting ... The hab.h code is defining the HAB API base address according to the old SoC revision number, thus failing when calling the HAB API authenticate_image() function. Fix this issue by using mx6dq rev 1.3 instead of mx6dq rev 1.5. Signed-off-by: Breno Lima <breno.lima@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-04-08iMX8M: Add support to enable CONFIG_IMX_HABYe Li1-0/+1
Add some SOC level codes and build configurations to use HAB lib for CONFIG_IMX_HAB (secure boot), like adding the SEC_CONFIG fuse, enable fuse driver, CAAM clock function, and add CAAM secure RAM to MMU table. The FSL_CAAM is temporally not enabled for iMX8M when CONFIG_IMX_HAB is set, because we don't need the CAAM driver for SPL. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-04-08imx: HAB: Add support for iMX8MMYe Li1-0/+4
The imx8mm has changed the address of rvt_hab, use new address for imx8mm. The authentication procedure is same as imx8mq. In u-boot, the authentication uses SIP call to trap ATF to run HAB authenticate. Users need to add CONFIG_SECURE_BOOT=y to defconfig to enable the feature. Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-04-08mx7ulp: hab: Add hab_status command for HABv4 M4 bootBreno Lima1-0/+15
When booting in low power or dual boot modes the M4 binary is authenticated by the M4 ROM code. Add an option in hab_status command so users can retrieve M4 HAB failure and warning events. => hab_status m4 Secure boot disabled HAB Configuration: 0xf0, HAB State: 0x66 No HAB Events Found! Add command documentation in mx6_mx7_secure_boot.txt guide. As HAB M4 API cannot be called from A7 core the code is parsing the M4 HAB persistent memory region. The HAB persistent memory stores HAB events, public keys and others HAB related information. The HAB persistent memory region addresses and sizes can be found in AN12263 "HABv4 RVT Guidelines and Recommendations". Reviewed-by: Utkarsh Gupta <utkarsh.gupta@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Breno Lima <breno.lima@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-04-08imx: hab: Check if IVT header is HABv4Breno Lima1-2/+0
The HABv4 implementation in ROM checks if HAB major version in IVT header is 4.x. The current implementation in hab.c code is only validating HAB v4.0 and HAB v4.1 and may be incompatible with newer HABv4 versions. Modify verify_ivt_header() function to align with HABv4 implementation in ROM code. Signed-off-by: Breno Lima <breno.lima@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-04-08imx: HAB: Update hab codes to support ARM64 and i.MX8MPeng Fan1-0/+14
There are some changes to support ARM64 i.MX8M platform in this patches: 1. The hab_rvt base and function vectors are different as i.MX6/7 2. Need to bypass an workaround for i.MX6 to fix problem in MMU. 3. The x18 register needed save & restore before calling any HAB API. According to ARM procedure call spec, the x18 is caller saved when it is used as temporary register. So calling HAB API may scratch this register, and cause crash once accessing the gd pointer. On ARMv7, the r9 is callee saved when it is used as variable register. So no need to save & restore it. 4. Add SEC_CONFIG fuse for iMX8M When current EL is not EL3, the direct calling to HAB will fail because CAAM/SNVS can't initialize at non-secure mode. In this case, we use SIP call to run the HAB in ATF. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-04-08imx8m: add regs used by CAAMPeng Fan1-0/+10
Add regs used by CAAM Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-04-08iMX8MQ: Recognize the B2 revisionYe Li1-0/+1
i.MX8MQ B2 is using same value in OCOTP_READ_FUSE_DATA like B1, so we have to check the ROM verision to distinguish the revision. As we have checked the B1 rev for sticky bits work around in secure boot. So it won't apply on B2. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-04-08arch: mach-imx: imx8m: fix unique_id read error for imx8mpPeng Fan1-0/+11
The value of Unique ID in uboot and kernel is different for iMX8MP: serial#=02e1444a0002aaff root@imx8mpevk:/sys/devices/soc0# cat soc_uid D699300002E1444A The reason is that Fuse Addresses of Unique ID of iMX8MP are 0x420 and 0x430. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Alice Guo <alice.guo@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-04-08imx8mn: Add support for 11x11 UltraLite part numberYe Li2-5/+12
There are 3 part numbers for 11x11 i.MX8MNano with different core number configuration: UltraLite Quad/Dual/Solo Comparing with i.MX8MN Lite parts, they have MIPI DSI disabled. So checking the MIPI DSI disable fuse to recognize these parts. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-04-06arm: meson: remove static ethernet link setupNeil Armstrong4-89/+0
The static ethernet link type config code is no more needed because now handled by the meson8b glue driver, delete it. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-03-15Merge tag 'v2021.04-rc4' into nextTom Rini3-2/+3
Prepare v2021.04-rc4
2021-03-05configs: fsl: move bootrom specific defines to KconfigRajesh Bhagat1-2/+0
Moves below bootrom specific defines to Kconfig: CONFIG_SYS_FSL_BOOTROM_BASE CONFIG_SYS_FSL_BOOTROM_SIZE Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-03-02arm: remove set_dacr/get_dacr functionsPatrick Delaunay1-14/+0
Remove the unused function set_dacr/get_dacr Serie-cc: Ard Biesheuvel <ardb@kernel.org> Serie-cc: R Sricharan <r.sricharan@ti.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-03-02arm: cp15: remove weak function arm_init_domainsPatrick Delaunay1-1/+0
Remove the unused weak function arm_init_domains used to change the DACR value. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-03-02arm: cosmetic: align TTB_SECT define valuePatrick Delaunay1-1/+1
Align TTB_SECT define value with previous value. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-03-02arm: remove TTB_SECT_XN_MASK in DCACHE_WRITETHROUGHPatrick Delaunay1-1/+1
The normal memory (other that DCACHE_OFF) should be executable by default, only the device memory (DCACHE_OFF) used for peripheral access should have the bit execute never (TTB_SECT_XN_MASK). Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-03-01ARM: imx: Add missing FEC ethernet quirk for MX8MMarek Vasut1-0/+1
The MX8M also contains a gigabit MAC, so define FEC_QUIRK_ENET_MAC. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2021-03-01ARM: imx8: Add missing FEC ENET quirk for i.MX8/i.MX8XOleksandr Suvorov1-0/+2
Both NXP SoCs i.MX8 and i.MX8X have ENET gigabit MAC. Define FEC_QUIRK_ENET_MAC for the imx8 platform and remove this definition from configs of boards, based on MX8/MX8X. Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-By: Ramon Fried <rfried.dev@gmail.com> Acked-by: Oliver Graute <oliver.graute@kococonnector.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2021-02-24common: Add "ifndef __ASSEMBLY__" in asm/global_data.hWIP/2021-02-24-assorted-fixesSiew Chin Lim1-0/+4
Commit "common: Drop asm/global_data.h from common header" added asm/global_data.h into secure.h. However, secure.h will be included by psci.S. Adding asm/global_data.h has caused compilation failure in pcsi.S. Add "ifndef __ASSEMBLY__" in asm/global_data.h. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-02-21dm: i2c: use CONFIG_IS_ENABLED macro for DM_I2C/DM_I2C_GPIOIgor Opaniuk4-4/+4
Use CONFIG_IS_ENABLED() macro, which provides more convenient way to check $(SPL)DM_I2C/$(SPL)DM_I2C_GPIO configs for both SPL and U-Boot proper. CONFIG_IS_ENABLED(DM_I2C) expands to: - 1 if CONFIG_SPL_BUILD is undefined and CONFIG_DM_I2C is set to 'y', - 1 if CONFIG_SPL_BUILD is defined and CONFIG_SPL_DM_I2C is set to 'y', - 0 otherwise. All occurences were replaced automatically using these bash cmds: $ find . -type f -exec sed -i 's/ifndef CONFIG_DM_I2C/if !CONFIG_IS_ENABLED(DM_I2C)/g' {} + $ find . -type f -exec sed -i 's/ifdef CONFIG_DM_I2C/if CONFIG_IS_ENABLED(DM_I2C)/g' {} + $ find . -type f -exec sed -i 's/defined(CONFIG_DM_I2C)/CONFIG_IS_ENABLED(DM_I2C)/g' {} + $ find . -type f -exec sed -i 's/ifndef CONFIG_DM_I2C_GPIO/if !CONFIG_IS_ENABLED(DM_I2C_GPIO)/g' {} + $ find . -type f -exec sed -i 's/ifdef CONFIG_DM_I2C_GPIO/if CONFIG_IS_ENABLED(DM_I2C_GPIO)/g' {} + $ find . -type f -exec sed -i 's/defined(CONFIG_DM_I2C_GPIO)/CONFIG_IS_ENABLED(DM_I2C_GPIO)/g' {} + Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-19sunxi: support boot console on uart1 for sun8iTobias Schramm1-0/+1
The A23, A33, H3, H5, A83T, V3 and Sochip S3 sun8i SoCs can mux uart1 on GPIOs PG6 and PG7. This patch adds support for using uart1 on those pins as boot console. Signed-off-by: Tobias Schramm <t.schramm@manjaro.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-02-15Merge branch '2021-02-02-drop-asm_global_data-when-unused'Tom Rini6-0/+12
- Merge the patch to take <asm/global_data.h> out of <common.h>
2021-02-08gpio: mpc8xxx_gpio: Fix for litte endianBiwen Li2-0/+26
Update gpio driver to use same logic for big-endian and little-endian Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08pci: layerscape: Remove the shadow SVR definitionsHou Zhiqiang3-32/+56
This patch moves the SVR definitions to a new svr.h for Layerscape armv7 and armv8 platforms respectively, so that the PCIe driver can reuse them. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08armv8: lx2: SVR_SOC_VER: Mask CAN_FD and security bitWasim Khan1-2/+5
Multiple LX2(LX2160A/LX2162A SoC) personality variants exists based on CAN-FD and security bit in SVR. Currenly SVR_SOC_VER mask only security bit. Update SVR_SOC_VER to mask CAN_FD and security bit for LX2 products. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-08armv8: ls1028a: fix stream id allocationNipun Gupta1-2/+2
When A-050382 errata is enabled, ECAM and EDMA have conflicting stream id 40. This patch fixes the same. Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com> Reviewed-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-02-02common: Drop asm/global_data.h from common headerSimon Glass6-0/+12
Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
2021-01-25sunxi: Add support for H616 SoCJernej Skrabec1-0/+7
H616 is very similar to H6 so most of the infrastructure can be reused. However, two big differences are that it doesn't have functional SRAM A2 which is usually used for TF-A and it doesn't have ARISC co-processor. It also needs bigger SPL size - 48 KiB. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-01-25sunxi: Add H616 DRAM supportJernej Skrabec2-0/+161
Allwinner H616 supports many types of DRAM. Most notably it supports LPDDR4. However, all commercially available boards at this time use only DDR3, so this commit adds only DDR3 support. Controller and MBUS are very similar to H6 but PHY is completely unknown. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Acked-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-01-25sunxi: add support for R_I2C on H616Jernej Skrabec1-0/+1
This port is needed for communication with PMIC. SPL uses it to set DRAM voltage on H616 boards. Reviewed-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-01-25sunxi: add support for H616 uart0Jernej Skrabec1-0/+1
This port is used for debug terminal on all known H616 boards. Reviewed-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-01-25sunxi: introduce support for H616 clocksJernej Skrabec1-1/+17
H616 has mostly the same clocks as H6 with some small differences. Just reuse H6 clocks for H616 and handle differences with macros. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-01-25sunxi: Add support for I2C on H6 like SoCsJernej Skrabec1-0/+1
I2C support, especially R_I2C port, will be needed in future. Upcoming support for H616 will need R_I2C to adjust DRAM voltage. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-01-25sunxi: prcm: Add memory map for H6 like SoCsJernej Skrabec3-238/+303
There was no need to have prcm definitions for H6 and similar SoCs till now. However, support R_I2C will be needed soon in SPL. Move old definitions to prcm_sun6i.h and add new ones in prcm_sun50i.h. One of those files will be selected in common prcm.h based on defined macros. This commit doesn't do any functional change. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-01-25mmc: sunxi: Replace H6 ifdefs with H6 gen macroJernej Skrabec1-1/+1
It turns out that several SoCs share same mmc configuration as H6. In order to lower ifdef clutter replace H6 specific macro with common one. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-01-25sunxi: Introduce common symbol for H6 like SoCsJernej Skrabec4-4/+4
It turns out that there are at least 2 other SoCs which have basically the same memory map, similar clocks and other features as H6. It's very likely that we'll see more such SoCs in the future. In order to ease porting to new SoCs and lower ifdef clutter, introduce common symbol for them. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-01-23spi: imx: Define register bits in the driverMarek Vasut6-200/+0
The CSPI/ECSPI register bits do not differ between newer SoCs, instead of having multiple copies of the same thing for each iMX SoC, define the bits in the driver. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Stefano Babic <sbabic@denx.de>
2021-01-23imx8m: clock: add type of set_clk_eqosPeng Fan1-0/+1
Add type of set_clk_eqos to make it could be used by other files. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-01-23imx: imx8mp_evk: enable eth supportPeng Fan1-0/+2
Add board code to configure the network interface Add net defconfig Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-01-18aspeed: Add AST2600 platform supportChia-Wei, Wang2-0/+28
Add low level platform initialization for the AST2600 SoC. The 2-stage booting with U-Boot SPL are leveraged to support different booting mode. However, currently the patch supports only the booting from memory-mapped SPI flash. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2021-01-18wdt: aspeed: Add AST2600 watchdog supportChia-Wei, Wang1-0/+129
AST2600 has 8 watchdog timers including 8 sets of 32-bit decrement counters, based on 1MHz clock. A 64-bit reset mask is also supported to specify which controllers should be reset by the WDT reset. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
generated by cgit v1.1 at 2024-08-12 15:44:03 +0000