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2022-03-28video: fsl: colibri_vf: Drop FSL DCU driverSimon Glass1-1/+0
This does not use driver model and is more than two years past the migration date. Drop it. It can be added back later if needed. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-03-28video: Drop references to CONFIG_VIDEO et alSimon Glass1-5/+0
Drop the Kconfigs which are not used and all references to them. In particular, this drops CONFIG_VIDEO to avoid confusion and allow us to eventually rename CONFIG_DM_VIDEO to CONFIG_VIDEO. Also drop the prototype for video_get_info_str() which is no-longer used. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Jason Liu <jason.hui.liu@nxp.com>
2022-03-25Convert CONFIG_PHY_RESET_DELAY to KconfigTom Rini1-3/+0
This converts the following to Kconfig: CONFIG_PHY_RESET_DELAY Cc: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-14Merge tag 'v2022.04-rc4' into nextTom Rini2-0/+10
Prepare v2022.04-rc4
2022-03-03mach-sunxi: Add SPL SPI boot for SUNIVJesse Taube1-0/+1
The SUNIV SoCs come with a sun6i-style SPI controller at the base address of sun4i SPI controller. The module clock of the SPI controller is missing which leaves us running directly from the AHB clock, which is set to 200MHz. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> [Icenowy: Original implementation] Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> [Jesse: adaptation to Upstream U-Boot] Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-03-03mach-sunxi: Add boot device detection for SUNIV/F1C100sJesse Taube1-0/+9
In contrast to other Allwinner SoCs the F1C100s BROM does not store a boot source indicator in the eGON header in SRAM. This leaves the SPL guessing where we were exactly booted from, and for instance trying the SD card first, even though we booted from SPI flash. By inspecting the BROM code and by experimentation, Samuel found that the top of the BROM stack contains unique pointers for each of the boot sources, which we can use as a boot source indicator. This patch removes the existing board_boot_order bodge and replace it with a proper boot source indication function. The only caveat is that this only works in the SPL, as the SPL header gets overwritten with the exception vectors, once U-Boot proper takes over. Always return MMC0 as the boot source, when called from U-Boot proper, as a placeholder for now, until we find another way. Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> Suggested-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-03-02armv8: Fix and simplify branch_if_master/branch_if_slaveAndre Przywara1-21/+8
The branch_if_master macro jumps to a label if the CPU is the "master" core, which we define as having all affinity levels set to 0. To check for this condition, we need to mask off some bits from the MPIDR register, then compare the remaining register value against zero. The implementation of this was slighly broken (it preserved the upper RES0 bits), overly complicated and hard to understand, especially since it lacked comments. The same was true for the very similar branch_if_slave macro. Use a much shorter assembly sequence for those checks, use the same masking for both macros (just negate the final branch), and put some comments on them, to make it clear what the code does. This allows to drop the second temporary register for branch_if_master, so we adjust all call sites as well. Also use the opportunity to remove a misleading comment: the macro works fine on SoCs with multiple clusters. Judging by the commit message, the original problem with the Juno SoC stems from the fact that the master CPU *can* be configured to be from cluster 1, so the assumption that the master CPU has all affinity values set to 0 does not hold there. But this is already mentioned above in a comment, so remove the extra comment. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-03-02armv8: Simplify switch_el macroAndre Przywara1-5/+3
The switch_el macro is a neat contraption to handle cases where we need different code depending on the current exception level, but its implementation was longer than needed. Simplify it by doing just one comparison, then using the different condition codes to branch to the desired target. PState.CurrentEL just holds two bits, and since we don't care about EL0, we can use >, =, < to select EL3, EL2 and EL1, respectively. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-03-02arm: Clean up asm/io.hAndre Przywara1-96/+2
asm/io.h is the header file containing the central MMIO accessor macros. Judging by the header and the comments, it was apparently once copied from the Linux kernel, but has deviated since then *heavily*. There is absolutely no point in staying close to the original Linux code anymore, so just remove the old cruft, by: - removing pointless Linux history - removing commented code - removing outdated comments - removing unused definitions (for mem_isa) This massively improves the readability of the file. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-03-02armv8: Always unmask SErrorsAndre Przywara1-0/+1
The ARMv8 architecture describes the "SError interrupt" as the fourth kind of exception, next to synchronous exceptions, IRQs, and FIQs. Those SErrors signal exceptional conditions from which the system might not easily recover, and are normally generated by the interconnect as a response to some bus error. A typical situation is access to a non-existing memory address or device, but it might be deliberately triggered by a device as well. The SError interrupt replaces the Armv7 asynchronous abort. Trusted Firmware enters U-Boot (BL33) typically with SErrors masked, and we never enable them. However any SError condition still triggers the SError interrupt, and this condition stays pending, it just won't be handled. If now later on the Linux kernel unmasks the "A" bit in PState, it will immediately take the exception, leading to a kernel crash. This leaves many people scratching their head about the reason for this, and leads to long debug sessions, possibly looking at the wrong places (the kernel, but not U-Boot). To avoid the situation, just unmask SErrors early in the ARMv8 boot process, so that the U-Boot exception handlers reports them in a timely manner. As SErrors are typically asynchronous, the register dump does not need to point at the actual culprit, but it should happen very shortly after the condition. For those exceptions to be taken, we also need to route them to EL2, if U-Boot is running in this exception level. This removes the respective code snippet from the Freescale lowlevel routine, as this is now handled in generic ARMv8 code. Reported-by: Nishanth Menon <nm@ti.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-02-23usb: ehci-omap: Drop dead codeAdam Ford1-13/+0
omap_ehci_hcd_stop appears to be dead code, and omap_ehci_hcd_init is only called by the probe function, so it can be static to that function. Remove both from the header along with some additional checking for DM_USB. Signed-off-by: Adam Ford <aford173@gmail.com>
2022-02-21arm: omap3: Make some memory functions static and clean headersAdam Ford2-6/+0
There are a few memory functions for both the emif4 (AM3517) and sdrc (OMAP35/DM37) code that can be defined as static, because those functions are not used externally. Make them static and clean up some of the corresponding headers. Signed-off-by: Adam Ford <aford173@gmail.com>
2022-02-21arm: omap3: Cleanup sys_info to fit OMAP3 booting with LTOAdam Ford1-4/+0
With LTO enabled, some functions appear to be optimized in a way that causes hanging on some OMAP3 boards after some unrelated patches were applied. The solution appears to make several functions __used. There also appears be to be some dead code, so remove it while cleaning this up. This has been tested on a general purpose OMAP3530, DM3730, and AM3517. Signed-off-by: Adam Ford <aford173@gmail.com>
2022-02-18imx: spl: Fix typo BMODE_EMI -> BMODE_EIMHarald Seiler1-5/+5
The interface for NOR/OneNAND is called "EIM" not "EMI". Fix this. Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-10arm: apple: Add RTKit supportMark Kettenis1-0/+11
Most Apple IOPs run a firmware that is based on what Apple calls RTKit. RTKit implements a common mailbox protocol. This code provides an implementation of the AP side of this protocol, providing a function to initialize RTKit-based firmwares as well as a function to do a clean shutdown of this firmware. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested on: Macbook Air M1 Tested-by: Simon Glass <sjg@chromium.org>
2022-02-10arm: apple: Change SoC name from "m1" into "apple"Mark Kettenis1-0/+0
U-Boot is expected to support multiple generations of Apple SoCs in a single binary with a single defconfig. Therefore it makes more sense to set SYS_SOC to "apple". Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-02-09Convert CONFIG_SCSI_AHCI_PLAT et al to KconfigSimon Glass1-3/+0
This converts the following to Kconfig: CONFIG_SCSI_AHCI_PLAT CONFIG_SYS_SCSI_MAX_SCSI_ID CONFIG_SYS_SCSI_MAX_LUN CONFIG_SYS_SATA_MAX_DEVICE Drop CONFIG_SCSI for everything except the sandbox build. We only need one build for tests. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-09scsi: Drop CONFIG_SYS_SCSI_MAX_DEVICESimon Glass1-2/+0
This is defined based on two other CONFIGs for all boards except sandbox and durian. For sandbox the value does not matter. For durian the value seems excessive. Drop the option completely, to simplify configuration and reduce the number of things we need to convert to Kconfig. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-08arm: mach-omap2: load/start remoteproc IPU1/IPU2Keerthy2-0/+13
First check the presence of the ipu firmware in the boot partition. If present enable the ipu and the related clocks & then move on to load the firmware and eventually start remoteproc IPU1/IPU2. do_enable_clocks by default puts the clock domains into auto which does not work well with reset. Hence adding do_enable_ipu_clocks function. Signed-off-by: Keerthy <j-keerthy@ti.com> [Amjad: fix IPU1_LOAD_ADDR and compile warnings] Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
2022-02-05mach-imx: iomux-v3: add a define for the SION bitAngus Ainslie1-0/+1
SION (Software Input On Field) - force the select mode input path Signed-off-by: Angus Ainslie <angus@akkea.ca>
2022-02-05mx6: crm_regs: drop BM_ANADIG_ANA_MISC0_REFTOP_VBGADJDario Binacchi1-1/+0
Commit 97c16dc8bf098 ("imx: mx6ull: update the REFTOP_VBGADJ setting") made this macro unused. Then remove it. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-05imx8m: lock id_swap_bypass bit in tzc380 enableAndrey Zhizhikin1-2/+4
According to TRM for i.MX8M Nano and Plus, GPR10 register contains lock bit for TZASC_ID_SWAP_BYPASS bit. This bit is required to be set in order to avoid AXI bus errors when GPU is enabled on the platform. TZASC_ID_SWAP_BYPASS bit is alread set for all imx8m applicable derivatives, but is missing a lock settings to be applied. Set the TZASC_ID_SWAP_BYPASS_LOCK bit for those derivatives which have it implemented. Since we're here, provide also names to bits from TRM instead of using BIT() macro in the code. Fixes: deca6cfbf5d7 ("imx8mn: set BYPASS ID SWAP to avoid AXI bus errors") Fixes: a07c7181296f ("imx8mp: set BYPASS ID SWAP to avoid AXI bus errors") Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> Cc: Peng Fan <peng.fan@nxp.com>
2022-02-05imx: Enable ACTLR.SMP in SPL for i.MX6/7Sven Schwermer1-0/+5
Similar to what has been done before with c5437e5b for u-boot proper, we enable the SMP bit for SPL as well. This is necessary when SDP booting straight into Linux, i.e. falcon boot. When SDP boot mode is active, the ROM code does not set this bit which makes the caches not work once activated in Linux. On an i.MX6ULL (528MHz), this reduces a minimal kernel's boot time into an initramfs shell from ~6.1s down to ~1.2s. Signed-off-by: Sven Schwermer <sven@svenschwermer.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-05imx8ulp: clock: Handle the DDRLOCKED when setting DDR clockYe Li1-0/+1
The DDRLOCKED bit in CGC2 DDRCLK will auto lock up and down by HW according to DDR DIV updating or DDR CLK halt status change. So DDR PCC disable/enable will trigger the lock up/down flow. We need wait until unlock to ensure clock is ready. And before configuring the DDRCLK DIV, we need polling the DDRLOCKED until it is unlocked. Otherwise writing ti DIV bits will not set. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05imx8ulp: clock: Support to enable/disable the ADC1 clockAlice Guo4-0/+10
This patch implements enable_adc1_clk() to enable or disable the ADC1 clock on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Alice Guo <alice.guo@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05imx8ulp: clock: Support to reset DCNano and MIPI DSIYe Li1-0/+1
When LPAV is allocated to RTD, the LPAV won't be reset. So we have to reset DCNano and MIPI DSI in u-boot before enabling the drivers Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05imx8ulp: Workaround LPOSC_TRIM fuse load issueYe Li1-0/+1
8ULP ROM should read the LPOSC trim BIAS fuse to fill the CGC0 LPOSCCTRL[7:0], but it writes a fixed value on A0.1 revision. A0.2 will fix the issue in ROM. But A0.1 we have to workaround it in SPL by setting LPOSCCTRL BIASCURRENT again. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05imx8ulp: Fix DCNANO QoS settingYe Li1-0/+1
The setting does not have effect because we should set it after power on the PS16 for NIC AV. So move it after upower_init which has powered on all PS Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05imx8ulp_evk: Control LPI2C0 PCA6416 and TPM0 for displayYe Li1-0/+4
The board use IO9 of PCA6416 on LPI2C0 and TPM0 for MIPI DSI MUX and backlight. However the LPI2C0 and TPM0 are M33 resources, in this patch we simply access them, but this is a temporary solution. We will modify it when M33 FW changes to set MIPI DSI panel as default path and enable backlight after reset. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05imx8ulp: clock: Add MIPI DSI clock and DCNano clockYe Li1-0/+2
Add the DSI clock enable and disable with PCC reset used. Add the LCD pixel clock calculation and configuration for DCNano Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05imx8ulp: clock: Support LPAV clocks in cgc and pccYe Li2-5/+93
Add the PCC5 clocks support and more LPAV clocks and PLL4 PFD in CGC. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-04sunxi: Add F1C100s DRAM initial supportIcenowy Zheng2-0/+48
Add support for F1C100s internal dram controller. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-02-04ARM: sunxi: Add clock and uart to sunxi headersIcenowy Zheng4-1/+21
This patch aims to add header files for the suniv. The header files included add support for uart, and clocks. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-02-04sunxi: move early "SRAM setup" into separate fileAndre Przywara1-0/+1
Currently we do some magic "SRAM setup" MMIO writes in s_init(), copied from the original BSP U-Boot. The comment speaks of this being required before DRAM access gets enabled, but there is no indication that this would actually be required that early. Move this out of s_init(), into board_init_f(). Since this actually only affects a very few older SoCs, the actual code goes into the cpu/armv7 directory, to move it out of the way for all other SoCs. This also uses the opportunity to convert some #ifdefs over to the fancy IS_ENABLED() macros used in actual C code. We keep the s_init() stub around for now, since armv8's lowlevel_init still relies on it. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2022-01-30sunxi: gpio: Add per-bank drive and pull settersSamuel Holland1-0/+2
The GPIO and pinctrl drivers need these setters for pin configuration. Since they are DM drivers, they should not be using hardcoded base addresses. Factor out variants of the setter functions which take a pointer to the GPIO bank's MMIO registers. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-01-30sunxi: gpio: Return void from setter functionsSamuel Holland1-2/+2
The return values of these functions are always zero, and they are never checked. Since they are not needed, remove them. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-01-19doc: replace @return by Return:Heinrich Schuchardt14-44/+44
Sphinx expects Return: and not @return to indicate a return value. find . -name '*.c' -exec \ sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \; find . -name '*.h' -exec \ sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \; Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-01-18common: board_r: move init_addr_map() to init.hOvidiu Panait1-8/+0
asm/mmu.h include is currently guarded by CONFIG_ADDR_MAP ifdef because the header is only present on arm and powerpc. In order to remove the dependency on this header and the associated ifdef, move init_addr_map() declaration to init.h, since it is only called during the common init sequence. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
2022-01-18common: board_r: drop initr_addr_map wrapperOvidiu Panait1-1/+1
Add a return value to init_addr_map and use it directly in the post-relocation init sequence, rather than using a wrapper stub. Reviewed-by: Matthias Brugger <mbrugger@suse.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
2021-12-27Convert CONFIG_SYS_IMMR to KconfigTom Rini3-3/+0
This converts the following to Kconfig: CONFIG_SYS_IMMR We do this by consolidating the SYS_IMMR options we have and providing defaults. We also, in the few places where M68K was also sharing code with these platforms, define it within the file to CONFIG_SYS_MBAR to match usage. This should be cleaned up longer term. Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27Convert CONFIG_CONS_INDEX et al to KconfigTom Rini1-1/+0
This converts the following to Kconfig: CONFIG_CONS_INDEX CONFIG_DEBUG_UART_CLOCK CONFIG_FSL_TZPC_BP147 CONFIG_GENERIC_ATMEL_MCI CONFIG_IDENT_STRING CONFIG_LIBATA CONFIG_LNX_KRNL_IMG_TEXT_OFFSET_BASE CONFIG_LPC32XX_GPIO CONFIG_MP CONFIG_MPC8XXX_GPIO CONFIG_MTD_PARTITIONS CONFIG_MVGBE CONFIG_MXC_GPIO CONFIG_NR_DRAM_BANKS CONFIG_OF_BOARD_SETUP CONFIG_OF_STDOUT_VIA_ALIAS CONFIG_OF_SYSTEM_SETUP CONFIG_PREBOOT CONFIG_ROCKCHIP_SERIAL CONFIG_RTC_ENABLE_32KHZ_OUTPUT CONFIG_RTC_MV CONFIG_SCSI_AHCI CONFIG_SF_DEFAULT_BUS CONFIG_SF_DEFAULT_CS CONFIG_SF_DEFAULT_SPEED CONFIG_SOFT_SPI CONFIG_SPI_FLASH_EON CONFIG_SPI_FLASH_MACRONIX CONFIG_SPI_FLASH_MTD CONFIG_SPI_FLASH_SPANSION CONFIG_SPI_FLASH_SST CONFIG_SPI_FLASH_STMICRO CONFIG_SUPPORT_RAW_INITRD CONFIG_SYS_ARCH_TIMER CONFIG_SYS_BOARD CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE CONFIG_SYS_DCACHE_OFF CONFIG_SYS_FDT_SAVE_ADDRESS CONFIG_SYS_FLASH_CFI CONFIG_SYS_FSL_ERRATUM_ESDHC135 CONFIG_SYS_HAS_SERDES CONFIG_SYS_L2CACHE_OFF CONFIG_SYS_LITTLE_ENDIAN CONFIG_SYS_LOAD_ADDR CONFIG_SYS_MMCSD_FS_BOOT_PARTITION CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR CONFIG_SYS_NS16550 CONFIG_SYS_PLLFIN CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_TIMER_SYS_TICK_CH CONFIG_USB_EHCI_FSL CONFIG_U_QE CONFIG_VERSION_VARIABLE Signed-off-by: Tom Rini <trini@konsulko.com>
2021-11-17clk: ast2600: Add RSACLK control for ACRYChia-Wei Wang1-0/+1
Add RSACLK enable for ACRY, the HW RSA/ECC crypto engine of ASPEED AST2600 SoCs. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
2021-11-17clk: ast2600: Add YCLK control for HACEJoel Stanley1-2/+3
Add YCLK enable for HACE, the HW hash engine of ASPEED AST2600 SoCs. Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
2021-11-17aspeed: ast2600: Enlarge SRAM sizeChia-Wei Wang1-1/+1
The AST2600 SRAM has been extended to 88KB since A1 chip revision. This patch updates the SRAM size to offer more space for early stack/heap use. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Joel Stanley <joel@jms.id.au>
2021-11-12Remove CONFIG_SERIAL_MULTITom Rini1-1/+0
This symbol has been functionally dead for a long time. Remove the last and recent re-introductions of setting it, and update the whitelist so it will not be re-introduced again. Signed-off-by: Tom Rini <trini@konsulko.com>
2021-11-10Merge tag 'u-boot-stm32-20211110' of ↵WIP/10Nov2021Tom Rini4-125/+0
https://source.denx.de/u-boot/custodians/u-boot-stm - DHSOM update: - Remove nWP GPIO hog - Increase SF bus frequency to 50Mhz and enable SFDP - Disable video output for DHSOM - Disable EFI - Enable DFU_MTD support - Create include file for STM32 gpio driver private data - Split board and SOC STM32MP15 configuration - Device tree alignement with v5.15-rc6 for STM32MP15 - Add binman support for STM32MP15x - Normalise newlines for stm32prog - Update OTP shadow registers in SPL
2021-11-10gpio: stm32: create include file for driver private dataPatrick Delaunay4-125/+0
The stm32 gpio driver private data are not needed in arch include files, they are not used by code except for stm32 gpio and pincontrol drivers, using the same IP; the defines for this IP is moved in a new file "stm32_gpio_priv.h" in driver/gpio. This patch avoids to have duplicated file gpio.h for each SOC in MPU directory mach-stm32mp and in each MCU directory arch-stm32* and allows to remove CONFIG_GPIO_EXTRA_HEADER for all STM32. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-11-05Convert CONFIG_SYS_HZ to KconfigTom Rini1-1/+0
This converts the following to Kconfig: CONFIG_SYS_HZ Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-31serial: s5p: Add Apple M1 supportMark Kettenis1-0/+41
Apple M1 SoCs include an S5L UART which is a variant of the S5P UART. Add support for this variant and enable it by default on Apple SoCs. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-31Revert "arch: arm: use dt and UCLASS_SYSCON to get gic lpi details"Michael Walle1-2/+2
Stop using the device tree as a source for ad-hoc information. This reverts commit 2ae7adc659f7fca9ea65df4318e5bca2b8274310. Signed-off-by: Michael Walle <michael@walle.cc> [trini: Also make board/broadcom/bcmns3/ns3.c fail clearly now] Signed-off-by: Tom Rini <trini@konsulko.com>
generated by cgit v1.1 at 2024-08-10 14:14:18 +0000