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path: root/arch/arm/include/asm/system.h
AgeCommit message (Expand)AuthorFilesLines
2017-03-14armv8: mmu: Add a function to change mapping attributesYork Sun1-0/+1
2017-01-18armv8: aarch64: Fix the warning about x1-x3 nonzero issueAlison Wang1-3/+5
2016-12-15ARMv8: Setup PSCI memory and device treemacro.wave.z@gmail.com1-0/+11
2016-11-22armv8: fsl-layerscape: Support loading 32-bit OS with PSCI enabledAlison Wang1-0/+2
2016-11-22armv8: Support loading 32-bit OS in AArch32 execution stateAlison Wang1-2/+117
2016-11-13arm: Set TTB XN bit in case DCACHE_OFF for LPAE modeKeerthy1-1/+1
2016-11-07armv8: add hooks for all cache-wide operationsStephen Warren1-1/+3
2016-10-18arm: Add PSCI shutdown functionAlexander Graf1-0/+1
2016-10-18arm: Disable HVC PSCI calls by defaultAlexander Graf1-10/+1
2016-10-06ARM: Introduce function to switch to hypervisor modeKeerthy1-0/+4
2016-08-05ARM: Rework and correct barrier definitionsTom Rini1-7/+1
2016-05-27arm: implement generic PSCI reset call for armv8Beniamino Galvani1-0/+2
2016-03-27arm: Add support for HYP mode and LPAE page tablesAlexander Graf1-6/+93
2016-03-27arm64: Add 32bit arm compatible dcache definitionsAlexander Graf1-1/+5
2016-03-15arm64: Remove non-full-va map codeAlexander Graf1-8/+4
2016-03-15arm64: Make full va map code more dynamicAlexander Graf1-6/+8
2016-01-31arm: Remove S bit from MMU section entryMarek Vasut1-2/+1
2016-01-31arm: Replace test for CONFIG_ARMV7 with CONFIG_CPU_V7Marek Vasut1-2/+2
2016-01-19armv8: Add Secure Monitor/Hypervisor Call (SMC/HVC) infrastructureSergey Temerkhanov1-0/+21
2016-01-19armv8: New MMU setup code allowing to use 48+ bits PA/VASergey Temerkhanov1-0/+7
2016-01-19armv8: Add read_mpidr() functionSergey Temerkhanov1-0/+11
2015-11-10armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORYStephen Warren1-5/+6
2015-10-16arm: mmu: Add missing volatile for reading SCTLR registerAlison Wang1-1/+1
2015-07-31armv8: caches: Added routine to set non cacheable regionSiva Durga Prasad Paladugu1-10/+19
2015-05-14arm: Add a prototype for save_boot_params_ret()Simon Glass1-0/+16
2015-05-13tegra124: Reserve secure RAM using MC_SECURITY_CFG{0, 1}_0Ian Campbell1-0/+1
2015-04-16ARMv7 TLB: Fixed TTBR0 and Table Descriptors to allow cachingBryan Brinsko1-0/+37
2015-02-24armv8/fsl-lsch3: Convert flushing L3 to assembly to avoid using stackYork Sun1-0/+1
2015-02-16arm: Allow lr to be saved by board codeSimon Glass1-0/+15
2014-12-18ARM: Implement non-cached memory supportThierry Reding1-0/+5
2014-11-12ARM: cache-cp15: Use more accurate typesThierry Reding1-1/+1
2014-10-06arm: cache: Add support for write-allocate D-CacheMarek Vasut1-0/+1
2014-07-03ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoCYork Sun1-0/+2
2014-04-07armv8/cache: Change cache invalidate and flush functionYork Sun1-0/+1
2014-01-09arm64: core supportDavid Feng1-0/+84
2013-03-28ARM: mmu: Set domain permissions to client accessR Sricharan1-0/+14
2013-02-03ARM: add wfi assembly macroRob Herring1-0/+6
2012-11-19arm: Add control over cachability of memory regionsSimon Glass1-0/+31
2010-04-13Move architecture-specific includes to arch/$ARCH/include/asmPeter Tyser1-0/+84
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