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path: root/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
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2022-11-10global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespaceTom Rini1-13/+13
Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-18arm: layerscape: Disable unused parts of ICID tablesSean Anderson1-2/+14
Several parts of the ICID table are only necessary for U-Boot proper. Disable them in SPL. This saves around 500 bytes. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-11-08fsl-layerscape: fix compile error with sec fw disabledLaurentiu Tudor1-1/+1
If SEC FW support is not enabled (ARMV8_SEC_FIRMWARE_SUPPORT=n), below compilation error appears arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h:169:4: error: 'CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT' undeclared here (not in a function) Fix it by wrapping with CONFIG_IS_ENABLED(). Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia Geanta <horia.geanta@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-08-22armv8: ls1028a: add icid setup for platform devicesLaurentiu Tudor1-11/+27
Add ICID setup for the platform devices contained on this chip: usb, sata, sdhc, edma, qdma, gpu, display and sec. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22armv8: ls1088a: add icid setup for platform devicesLaurentiu Tudor1-10/+44
Add ICID setup for the platform devices contained on this chip: usb, sata, sdhc, sec. The ICID macros for SEC needed to be adapted because the format of the registers is different. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-08-22armv8: fsl-layerscape: make icid setup endianness awareLaurentiu Tudor1-10/+24
The current implementation assumes that the registers holding the ICIDs are universally big endian. That's no longer the case on newer platforms so update the code to take into account the endianness of each register. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-03-03armv8: fsl-layerscape: avoid DT fixup warningLaurentiu Tudor1-1/+8
sec_firmware reserves JR3 for it's own usage and deletes the JR3 node from the device tree. This causes this warning to be issued when doing the device tree fixup: WARNING could not find node fsl,sec-v4.0-job-ring: FDT_ERR_NOTFOUND. Fix it by excluding the device tree fixup for the JR reserved by sec_firmware. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia Geanta <horia.geanta@nxp.com> Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-03-03armv8: fsl-layerscape: fix SEC QI ICID setupLaurentiu Tudor1-2/+1
The SEC QI ICID setup in the QIIC_LS register is actually an offset that is being added to the ICID coming from the qman portal. Setting it with a non-zero value breaks SMMU setup as the resulting ICID is not known. On top of that, the SEC QI ICID must match the qman portal ICIDs in order to share the isolation context. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia Geanta <horia.geanta@nxp.com> Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-01-17armv8: fsl-layerscape: properly configure qdma ICIDLaurentiu Tudor1-1/+5
The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27armv8: ls1043a: add icid setup supportLaurentiu Tudor1-0/+4
Reuse the existing ICID setup code done for LS1046A smmu enablement and add the equivalent setup for LS1043A chips. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-08-10armv8: ls1046a: setup SEC ICIDs and fix up device treeLaurentiu Tudor1-0/+25
Add support for SEC ICID configuration and apply it for ls1046a. Also add code to make the necessary device tree fixups. Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-08-10armv8: ls1046a: setup fman ports ICIDs and device treeLaurentiu Tudor1-0/+10
Add support for ICID setting of fman ports and the required device tree fixups. Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-08-10armv8: ls1046a: initial icid setup supportLaurentiu Tudor1-0/+80
Add infrastructure for ICID setup and device tree fixup on ARM platforms. This include basic ICID setup for several devices. Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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