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path: root/arch/arm/dts/zynqmp-clk-ccf.dtsi
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2022-09-13arm64: zynqmp: add ref_clk property for REFCLKPER calculationPiyush Mehta1-0/+8
Added ref_clk 'ref' property for GUCTL_REFCLKPER and GFLADJ_REFCLK_FLADJ calculation. This property configure correct value for SOF/ITP counter and period of ref_clk. This patch adds 'ref' property for both dwc3_0 and dwc3_1 cores. Signed-off-by: Piyush Mehta <piyush.mehta@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/417545b948ea12a9301a5e80851f98523be2b443.1661259809.git.michal.simek@amd.com
2022-03-07arm64: zynqmp: Use assigned-clock-rates for setting up clock in SOMMichal Simek1-0/+4
With limited low level configuration done via psu-init only IPs connected on SOM are initialized and configured. All IPs connected to carrier card are not initialized. There is a need to do proper reset, pin configuration and also clock setting. The patch targets the last part which is setting up proper clock for USBs and SDs. Also setup proper bus width for SD cards. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> Link: https://lore.kernel.org/r/d9f80b2551bd246c3d7ecb09b516806c8dc83ed9.1645629459.git.michal.simek@xilinx.com
2022-03-07arm64: zynqmp: Setup clock for DP and DPDMAMichal Simek1-0/+4
Clocks are coming from shared HW design where these frequencies should be aligned with PLL setup. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/04454c50d0d13e450976942085d763ab5aa38f98.1645629459.git.michal.simek@xilinx.com
2022-01-05arm64: zynqmp: Remove clock-names from GEM in zynqmp-clk-ccf.dtsiMichal Simek1-4/+0
Remove clock-names from GEM nodes from clk-ccf because they should be only present in zynqmp.dtsi. And as is visible both clock-names defined didn't really match. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/d6045d81b3e7e97df0ba3eeacb9f3f75ed7cff18.1637239345.git.michal.simek@xilinx.com
2021-06-23arm64: zynqmp: Remove unused dp_aclk clockMichal Simek1-8/+1
dp_aclk is not used anywhere that's why remove it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-03-30xilinx: Sync DTs with Linux kernelMichal Simek1-9/+7
There are several changes which happen in mainline kernel which should get also to U-Boot. Here is the list of patches from the kernel: - ARM: zynq: Fix leds subnode name for zc702/zybo-z7 - arm64: dts: zynqmp: Fix leds subnode name for zcu100/ultra96 v1 - arm64: dts: zynqmp: Fix u48 si5382 chip on zcu111 - arm64: dts: zynqmp: Wire up the DisplayPort subsystem - arm64: dts: zynqmp: Add DisplayPort subsystem - arm64: dts: zynqmp: Add DPDMA node - arm64: dts: zynqmp: Enable phy driver for Sata on zcu102/zcu104/zcu106 - arm64: dts: zynqmp: Enable si5341 driver for zcu102/106/111 - arm64: dts: zynqmp: Add DT description for si5328 for zcu102/zcu106 - arm64: dts: zynqmp-zcu100-revC: correct interrupt flags - arm64: dts: xilinx: align GPIO hog names with dtschema - arm64: zynqmp: Add Xilinx AES node - dt: bindings: dma: xilinx: dpdma: DT bindings for Xilinx DPDMA but also some other changes have been done. - Using only one compatible string for adxl345 on zturn - Remove Xilinx internal DP bindings - Remove USB3.0 serdes configurations - Remove SATA serdes configuration for zc1232 - Resort nvmem_firmware - Update nand compatible string - Aling power-domains property for sd0/1 Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-06arm64: zynqmp: Sync DP subsystemMichal Simek1-1/+5
Sync DP subsystem with the latest state in Xilinx U-Boot repository. This binding hasn't been approved in mainline Linux but it is much better than ancient version which this patch removes. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-06arm64: zynqmp: Sync zynqmp fpga manager with mainlineNava kishore Manne1-0/+4
Sync zynqmp fpga manager with mainline. Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-06arm64: zynqmp: Update Copyright years to 2020Michal Simek1-1/+1
Trivial change. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-01-14arm64: zynqmp: Sync gem clock nodes with mainline LinuxMichal Simek1-9/+13
Just fixing indentation and update year in Copyright. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-24arm64: zynqmp: List lpd watchdog in dtsiMichal Simek1-0/+4
There are use cases where lpd watchdog can be configured for APU use. By design this IP should be listed in zynqmp.dtsi to make sure that node is properly enabled by DTG. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-24arm64: zynqmp: Switch to xlnx-zynqmp-clk headerMichal Simek1-92/+72
Use prepared header instead of hardcoded values. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-31arm64: zynqmp: Add TTC clocksRajan Vaja1-0/+16
PS clock(LPD_APB_CLK) is default clock for TTC. Add this clock entry in TTC nodes. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-04-09arm64: zynqmp: Sync up license with mainline kernelMichal Simek1-2/+1
Mainline Linux kernel has adopted SPDX header license in a different format then was used before. This patch is syncing it up. Also update years in License text and remove Nathalie's email because it is no longer valid. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23arm64: zynqmp: Convert board to use zynqmp-clk driverMichal Simek1-0/+290
Use zynqmp clock driver instead of fixed clocks. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
generated by cgit v1.1 at 2024-09-16 07:06:38 +0000