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path: root/arch/arm/cpu/armv7/nonsec_virt.S
AgeCommit message (Expand)AuthorFilesLines
2023-10-11ARM: psci: move GIC address override to KconfigAndre Przywara1-2/+2
2022-12-23global: Migrate CONFIG_SMP_PEN_ADDR to CFGTom Rini1-2/+2
2022-12-23global: Migrate CONFIG_ARM_GIC_BASE_ADDRESS to CFGTom Rini1-2/+2
2022-12-06arm: Use the WEAK assembly entry point consistentlyTom Rini1-2/+1
2022-04-21arm: set cntfrq_el0 if CONFIG_COUNTER_FREQUENCY is validWIP/2022-04-21-further-cleanupsPeng Fan1-2/+2
2018-07-25ARM: HYP/non-sec: migrate stackMark Kettenis1-0/+2
2018-05-07SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini1-2/+1
2017-04-05ARM: rename CONFIG_TIMER_CLK_FREQ to COUNTER_FREQUENCYAndre Przywara1-2/+2
2016-07-15ARM: PSCI: Split out common stack setup code from psci_arch_initChen-Yu Tsai1-1/+6
2016-02-06Use correct spelling of "U-Boot"Bin Meng1-1/+1
2015-10-11arndale: Apply Cortex-A15 errata #773022 and #774769Ian Campbell1-0/+14
2014-12-11ARM: HYP/non-sec: Fix the ARCH Timer frequency setting.Xiubo Li1-2/+2
2014-12-11ARM: HYP/non-sec: add the pen address BE mode support.Xiubo Li1-0/+3
2014-07-28ARM: HYP/non-sec: add the option for a second-stage monitorMarc Zyngier1-2/+11
2014-07-28ARM: HYP/non-sec: allow relocation to secure RAMMarc Zyngier1-84/+77
2014-07-28ARM: non-sec: reset CNTVOFF to zeroMarc Zyngier1-1/+8
2014-07-28ARM: HYP/non-sec: add a barrier after setting SCR.NS==1Marc Zyngier1-0/+1
2013-12-06ARM: align MVBAR on 32 byte boundaryMasahiro Yamada1-1/+1
2013-10-07ARM: virtualization: replace verbose license with SPDX identifierAndre Przywara1-17/+1
2013-10-03ARM: extend non-secure switch to also go into HYP modeAndre Przywara1-5/+38
2013-10-03ARM: add SMP support for non-secure switchAndre Przywara1-0/+35
2013-10-03ARM: add assembly routine to switch to non-secure stateAndre Przywara1-0/+87
2013-10-03ARM: add secure monitor handler to switch to non-secure stateAndre Przywara1-0/+53
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