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2020-12-20Merge tag 'efi-2021-01-rc4' of ↵WIP/20Dec2020Tom Rini1-0/+2
https://gitlab.denx.de/u-boot/custodians/u-boot-efi Pull request for UEFI sub-system for efi-2021-01-rc4 * Provide a tool to create a file with UEFI variables to preseed UEFI variable store. * Make size of UEFI variable store configurable. * Add man pages for commands 'bootefi' and 'button'.
2020-12-20MAINTAINERS: add tools/efivar.py to EFI PAYLOADHeinrich Schuchardt1-0/+1
tools/efivar.py allows to prepare a file with UEFI variables to preseed the UEFI variable store. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-12-20doc: man-page for bootefi commandHeinrich Schuchardt1-0/+1
Provide a description of the bootefi command. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-12-18spi: ca_sflash: Add CAxxxx SPI Flash ControllerPengpeng Chen1-0/+2
Add SPI Flash controller driver for Cortina Access CAxxxx SoCs Signed-off-by: Pengpeng Chen <pengpeng.chen@cortina-access.com> Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com> CC: Vignesh R <vigneshr@ti.com> CC: Tom Rini <trini@konsulko.com> [jagan: rebase on master] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-12-09MAINTAINERS: Update ARM STI and ARM STM STM32MP Arch maintainers emailsPatrice Chotard1-3/+3
Update Patrick and my email address with the one dedicated to upstream activities. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-12-02MAINTAINERS: assign include/log.hHeinrich Schuchardt1-0/+1
include/log.h belongs to LOGGING. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-30lib: Add getoptSean Anderson1-0/+1
Some commands can get very unweildy if they have too many positional arguments. Adding options makes them easier to read, remember, and understand. This implementation of getopt has been taken from barebox, which has had option support for quite a while. I have made a few modifications to their version, such as the removal of opterr in favor of a separate getopt_silent function. In addition, I have moved all global variables into struct getopt_context. The getopt from barebox also re-orders the arguments passed to it so that non-options are placed last. This allows users to specify options anywhere. For example, `ls -l foo/ -R` would be re-ordered to `ls -l -R foo/` as getopt parsed the options. However, this feature conflicts with the const argv in cmd_tbl->cmd. This was originally added in 54841ab50c ("Make sure that argv[] argument pointers are not modified."). The reason stated in that commit is that hush requires argv to stay unmodified. Has this situation changed? Barebox also uses hush, and does not have this problem. Perhaps we could use their fix? I have assigned maintenance of getopt to Simon Glass, as it is currently only used by the log command. I would also be fine maintaining it. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-10-29Merge tag 'xilinx-for-v2021.01-v2' of ↵Tom Rini1-0/+1
https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2021.01-v2 common: - Add support for 64bit loadables from SPL xilinx: - Update documentation and record ownership - Enable eeprom board detection based legacy and fru formats - Add support for FRU format microblaze: - Optimize low level ASM code - Enable SPI/I2C - Enable distro boot zynq: - Add support for Zturn V5 zynqmp: - Improve silicon detection code - Enable several kconfig options - Align DT with the latest state - Enabling security commands - Enable and support FPGA loading from SPL - Optimize xilinx_pm_request() calling versal: - Some DTs/Kconfig/defconfig alignments - Add binding header for clock and power zynq-sdhci: - Add support for tap delay programming zynq-spi/zynq-qspi: - Use clock framework for getting clocks xilinx-spi: - Fix some code issues (unused variables) serial: - Check return value from clock functions in pl01x
2020-10-29MAINTAINERS, git-mailrc: Update sunxi maintainersAndre Przywara1-1/+1
Maxime mentioned that he feels not having the time to be an Allwinner maintainer anymore. Take over from him. Maxime, many thanks for your great work in the past! I hope I can still relay the occasional technical question to you in the future. Acked-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2020-10-27rtc: provide an emulated RTCHeinrich Schuchardt1-0/+1
On a board without hardware clock this software real time clock can be used. The build time is used to initialize the RTC. So you will have to adjust the time either manually using the 'date' command or use the 'sntp' to update the RTC with the time from a network time server. See CONFIG_CMD_SNTP and CONFIG_BOOTP_NTPSERVER. The RTC time is advanced according to CPU ticks. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-10-27MAINTAINERS: Record documentation for Xilinx platformsMichal Simek1-0/+1
Add fragment to cover documenation for Xilinx platforms. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-10-26riscv: Move timer portions of SiFive CLINT to drivers/timerSean Anderson1-0/+1
Half of this driver is a DM-based timer driver, and half is RISC-V-specific IPI code. Move the timer portions in with the other timer drivers. The KConfig is not moved, since it also enables IPIs. It could also be split into two configs, but no boards use the timer but not the IPI atm, so I haven't split it. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com>
2020-10-26riscv: Move Andes PLMT driver to drivers/timerSean Anderson1-0/+1
This is a regular timer driver, and should live with the other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com>
2020-10-22rng: Add Qualcomm MSM PRNG driverRobert Marko1-0/+1
Add support for the hardware pseudo random number generator found in Qualcomm SoC-s. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-10-22net: Add IPQ40xx MDIO driverRobert Marko1-0/+1
This adds the driver for the IPQ40xx built-in MDIO. This will be needed to support future PHY driver. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-10-22spi: Add Qualcomm QUP SPI controller driverRobert Marko1-0/+1
This patch adds support for the Qualcomm QUP SPI controller that is commonly found in most of Qualcomm SoC-s. Driver currently supports v1.1.1, v2.1.1 and v2.2.1 HW. FIFO and Block modes are supported, no support for DMA mode is planned. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-10-22Merge tag 'u-boot-stm32-20201021' of ↵Tom Rini1-0/+3
https://gitlab.denx.de/u-boot/custodians/u-boot-stm - Activate CMD_EXPORTENV/CMD_IMPORTENV/CMD_ELF for STM32MP15 defconfig - Fix stm32prog command: parsing of FlashLayout without partition - Update MAINTAINERS for ARM STM STM32MP - Manage eth1addr on dh board with KS8851 - Limit size of cacheable DDR in pre-reloc stage in stm32mp1 - Use mmc_of_parse() to read host capabilities in mmc:sdmmc2 driver
2020-10-21MAINTAINERS: Add STM32MP1 RNG driver in stm32mp platformPatrick Delaunay1-0/+1
Add the STM32MP1 RNG driver in the list of drivers supported by the STMicroelectronics STM32MP15x series. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-21MAINTAINERS: Add stm32 and stm regexp for ARM STM STM32MP platformPatrick Delaunay1-0/+2
Add files and directories regex "stm32" and "stm" in "ARM STM STM32MP" platform to avoid missing files or drivers supported by the STMicroelectronics series STM32MP15x. This patch adds the rules already used in Linux kernel for ARM/STM32 ARCHITECTURE. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-20MAINTAINERS: add USB driver to ARM MEDIATEKChunfeng Yun1-0/+3
Add MediaTek USB3 Dual-Role controller driver to ARM MEDIATEK, and add myself as a maintainer for it. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-08pinctrl: Add support for Kendryte K210 FPIOASean Anderson1-0/+2
The Fully-Programmable Input/Output Array (FPIOA) device controls pin multiplexing on the K210. The FPIOA can remap any supported function to any multifunctional IO pin. It can also perform basic GPIO functions, such as reading the current value of a pin. However, GPIO functionality remains largely unimplemented (in favor of the dedicated GPIO peripherals). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-08test: pinmux: Add test for pin muxingSean Anderson1-0/+1
This extends the pinctrl-sandbox driver to support pin muxing, and adds a test for that behaviour. The test is done in C and not python (like the existing tests for the pinctrl uclass) because it needs to call pinctrl_select_state. Another option could be to add a command that invokes pinctrl_select_state and then test everything in test/py/tests/test_pinmux.py. The pinctrl-sandbox driver now mimics the way that many pinmux devices work. There are two groups of pins which are muxed together, as well as four pins which are muxed individually. I have tried to test all normal paths. However, very few error cases are explicitly checked for. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-06MAINTAINERS: assign doc/arch/sandbox.rstHeinrich Schuchardt1-0/+1
Add doc/arch/sandbox.rst to the scope of SANDBOX. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-05Merge tag 'u-boot-atmel-2021.01-a' of ↵Tom Rini1-0/+2
https://gitlab.denx.de/u-boot/custodians/u-boot-atmel into next First set of u-boot-atmel features for 2021.01 cycle: This feature set includes a new CPU driver for at91 family, new driver for PIT64B hardware timer, support for new at91 family SoC named sama7g5 which adds: clock support, including conversion of the clock tree to CCF; SoC support in mach-at91, pinctrl and mmc drivers update. The feature set also includes updates for mmc driver and some other minor fixes and features regarding building without the old Atmel PIT and the possibility to read a secondary MAC address from a second i2c EEPROM.
2020-10-05cpu: at91: add driver for CPUClaudiu Beznea1-0/+1
Add basic CPU driver use to retrieve information about CPU itself. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-28MAINTAINERS: add Microchip PIT64B timerClaudiu Beznea1-0/+1
Add Microchip PIT64B timer. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-21Merge branch 'master' into nextTom Rini1-1/+3
Merge in v2020.10-rc5
2020-09-18phy: add driver for Qualcomm IPQ40xx USB PHYRobert Marko1-0/+1
Add a driver to setup the USB PHY-s on Qualcomm IPQ40xx series SoCs. The driver sets up HS and SS phys. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-09-18reset: Add IPQ40xx reset controller driverRobert Marko1-0/+2
On Qualcomm IPQ40xx SoC series, GCC clock IP also handles the resets. So since this will be needed by further drivers, lets add a driver for the reset controller. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-09-16MAINTAINERS: add myself as reviewer for SquashFSMiquel Raynal1-0/+1
I also followed the development of the SquashFS support in U-Boot as part of Joao Marcos internship, so I would also appreciate receiving new contributions and bug reports related to this topic. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2020-09-16MAINTAINERS: add myself as reviewer for SquashFSThomas Petazzoni1-0/+1
As I have followed the development of the SquashFS support in U-Boot as part of Joao Marcos work, it makes sense to get Cc'ed on contributions/bug reports related to the squashfs support. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
2020-09-16MAINTAINERS: update clk entry git treeBaruch Siach1-1/+1
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
2020-09-09dt-bindings: clock: import Qualcomm IPQ4019 bindingsRobert Marko1-0/+1
Import Qualcomm IPQ4019 GCC bindings from Linux. This will enable using bindings instead of raw clock numbers both in the driver and DTS like Linux does. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-09-09MAINTAINERS: update maintainers file for new filesRayagonda Kokatanur1-0/+4
Update MAINTAINERS file for new files. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-07MAINTAINERS: Add btrfs mailing list and myself as reviewerQu Wenruo1-0/+2
Since the current code base is mostly from btrfs-progs, anyone contributing to U-Boot btrfs code could also help us to improve btrfs-progs and btrfs kernel module. Also add myself as designated reviewer. Signed-off-by: Qu Wenruo <wqu@suse.com> Reviewed-by: Marek Behún <marek.behun@nic.cz>
2020-08-31MAINTAINERS: step down as maintainer of UniPhier SoCsMasahiro Yamada1-3/+1
I am leaving Socionext. Orphan the UniPhier platform until somebody takes the role. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-08-24MAINTAINERS: Add maintainers to XEN sectionAnastasiia Lukianenko1-0/+16
Signed-off-by: Anastasiia Lukianenko <anastasiia_lukianenko@epam.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-14MAINTAINERS: Add maintainers for Aspeed SoCsChia-Wei, Wang1-0/+12
Update maintainers for Aspeed SoC platforms. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
2020-08-07led: led_cortina: Add CAxxx LED supportJway Lin1-1/+3
Add Cortina Access LED controller support for CAxxxx SOCs Signed-off-by: Jway Lin <jway.lin@cortina-access.com> Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com> CC: Simon Glass <sjg@chromium.org> Add head file fixed link error and remove unused flashing function Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-07test/py: Add tests for the SquashFS commandsJoao Marcos Costa1-0/+1
Add Python scripts to test 'ls' and 'load' commands. The scripts generate a SquashFS image and clean the directory after the assertions, or if an exception is raised. Signed-off-by: Joao Marcos Costa <joaomarcos.costa@bootlin.com>
2020-08-07fs/squashfs: add filesystem commandsJoao Marcos Costa1-0/+1
Add 'ls' and 'load' commands. Signed-off-by: Joao Marcos Costa <joaomarcos.costa@bootlin.com>
2020-08-07fs/squashfs: new filesystemJoao Marcos Costa1-0/+6
Add support for SquashFS filesystem. Right now, it does not support compression but support for zlib will be added in a follow-up commit. Signed-off-by: Joao Marcos Costa <joaomarcos.costa@bootlin.com>
2020-07-29MAINTAINERS: update maintainers for broadcom ns3 platformRayagonda Kokatanur1-0/+15
Update MAINTAINERS for broadcom ns3 platform (TARGET_NS3). Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-29arm: add (default) config for nanopi2 boardStefan Bosch1-0/+17
Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01: - Configuration changed, mainly several "CONFIG_..." moved from s5p4418_nanopi2.h to s5p4418_nanopi2_defconfig and USB related configs removed because USB is not supported yet. - s5p4418_nanopi2.h: "CONFIG_" removed from several s5p4418/nanopi2 specific defines because the appropriate values do not need to be configurable. - pinctrl is supported now, therefore "CONFIG_PINCTRL=y" added to s5p4418_nanopi2_defconfig. Signed-off-by: Stefan Bosch <stefan_b@posteo.net>
2020-07-29arm: Add support for Qualcomm IPQ40xx familyRobert Marko1-0/+7
This introduces initial support for the popular Qualcomm IPQ40x8 and IPQ40x9 WiSoC series. IPQ40xx series have 4x Cortex A7 ARM-v7A cores. Supported are: IPQ4018, IPQ4019, IPQ4028 and IPQ4029. IPQ40x8 and IPQ40x9 use the same cores, but differ in addressable RAM size (1GB for IPQ40x9 and 256MB for IPQ40x8) and supported peripherals (IPQ40x8 lacks RGMII, LCD controller and EMMC/SDHCI controllers). IQP4028/IPQ4029 models differ from IPQ4018/IPQ4019 only by their rated temperatures rates with IPQ402X models being rated for wider temperature ranges. Initially this supports: * Simple clock driver (Only for UART1 now, will be extended) * Pinctrl driver (Supports UARTX and GPIO now, will be extended) * GPIOs already supported by msm_gpio driver with updates * UARTs already supported by serial_msm driver with updates Further peripherals will come in later patches. Signed-off-by: Robert Marko <robert.marko@sartura.hr>
2020-07-27Watchdog: introduce ARM SBSA watchdog driverZhao Qiang1-0/+1
According to Server Base System Architecture (SBSA) specification, the SBSA Generic Watchdog has two stage timeouts: the first signal (WS0) is for alerting the system by interrupt, the second one (WS1) is a real hardware reset. More details about the hardware specification of this device: ARM DEN0029B - Server Base System Architecture (SBSA) This driver can operate ARM SBSA Generic Watchdog as a single stage In the single stage mode, when the timeout is reached, your system will be reset by WS1. The first signal (WS0) is ignored. Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-18mips: octeon: dts: Add Octeon 3 cn73xx base dtsi fileStefan Roese1-0/+1
This patch adds the base dtsi file for the Octeon 3 cn73xx SoC. Signed-off-by: Stefan Roese <sr@denx.de>
2020-07-18mips: octeon: Initial minimal support for the Marvell Octeon SoCAaron Williams1-0/+6
This patch adds very basic support for the Octeon III SoCs. Only CFI parallel NOR flash and UART is supported for now. Please note that the basic Octeon port does not include the DDR3/4 initialization yet. This will be added in some follow-up patches later. To still use U-Boot on with this port, the L2 cache (4MiB on Octeon III CN73xx) is used as RAM. This way, U-Boot can boot to the prompt on such boards. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2020-07-09i2c: i2c-cortina: added CAxxxx I2C supportArthur Li1-0/+4
Add I2C controller support for Cortina Access CAxxxx SoCs Signed-off-by: Arthur Li <arthur.li@cortina-access.com> Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com> CC: Heiko Schocher <hs@denx.de> Reviewed-by: Heiko Schocher <hs@denx.de> hs: fixed build error, add include log.h
2020-07-05Merge tag 'efi-2020-10-rc1' of ↵Tom Rini1-0/+1
https://gitlab.denx.de/u-boot/custodians/u-boot-efi into next Pull request for UEFI sub-system for efi-2020-10-rc1 This series comprises error corrections for the UEFI subsystem: * correct consideration of timestamps for variable authentication * correct collection of data regions for code authentication * correct unit tests to test loading dbx * enable FAT_WRITE as required by the UEFI spec The boot manager uses log functions instead of printf() and debug(). The UEFI intialization state is exported.
generated by cgit v1.1 at 2024-07-14 14:23:47 +0000