aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2015-11-12fastboot: Move fastboot response functions to fastboot coreMaxime Ripard5-59/+76
The functions and a few define to generate a fastboot message to be sent back to the host were so far duplicated among the users. Move them all to a common place. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2015-11-12sparse: Simplify multiple logicMaxime Ripard1-4/+10
To check the alignment of the image blocks to the storage blocks, the current code uses a convoluted syntax, while a simple mod also does the work. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2015-11-12sparse: Refactor chunk parsing functionMaxime Ripard1-133/+239
The chunk parsing code was duplicating a lot of code among the various chunk types, while all of them could be covered by generic and simple functions. Refactor the current code to reuse as much code as possible and hopefully make the chunk parsing loop more readable and concise. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2015-11-12sparse: Move main header parsing to a function of its ownMaxime Ripard1-21/+24
The current sparse image format parser is quite tangled, with a lot of code duplication. Start refactoring it by moving the header parsing function to a function of its own. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2015-11-12mtd: uboot: Add meaningful error messageMaxime Ripard1-1/+1
The current error message in get_part if CONFIG_MTDPARTS is disabled is "offset is not a number" which is confusing and doesn't help at all. Change that for something that might give a hint on what's going on. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2015-11-12board/BuR/kwb: use bootvx(...) (with bootline feature) instead go(...)Hannes Petermaier3-21/+17
Since we don't have for sure a valid IP-setup during board_late_init(...) because it maybe allready stored in environment or not, we cannot form a proper vxWorks bootline at this place. So we move to the way, forming the bootline just before executing/launching vxWorks. To do this we use the bootvx command instead go. We only have to form the "othbootargs" environment variable, the rest is done pretty good by the "bootvx" commannd. Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-12ARM: tegra: note that p2371-2180 is Jetson TX1Stephen Warren1-5/+5
p2371-2180 is the engineering board name for the Jetson TX1 developer kit. Update Kconfig description and help text to make this obvious to everyone. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-11-12Tegra: T210: Add QSPI driverTom Warren3-0/+425
This is the normal Tegra SPI driver modified to work with the QSPI controller in Tegra210. It does not do 2x/4x transfers or any other QSPI protocol. Signed-off-by: Yen Lin <yelin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-11-12ARM: tegra: rename GPU functionsAlexandre Courbot3-8/+8
Rename GPU functions to less generic names to avoid potential name collisions. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-11-12ARM: tegra: simplify GPU setupAlexandre Courbot8-29/+22
Enable the GPU node in the system-wide ft_system_setup() hook instead of the board-specific ft_board_hook(). This allows us to enable GPU per SoC generation instead of per-board as we did initially. Reported-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-11-12ARM: tegra: remove vpr_configured() functionAlexandre Courbot2-12/+1
There is no justification for this function, especially in exported form. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-11-12ARM: tegra: error check Tegra210 XUSB padctl waitsStephen Warren1-5/+20
Add code to detect timeouts when waiting for HW events such as PLL lock done. Any errors are logged and trigger an error return code. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-11-12ARM: tegra: add lane tables to Tegra210 XUSB padctlStephen Warren2-6/+76
Add the tables defining which pads and mux options exist in the Tegra210 XUSB padctl hardware. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-11-12ARM: tegra: switch Tegra210 to common XUSB padctlStephen Warren2-158/+16
This change simply deletes code from the Tegra210 XUSB padctl driver that is already present in the common XUSB padctl code. Since all the arrays in tegra210_socdata are empty, this update may leave the Tegra210 XUSB padctl driver non-functional at run-time. However, (a) this driver is not used yet so no regression can be observed and (b) the next commit will immediately fix this up. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-11-12ARM: tegra: parameterize common XUSB codeStephen Warren2-82/+34
There are some differences between the Tegra124 and Tegra210 XUSB padctl code. So far, the common XUSB padctl code only supports Tegra124. Add some parameters etc. so that it can work for both chips. This also allows moving Tegra124's process_nodes() into the common file; something that would have requires edits during the move if done in the previous commit. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-11-12ARM: tegra: create common XUSB padctl driver fileStephen Warren4-341/+414
A fair amount of the XUSB padctl driver will be common between Tegra124 and Tegra210. To avoid cut/paste between the two chips, create a new file that will contain the common code, and convert the Tegra124 code to use it. This change doesn't move every last piece of code that can/will be shared, but rather concentrates on moving code that can be moved with zero changes, so there are no other diffs mixed in. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-11-12ARM: tegra: clean up XUSB padctl error() callsStephen Warren1-19/+14
This file defines pr_fmt(), so the individual error() calls don't need to include the prefix in their format strings. Doing so results in duplicate text in any error messages. Remove the duplication. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-11-12ARM: tegra: rename dummy XUSB padctl implementationStephen Warren2-1/+1
A future patch will soon move some of the XUSB padctl code into a common file in arch/arm/mach-tegra. Rename the existing dummy XUSB padctl file to avoid conflicting with that, or being confusing. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-11-12ARM: tegra: enable PCI support of p2371-2180Stephen Warren3-0/+90
p2371-2180 has two PCI ports; a regular x4 slot and a x1 M.2 slot. This patch adds the relevant DT to enable the PCI controller and configure the XUSB padctl pin muxing, and code to turn on the PCI power and enable PCI features in U-Boot. I have only tested the x4 slot. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-11-12ARM: tegra: add PCI to Tegra210 SoC DTStephen Warren1-0/+66
Tegra210's PCI controller is largely identical to Tegra124, and hence shares the same binding. However, it has a unique compatible value due to the existence of at least one new HW bug that would prevent any driver for a previous HW version from operating correctly. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-11-12pci: tegra: add/enable support for Tegra210Stephen Warren3-0/+24
This needs a separate compatible value from Tegra124 since the new HW version has bugs that would prevent a driver for previous HW versions from operating at all. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-11-12pci: tegra: call tegra_pcie_board_init() earlierStephen Warren1-2/+2
The board PCI setup code may control regulators that are required simply to bring up the PCI controller itself (or PLLs, IOs, ... it uses). Move the call to this function earlier so that all board-provided resources are ready early enough for everything to work. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-11-12pci: tegra: implement PCA enable workaroundStephen Warren1-0/+14
Tegra210's PCIe controller has a bug that requires the PCA (performance counter) feature to be enabled. If this isn't done, accesses to device configuration space will hang the chip for tens of seconds. Implement the workaround. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-11-12pci: tegra: use #address-/size-cells from DTStephen Warren1-3/+30
The number of cells used by each entry in the DT ranges property is determined by the #address-cells/#size-cells properties. Fix the code to respect this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-11-12pci: tegra: clip RAM size to 32-bitsStephen Warren1-1/+9
Tegra peripherals can generally access a 32-bit physical address space, and I believe this applies to PCIe. Clip the PCI region that refers to DRAM so it fits into 32-bits to avoid issues. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-11-12ARM: tegra210: implement PLLE init procedure from TRMStephen Warren1-47/+132
Implement the procedure that the TRM mandates to initialize PLLREFE and PLLE. This makes the PLL actually lock. Note that this section of the TRM is being cleaned up to remove some confusion. The set of register accesses in this patch should be final, although the step numbers/descriptions might still change. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-11-12Merge branch 'next' of git://git.denx.de/u-boot-blackfinTom Rini6-6/+0
2015-11-12nios2: add 3c120 and 10m50 devboards MAINTAINERSThomas Chou1-0/+13
Add 3c120 and 10m50 devboards MAINTAINERS Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Marek Vasut <marex@denx.de>
2015-11-12nios2: change README.nios2 to use 10m50 as templateThomas Chou1-7/+7
The 10m50 devboard becomes the new golden reference design of Nios II Linux. So change README.nios2 to use 10m50 as template. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Marek Vasut <marex@denx.de>
2015-11-12nios2: rename board nios2-generic to 3c120_devboardThomas Chou2-1/+1
Rename board nios2-generic to 3c120_devboard. Since nios2 is converted to driver model and device tree control of u-boot, the nios2-generic board directory is removed. We can rename the board back to a real board name. Now the boards maintained in u-boot mainline are the same as Linux kernel, namely 3c120 and 10m50. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de>
2015-11-12nios2: add 10m50 devboard supportThomas Chou3-0/+396
Add 10m50 devboard support. It is based on the Golden Hardware Reference Design (GHRD), available at, http://rocketboards.org/foswiki/view/Documentation/ AlteraMAX1010M50RevCDevelopmentKitLinuxSetup Though we supported only one nios2-generic board in the past. Now, with the removal of the nios2-generic board dir, adding new nios2 boards to u-boot is easier than before. It should be helpful to add those boards supported in Linux mainline. There are only two such nios2 boards, the 3c120 devboard and 10m50 devboard. The nios2-generic is actually 3c120, and should restore the name. The 10m50 is this one. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Marek Vasut <marex@denx.de>
2015-11-12net: altera_tse: add mSG-DMA supportThomas Chou2-0/+191
The Modular Scatter-Gather DMA core is a new DMA core to work with the Altera Triple-Speed Ethernet MegaCore. It replaces the legacy Scatter-Gather Direct Memory Access (SG-DMA) controller core. Please find details on the "Embedded Peripherals IP User Guide" of Altera. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Marek Vasut <marex@denx.de>
2015-11-12net: altera_tse: add priv ops to prepare msgdma supportThomas Chou2-25/+81
Add priv ops to prepare msgdma support. These ops are dma type specific. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Marek Vasut <marex@denx.de>
2015-11-12net: altera_tse: wait sgdma in altera_tse_recvThomas Chou1-1/+1
Move the sgdma wait from free_pkt to recv. This is the proper place to wait recv sgdma done. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Marek Vasut <marex@denx.de>
2015-11-12net: altera_tse: factor out stop mac funcThomas Chou1-15/+21
Factor out the stop mac function to prepare msgdma support. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Marek Vasut <marex@denx.de>
2015-11-12net: zap altera_tse_initialize prototypesThomas Chou1-3/+0
Zap the altera_tse_initialize() prototypes, since it is converted to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Marek Vasut <marex@denx.de>
2015-11-12nios2: nios2-generic: do not allocate rx buf in net.cThomas Chou1-1/+2
Do not allocate rx buf in net.c, because altera_tse allocates its own rx buf in driver. This can save 6KB memory. Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
2015-11-12mtd: add altera quadspi driverThomas Chou4-0/+318
Add Altera Generic Quad SPI Controller support. The controller converts SPI NOR flash to parallel flash interface. So it is not like other SPI flash, but rather like CFI flash. Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
2015-11-12nios2: add memcpy_fromio and memcpy_toioThomas Chou1-0/+4
Add memcpy_fromio() and memcpy_toio(). Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
2015-11-12nios2: use cfi flash driver modelThomas Chou2-2/+3
Use cfi flash driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
2015-11-12cfi_flash: convert to driver modelThomas Chou3-0/+177
Convert cfi flash to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org>
2015-11-12dm: implement a MTD uclassThomas Chou7-0/+63
Implement a Memory Technology Device (MTD) uclass. It should include most flash drivers in the future. Though no uclass ops are defined yet, the MTD ops could be used. The NAND flash driver is based on MTD. The CFI flash and SPI flash support MTD, too. It should make sense to convert them to MTD uclass. Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
2015-11-11ARM: uniphier: drop UniPhier specific SMP codeMasahiro Yamada2-61/+0
The latest Linux can directly handle SMP operations for UniPhier SoCs without any help of U-boot. Drop the relevant code from U-boot. See commit b1e4006aeda8c8784029de17d47987c21ea75f6d ("ARM: uniphier: rework SMP operations to use trampoline code") in Linux Kernel. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2015-11-11ARM: dts: uniphier: add USB xHCI nodes for PH1-Pro5 and ProXstream2Masahiro Yamada6-0/+60
This makes USB3.0 available on new SoCs/boards. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2015-11-11ARM: dts: uniphier: fix interrupt number of USB core for PH1-Pro4Masahiro Yamada1-1/+1
The IRQ is not used in U-Boot, but this would be useful to sync device trees between Linux and U-Boot. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-11-10Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini36-17/+855
2015-11-10ARM: tegra: enable CONFIG_SYS_NONCACHED_MEMORY everywhereStephen Warren1-2/+0
Now that we have solved the problems that prevented this feature from being enabled, enable it everywhere. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2015-11-10ARM: tegra: add custom MMU setup on ARMv8Stephen Warren2-0/+132
This sets up a fine-grained page table, which is a requirement for noncached_init() to operate correctly. MMU setup code currently exists in a number of places: - A version in the core ARMv8 support code that sets up page tables that use very large block sizes that CONFIG_SYS_NONCACHED_MEMORY doesn't support. - Enhanced versions for fsl-lsch3 and zynmq that set up finer grained page tables. Ideally, rather than duplicating the MMU setup code yet again this patch would instead consolidate all the different routines into the core ARMv8 code so that it supported all use-cases. However, this will require significant effort since there appear to be a number of discrepancies[1] between different versions of the code, and between the defines/values by some copies of the MMU setup code use and the architectural MMU documentation. Some reverse engineering will be required to determine the intent of the current code. [1] For example, in the core ARMv8 MMU setup code, three defines named TCR_EL[123]_IPS_BITS exist, but only one of them sets the IPS field and the others set a different field (T1SZ) in the page tables. As far as I can tell so far, there should be no need to set different values per exception level nor to modify the T1SZ field at all, since TTBR1 shouldn't be enabled anyway. Another example is inconsistent values for *_VA_BITS between the current core ARMv8 MMU setup code and the various SoC- specific MMU setup code. Another example is that asm/armv8/mmu.h's value for SECTION_SHIFT doesn't match asm/system.h's MMU_SECTION_SHIFT; research is needed to determine which code relies on which of those values and why, and whether fixing the incorrect value will cause any regression. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2015-11-10armv8: allow custom MMU setup routines on ARMv8Stephen Warren1-1/+1
In order for noncached_init() to operate correctly, SoCs must set up a custom page table with fine-grained (2MiB) sections, which can be configured from noncached_init(). This is currently performed by arch/arm/cpu/armv8/{fsl-lsch3,zynqmp}/cpu.c by cut/pasting and re-implementing mmu_setup, enable_caches(), etc. There are some other reasons for the duplication there though, such as enabling icache early, and enabling dcaching earlier with a different configuration. This change makes mmu_setup() a weak implementation, so that the MMU setup code can be replaced without having to duplicate other code that calls it. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2015-11-10armv8: enable compilation with CONFIG_SYS_NONCACHED_MEMORYStephen Warren1-5/+6
The implementation of noncached_init() uses define MMU_SECTION_SIZE. Define this on ARM64. Move the prototype of noncached_{init,alloc}() to a location that doesn't depend on !defined(CONFIG_ARM64). Note that noncached_init() calls mmu_set_region_dcache_behaviour() which relies on something having set up translation tables with 2MB block size. The core ARMv8 MMU setup code does not do this by default, but currently relies on SoC specific MMU setup code. Be aware of this before enabling this feature on your platform! Signed-off-by: Stephen Warren <swarren@nvidia.com>
generated by cgit v1.1 at 2024-07-31 05:25:30 +0000