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2018-05-30fastboot: Extract fastboot_okay/fail to fb_common.cAlex Kiernan5-16/+88
Add drivers/fastboot/fb_common.c, where fastboot_okay/fail are implemented so we can call them from a non-USB implementation. Introduce fastboot_response which takes varargs parameters so we can use it to generate formatted response strings. Refactor fastboot_okay/fail to use it. Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2018-05-30fastboot: Refactor fastboot_okay/fail to take responseAlex Kiernan9-97/+105
Add the response string as a parameter to fastboot_okay/fail, instead of modifying a global, to match the contract expected by the AOSP U-Boot code. Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2018-05-30fastboot: Move fastboot to drivers/fastbootAlex Kiernan47-79/+75
Separate CMD_FASTBOOT from FASTBOOT and move code and configuration to drivers/fastboot. Switch dependencies on FASTBOOT to USB_FUNCTION_FASTBOOT as anyone who wants FASTBOOT before this series wants USB_FUNCTION_FASTBOOT. Split USB_FUNCTION_FASTBOOT from FASTBOOT so they retain their existing behaviour. Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-05-30gadget: f_thor: Fix memory leaks of usb request and its bufferSeung-Woo Kim1-33/+32
There are memory leaks of usb request and its buffer for ep0, in_ep, and out ep. Fix memory leaks of usb request and its buffer. Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
2018-05-30rockchip: xhci: remove DTS parsing for PHY (which is unused)Philipp Tomsich1-16/+0
The xhci wrapper-driver for Rockchip searches the DTS to find its child node compatbile with 'rockchip,rk3399-usb3-phy' to retrieve the base-address of the PHY. However, this is currently broken (and always has been), returning NULL. However, the (wrongly) retrieved base-address is never used. We thus remove this code for now. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-05-30usb: xhci: Handle endianness in xhci_set_configuration()Bin Meng1-1/+1
In xhci_set_configuration(), 'Context Entries' field in the slot context was cleared with mask LAST_CTX_MASK, but it should have taken the endianness into consideration. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2018-05-30usb: xhci: Fix config fail of FS hub behind a HS hub with MTTBin Meng1-1/+8
If a full speed hub connects to a high speed hub which supports MTT, the MTT field of its slot context will be set to 1 when xHCI driver setups an xHCI virtual device in xhci_setup_addressable_virt_dev(). Once usb core fetch its hub descriptor, and need to update the xHC's internal data structures for the device, the HUB field of its slot context will be set to 1 too, meanwhile MTT is also set before, this will cause configure endpoint command fail. In the case, we should clear MTT to 0 for full speed hub according to section 6.2.2. This keeps in sync with Linux kernel commit: 096b110: usb: xhci: fix config fail of FS hub behind a HS hub with MTT Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2018-05-30usb: xhci: Initialize dev_state to 0 in the input slot contextBin Meng1-0/+1
Per xHCI spec chapter 6.2.2 table 6-7, as input, software shall initialize the dev_state field to '0'. Though this does not seem to cause any issue with most xHC implementations, let's do this to conform with the spec. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Marek Vasut <marek.vasut@gmail.com> Tested-by: Matthias Blankertz <matthias.blankertz@cetitec.com>
2018-05-30usb: xhci: Set accurate add context flags when updating hub attributesBin Meng1-1/+1
If a USB 3.0 hub is plugged into the root port of the xHC, the xHCI driver will issue a 'Configure Endpoint' command to the xHC for it to update its internal data structure for this hub device. The hub attributes are in the slot context so we need tell xHC to update the slot context by setting the add context flags of the input control context to only cover the slot context. At present the add context flags is or'ed with the slot context bit, but it should really be accurately set to the slot context, as the variable that holds the value of the add context flags comes from whatever was set in the last command execution, which may contain additional contexts that 'Configure Endpoint' command should not touch. Some xHC implementations like x86 don't complain such, but it was observed on Renesas RCar Gen3 platform that the RCar xHC complains with a 'TRB error' completion codes as the response. Reported-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Marek Vasut <marek.vasut@gmail.com> Tested-by: Matthias Blankertz <matthias.blankertz@cetitec.com>
2018-05-30usb: xhci-rcar: deregister before deactivating clockMatthias Blankertz1-1/+4
During the execution of xhci_deregister xHCI registers are accessed. If the clock is already deactivated when xhci_deregister is called this can lead to undefined behavior. Change the order to deregister the device before deactivating the clock. Signed-off-by: Matthias Blankertz <matthias.blankertz@cetitec.com>
2018-05-26add FIT data-position & data-offset property supportKelvin Cheung2-3/+53
Add FIT data-position & data-offset property support for bootm, which were already supported in SPL. Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com>
2018-05-26malloc: Use malloc simple before malloc is fully initialized in memalign()Ley Foon Tan1-0/+7
Follow implementation in mALLOc(). Check GD_FLG_FULL_MALLOC_INIT flag and use malloc_simple if GD_FLG_FULL_MALLOC_INIT is unset. Adjust the malloc bytes to align with the requested alignment. The original memalign() function will access mchunkptr struct to adjust the alignment if there is misalignment happen, but mchunkptr struct is not being initialized before full malloc is initialized. This cause the system crash. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
2018-05-26mmc: stm32_sdmmc2: Fix stm32_sdmmc2_start_cmd()Patrice Chotard1-2/+2
SDMMC_CMD_CPSMEN bit is wrongly check and set in SDMMC_ARG register instead of SDMMC_CMD register. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-26stm32mp1: use OTP to configure MAC address and serial numberPatrick Delaunay1-0/+81
Use OTP57 and 58 for MAC address - OTP57 = MAC address bits [31:0] - OTP58 = MAC address bit [47:32] stored in OTP LSB's Use manufacture information in OTP13 to OTP15 to build unique chip id saved in env variable "serial#" (used for USB device enumeration) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-26stm32mp1: add FUSE command supportPatrick Delaunay6-0/+129
Add support of fuse command (read/write/program/sense) on bank 0 to access to BSEC SAFMEM (4096 OTP bits). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-26stm32mp1: add bsec driverPatrick Delaunay3-2/+442
Add a MISC driver with read and write access to BSEC IP (Boot and Security and OTP control) - offset 0: shadowed values - offset 0x80000000: OTP fuse box values (SAFMEM) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-26stm32mp1: remove the second TAMP_BOOT_CONTEXT updatePatrick Delaunay1-3/+0
The register TAMP_BOOT_CONTEXT is already updated in get_bootmode() in cpu.c and no need to be done twice. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-26stm32mp1: Allow to activate CONFIG_DEBUG_UARTPatrick Delaunay4-1/+67
Add the needed information to enable the debug uart to have printf before the serial driver probe (so before probe for clock, pincontrol and reset drivers) To enable the debug on uart 4 (default console): + CONFIG_DEBUG_UART=y + CONFIG_DEBUG_UART_STM32=y Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-26serial: stm32: Add setparity supportPatrick Delaunay2-2/+51
Add possibility to update the serial parity used. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-26dm: serial: Add setparityPatrick Delaunay1-0/+16
Implements serial setparity ops to allow uart parity change. It allows to select ODD, EVEN or NONE parity. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-26serial: stm32: Fix bits defines namePatrice Chotard2-10/+10
Rename USART_ISR_FLAG_xxx bits to USART_ISR_xxx bits and USART_ICR_OREF to USART_ICR_ORECF in order to match datasheets. Sort defines by descendant order. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-26serial: stm32: Add debug uart supportPatrick Delaunay2-22/+92
Add support for early debug printf, before the availability of driver model and device tree support. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-26ram: stm32_sdram: Adds stm32f429-disco fixes for HardFault at bootingRadoslaw Pietrzyk3-16/+29
- adds reading FMC swap setting from DTB to SDRAM driver - sets FMC swap for stm32f429-disco board - changes ram start address to 0x90000000 Signed-off-by: Radoslaw Pietrzyk <radoslaw.pietrzyk@gmail.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-26serial: serial_msm: added pinmux & configRamon Fried1-6/+18
Serial port configuration was missing from previous implementation. It only worked because it was preconfigured by LK. This patch configures the uart for 115200 8N1. It also configures the pin mux for uart pins using DT bindings. Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
2018-05-26db410: added pinctrl node and serial bindingsRamon Fried1-0/+14
Added TLMM pinctrl node for pin muxing & config. Additionally, added a serial node for uart. Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
2018-05-26mach-snapdragon: Introduce pinctrl driverRamon Fried6-0/+249
This patch adds pinmux and pinctrl driver for TLMM subsystem in snapdragon chipsets. Currently, supporting only 8016, but implementation is generic and 8096 can be added easily. Driver is using the generic dt-bindings and doesn't introduce any new bindings (yet). Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-26mach-snapdragon: Fix UART clock flowRamon Fried5-12/+43
UART clock enabling flow was wrong. Changed the flow according to downstream implementation in LK. Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
2018-05-26serial: serial_msm: initialize uart only before relocationRamon Fried1-0/+4
The uart is already initialized prior to relocation, reinitialization after relocation is unnecessary. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-26serial: serial_msm: fail probe if settings clocks failsRamon Fried1-2/+4
Failure to set the clocks will causes data abort exception when trying to write to AHB uart registers. This patch ensures that we don't touch these registers if clock setting failed. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-26db820c: set clk node to be probed before relocationRamon Fried1-0/+14
The clock and serial nodes are needed before relocation. This patch ensures that the msm-serial driver will probe and provide uart output before relocation. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-26Remove CONFIG_MVGBE from config_whitelist.txtChris Packham1-1/+0
Now that there are more boards defining this it can be removed from the whitelist. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-26PCI: Document pciauto_region_allocate()Tuomas Tynkkynen1-0/+13
Add a doc comment for pciauto_region_allocate(). Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-26PCI: autoconfig: Don't allocate 64-bit addresses to 32-bit only resourcesTuomas Tynkkynen4-6/+14
Currently, if we happen to allocate an address requiring 64 bits to a device only supporting 32-bit BARs, the address eventually gets silently truncated to 32 bits. Avoid this by adding a new flag to pciauto_region_allocate() to bail out in such situations. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-26PCI: Add newlines to debug prints in pci_auto_common.cTuomas Tynkkynen1-2/+2
All of the debug output from this file is squished to one line. Fix it. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-26doc: qemu-arm: Drop highmem=off referencesTuomas Tynkkynen1-4/+3
Now that U-Boot works fine with highmem enabled, there is no need to tell users to disable highmem. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-26ARM: qemu-arm: Bump RAM size in AArch64 MMU tableTuomas Tynkkynen1-1/+1
Now that PCI devices work with highmem-enabled QEMU emulation, bump up the RAM size in the MMU tables to gain access to the full 255 GB of RAM potential instead of the puny 3 GB. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-26PCI: dm: Ignore 64-bit memory regions if CONFIG_SYS_PCI_64BIT not setTuomas Tynkkynen1-0/+7
Currently, qemu_arm_defconfig and qemu_arm64_defconfig only work with the 'highmem=off' parameter passed to QEMU's virt machine. The reason is that when 'highmem' is not disabled, QEMU appends 64-bit a memory resource to the PCI controller's regions property in DT in addition to the 32-bit PCI memory window in low memory. And the current DT parsing code picks the last (thus the 64-bit one) memory resource, whose address eventually gets silently truncated to 32 bits because CONFIG_SYS_PCI_64BIT is not set, which obviously causes PCI to break. Avoid this problem by ignoring memory regions whose addresses are above the 32-bit boundary when CONFIG_SYS_PCI_64BIT is not set. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-25configs: add TPMv2.x support in SandboxMiquel Raynal5-0/+5
Enable the Sandbox TPMv2 driver in all possible configurations. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-05-25sandbox: dts: add Sandbox TPMv2.x nodeMiquel Raynal3-0/+12
This node declares the presence of the Sandbox TPMv2.x emulated chip, available for testing. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-05-25doc: device-tree-bindings: add Sandbox TPMv2.0 module infoMiquel Raynal1-0/+11
Add Sandbox TPMv2.0 module bindings. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-05-25tpm: add a Sandbox TPMv2.x driverMiquel Raynal3-1/+636
This driver can emulate all the basic functionalities of a TPMv2.x chip and should behave like them during regular testing. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-05-25test/py: add TPMv2.x test suiteMiquel Raynal1-0/+233
Add tests for the TPMv2.x commands. These commands may run both on a physical TPM and with the sandbox driver. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-05-25doc: device-tree-bindings: add TIS TPMv2.0 SPI module infoMiquel Raynal1-0/+18
Add TIS TPMv2.0 SPI module bindings. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-05-25tpm2: tis_spi: add the possibility to reset the chip with a gpioMiquel Raynal1-0/+16
On some designs, the reset line could not be connected to the SoC reset line, in this case, request the GPIO and ensure the chip gets reset. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-25tpm: add support for TPMv2.x SPI modulesMiquel Raynal3-0/+675
Add the tpm2_tis_spi driver that should support any TPMv2 compliant (SPI) module. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-25tpm: add PCR authentication commands supportMiquel Raynal3-0/+177
Add support for the TPM2_PCR_SetAuthPolicy and TPM2_PCR_SetAuthValue commands. Change the command file and the help accordingly. Note: These commands could not be tested because the TPMs available do not support them, however they could be useful for someone else. The user is warned by the command help. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-05-25tpm: add TPM2_HierarchyChangeAuth command supportMiquel Raynal3-12/+105
Add support for the TPM2_HierarchyChangeAuth command. Change the command file and the help accordingly. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-05-25tpm: add dictionary attack mitigation commands supportMiquel Raynal3-0/+175
Add support for the TPM2_DictionaryAttackParameters and TPM2_DictionaryAttackLockReset commands. Change the command file and the help accordingly. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-05-25tpm: add TPM2_GetCapability command supportMiquel Raynal3-0/+92
Add support for the TPM2_GetCapability command. Change the command file and the help accordingly. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-05-25tpm: add TPM2_PCR_Read command supportMiquel Raynal3-0/+98
Add support for the TPM2_PCR_Read command. Change the command file and the help accordingly. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
generated by cgit v1.1 at 2024-09-07 02:30:31 +0000