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2020-10-21arm: stm32: cleanup arch gpio.hPatrick Delaunay3-70/+6
Cosmetic update of gpio.h: - remove enumerate: stm32_gpio_port, stm32_gpio_pin because STM32_GPIO_XXX values are unused - move STM32_GPIOS_PER_BANK in stm32_gpio.c as its value is IP dependent and not arch dependent No functional change as number of banks and number of gpio by banks is managed by device tree since since DM migration and commit 8f651ca60ba1 ("pinctrl: stm32: Add get_pins_count() ops"). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-21ARM: dts: stm32: Do not set eth1addr if KS8851 has EEPROMMarek Vasut1-4/+36
In case the KS8851 has external EEPROM attached to it, do not set eth1addr at all. The network stack will read the MAC out of the KS8851 and set eth1addr accordingly. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-10-21stm32mp: limit size of cacheable DDR in pre-reloc stagePatrick Delaunay3-2/+17
In pre-reloc stage, U-Boot marks cacheable the DDR limited by the new config CONFIG_DDR_CACHEABLE_SIZE. This patch allows to avoid any speculative access to DDR protected by firewall and used by OP-TEE; the "no-map" reserved memory node in DT are assumed after this limit: STM32_DDR_BASE + DDR_CACHEABLE_SIZE. Without security, in basic boot, the value is equal to STM32_DDR_SIZE. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-21mmc: stm32_sdmmc2: Use mmc_of_parse() to read host capabilitiesAlexandru Gagniuc1-16/+2
mmc_of_parse() can populate the 'f_max' and 'host_caps' fields of struct mmc_config from devicetree. The same logic is duplicated in stm32_sdmmc2_probe(). Use mmc_of_parse(), which is more generic. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2020-10-21mmc: mmc_of_parse: Enable 52 MHz support with "cap-mmc-highspeed"Alexandru Gagniuc1-1/+1
"cap-mmc-highspeed" enables support for 26 MHz MMC, but there is no additional flag to enable 52 MHz MMC. In Linux. "cap-mmc-highspeed" is used for MMC HS at both 26MHz and 52MHz. Use the same approach and enable MMC_CAP(MMC_HS_52) host capability when "cap-mmc-highspeed" is found in the devicetree. In the event an MMC card doesn't support 52 MHz, it will be clocked at a speed based on its EXT CSD, even on 52 MHz host controllers Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Tested-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-19Merge tag 'u-boot-atmel-2021.01-b' of ↵Tom Rini14-206/+729
https://gitlab.denx.de/u-boot/custodians/u-boot-atmel Second set of u-boot-atmel features for 2021.01 cycle: This feature set brings the rework of the clock tree for sam9x60 SoC. This makes the clock tree fully compatible with Common Clock Framework and allows full clock configuration in U-Boot. This means that the sam9x60 boards can boot now using U-Boot. This also includes the definitions for sam9x60 SiPs and a divisor fix for the clock on sama7g5 SoC.
2020-10-19clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristicsEugen Hristev1-2/+2
This SoC has the 5th divisor for the mck0 master clock. Adapt the characteristics accordingly. Reported-by: Mihai Sain <mihai.sain@microchip.com> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19clk: at91: clk-master: add 5th divisor for mck masterEugen Hristev2-2/+2
clk-master can have 5 divisors with a field width of 3 bits on some products. Change the mask and number of divisors accordingly. Reported-by: Mihai Sain <mihai.sain@microchip.com> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19ARM: at91: Add chip ID for SAM9X60 SiPNicolas Ferre2-0/+9
SAM9X60 SiP (System in Package) are added for SoC identification. Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2020-10-19ARM: dts: sam9x60: use alphabetical orderClaudiu Beznea1-14/+13
Use alphabetical order for entries in sam9x60ek-u-boot.dtsi Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19configs: sam9x60ek: update defconfigs for CCFClaudiu Beznea3-3/+9
Update defconfigs for using common clock framework compatible clocks. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19ARM: dts: sam9x60: use CCF compatibles for PMCClaudiu Beznea3-164/+33
Use CCF compatible for PMC. With this, the board/SoC will be able to boot. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19ARM: dts: sam9x60: use slow clock CCF compatible bindingsClaudiu Beznea2-47/+20
Use slow clock CCF compatible DT bindings. This will not break the above functionality as the SoC is not booting with current PMC bindings. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19ARM: dts: sam9x60: use u-boot,dm-pre-relocClaudiu Beznea1-0/+8
Use u-boot,dm-pre-reloc for slow xtal and main xtal. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19ARM: dts: sam9x60ek: add clock frequencies to board fileClaudiu Beznea2-2/+10
Slow Xtal and Main Xtal are board specific. Add their proper frequency to board file. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19clk: at91: sam9x60: add support compatible with CCFClaudiu Beznea2-0/+650
Add SAM9X60 clock support compatible with CCF. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-19board: atmel: sam9x60ek: add SYS_MALLOC_F_LEN to SYS_INIT_SP_ADDRClaudiu Beznea1-1/+2
Heap base address is computed based on SYS_INIT_SP_ADDR by subtracting the SYS_MALLOC_F_LEN value in board_init_f_init_reserve(). Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-18Merge tag 'video-for-2021.01' of ↵Tom Rini136-138/+283
https://gitlab.denx.de/u-boot/custodians/u-boot-video - add dw-mipi-dsi phy timings and Tx escape clock configuration - fix pwm backlight duty cycle calculation - migrate CONFIG_VIDEO_BMP_* and CONFIG_BMP_* to Kconfig
2020-10-18configs: migrate CONFIG_BMP_16/24/32BPP to defconfigsPatrick Delaunay103-63/+122
Done with: ./tools/moveconfig.py BMP_16BPP BMP_24BPP BMP_32BPP Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-18configs: migrate CONFIG_VIDEO_BMP_RLE8 to defconfigsPatrick Delaunay119-43/+88
Done with: ./tools/moveconfig.py VIDEO_BMP_RLE8 Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-18configs: migrate CONFIG_VIDEO_BMP_GZIP to defconfigsPatrick Delaunay23-14/+21
Done with: ./tools/moveconfig.py VIDEO_BMP_GZIP The 3 suspicious migration because CMD_BMP and SPLASH_SCREEN are not activated in these defconfigs: - trats_defconfig - s5pc210_universal_defconfig - trats2_defconfig Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-18video: backlight: fix pwm's duty cycle calculationDario Binacchi2-7/+7
For levels equal to the maximum value, the duty cycle must be equal to the period. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-18video: backlight: fix pwm data structure descriptionDario Binacchi1-1/+1
The description of the 'max_level' field was incorrectly assigned to the 'min_level' field. Signed-off-by: Dario Binacchi <dariobin@libero.it>
2020-10-18video: dw-mipi-dsi: permit configuring the escape clock rateNeil Armstrong2-4/+17
The Amlogic D-PHY in the Amlogic AXG SoC Family does support a frequency higher than 10MHz for the TX Escape Clock, thus make the target rate configurable. This is based on the Linux commit [1] and adapted to the U-Boot driver. [1] a328ca7e4af3 ("drm/bridge: dw-mipi-dsi: permit configuring the escape clock rate") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-10-18video: dw-mipi-dsi: driver-specific configuration of phy timingsNeil Armstrong2-6/+27
The timing values for dw-dsi are often dependent on the used display and according to Philippe Cornu will most likely also depend on the used phy technology in the soc-specific implementation. To solve this and allow specific implementations to define them as needed add a new get_timing callback to phy_ops and call this from the dphy_timing function to retrieve the necessary values for the specific mode. This is based on the Linux commit [1] and adapted to the U-Boot driver. [1] 25ed8aeb9c39 ("drm/bridge/synopsys: dsi: driver-specific configuration of phy timings") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-10-17test: Fix sandbox tests failing to buildSean Anderson2-2/+2
syslog_test.h is in test/log/, not include/ Fixes: 52d3df7fef ("log: Allow LOG_DEBUG to always enable log output") Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-16Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellTom Rini8-7/+93
- Fix Octeon SPI driver for Octeon TX2 - Fix and enhance Octeon watchdog driver - Misc minor enhancements to Octeon TX/TX2
2020-10-16Merge branch '2020-10-15-further-cleanup_dev_xxx'Tom Rini26-94/+74
- Bring in the next round of dev_xxx cleanup patches.
2020-10-16dm: Don't undefine dev_xxx macrosSean Anderson1-20/+0
Now that linux/compat.h does not define these macros, we do not need to undefine them. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-16linux/compat.h: Remove redefinition of dev_xxx macrosSean Anderson1-28/+0
All users of these functions now include dm/device_compat.h directly. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-16usb: dwc3: Include device_compat.h in dwc3-octeon-glue.cTom Rini1-0/+1
Necessary for dev_xxx. Signed-off-by: Tom Rini <trini@konsulko.com>
2020-10-16clk: at91: Include device_compat.h in compat.cTom Rini1-0/+1
Necessary for dev_xxx. Signed-off-by: Tom Rini <trini@konsulko.com>
2020-10-16arm: fsl-layerscape: Include device_compat.h in soc.cTom Rini1-0/+1
Necessary for dev_xxx. Signed-off-by: Tom Rini <trini@konsulko.com>
2020-10-16usb: musb-new: mt85xx: Fix not calling dev_err with a deviceSean Anderson1-3/+4
This driver doesn't use DM (in the correct places), so we use a device and not a udevice. We also need to include device_compat.h Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-10-16usb: musb-new: Include device_compat.hSean Anderson5-1/+11
This was included, but was ifdef'd out. We also need dm.h for struct udevice. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-10-16usb: xhci: Include device_compat.hSean Anderson2-5/+7
This header is necessary for the dev_xxx macros. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-10-16timer: Include device_compat.hSean Anderson1-2/+3
Necessary for dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-16tee: optee: Include device_compat.hSean Anderson1-0/+1
Necessary for dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-16spi: fsl_qspi: Include device_compat.hSean Anderson1-4/+5
Necessary for dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-10-16spi: nxp_fspi: Include device_compat.hSean Anderson1-3/+4
Necessary for dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-10-16arm: octeontx: Add CMD_WDTStefan Roese4-0/+4
Enable WDT command for Octeon TX/TX2 boards. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Suneel Garapati <sgarapati@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com>
2020-10-16watchdog: octeontx_wdt: Add support for start and stopSuneel Garapati1-5/+83
This patch enhances the Octeon TX/TX2 watchdog driver to fully enable the WDT. With this changes, the "wdt" command is now also supported on these platforms. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Suneel Garapati <sgarapati@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com>
2020-10-16arm: octeontx: Select CLKStefan Roese1-0/+2
Clock support is needed for all Octeon TX/TX2 boards. This patch selects CONFIG_CLK so that it is available. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Suneel Garapati <sgarapati@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com>
2020-10-16mmc: octeontx_hsmmc.c: Remove test debug messageStefan Roese1-1/+0
Remove a left-over debug test message from the Octeon TX / TX2 MMC driver. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Suneel Garapati <sgarapati@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com>
2020-10-16spi: octeon_spi: Use a fixed 100MHz input clock on Octeon TX2Stefan Roese1-1/+4
Octeon TX2 sets the TB100_EN bit in the config register. We need to use a fixed 100MHz clock for this as well to work properly. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Suneel Garapati <sgarapati@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Jagan Teki <jagan@amarulasolutions.com>
2020-10-15ram: imxrt: Include device_compat.hSean Anderson1-0/+1
Necessary for dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-10-15phy: Include device_compat.hSean Anderson1-1/+1
Necessary for dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-10-15net: ldpaa_eth: Include device_compat.hSean Anderson1-7/+7
Necessary for dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-10-15mtd: mxs_nand: Fix not calling dev_xxx with a deviceSean Anderson1-13/+15
This includes device_compat.h, and fixes several calls to dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-10-15firmware: scmi: Include device_compat.hSean Anderson3-0/+3
This header is necessary for the dev_xxx macros. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-10-08 14:11:45 +0000