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2023-08-18Merge branch '2023-08-18-assorted-updates' into nextTom Rini17-16/+225
- Use built-in ffs/fls on ARM, fix a PIE issue in SPL on ARMv8, bcm283x and mediatek updates, whitespace fix in UFS uclass, make CI use "tools-only" defconfig for more tests, add TI TCA9554 GPIO support, cache alignment fix for SCSI, and fix a problem with SYS_MMCSD_RAW_MODE_ARGS_SECTOR in SPL.
2023-08-17CI: Switch to tools-only from sandbox_spl for tooling testsWIP/2023-08-17-assorted-updatesTom Rini2-8/+8
When running tools for various tests use the tools-only build rather than sandbox_spl. We used sandbox_spl here for historical reasons that are no longer true. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-17spl: mmc: Fix check of CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORElena Popa1-1/+1
When Falcon Mode is enabled, SPL needs to check the value of CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR. Unfortunately, it was using the CONFIG_VAL(SYS_MMCSD_RAW_MODE_ARGS_SECTOR) which converts it into CONFIG_SPL_SYS_MMCSD_RAW_MODE_ARGS_SECTOR when CONFIG_SPL_BUILD is enabled. CONFIG_SPL_SYS_MMCSD_RAW_MODE_ARGS_SECTOR does not exist in common/spl/Kconfig. Replaced with defined(CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR). Signed-off-by: Elena Popa <elena.popa@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2023-08-17scsi: Cache align temporary bufferMarek Vasut1-2/+3
The temporary buffer may be passed to DMA capable device, make sure it is cache aligned. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-08-17gpio: pca953x: Add TI TCA9554 supportMarek Vasut1-0/+1
Add support for TI TCA9554, which is compatible with PCA9554 . Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-08-17ufs: cdns: Drop extra spaceMarek Vasut1-1/+1
Drop extra space before UCLASS. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-08-17arm: mediatek: add usb support for MT7988Frank Wunderlich1-0/+60
MT7988 has a t-phy and an x-phy controller. There is already a driver for t-phy so we can add USB support for this phy type. Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2023-08-17arm: dts: mediatek: convert gmac link mode to 2500base-x for r3Frank Wunderlich1-2/+2
Ethernet on Bananapi-r3 is broken after commit bd70f3cea353 ("net: mediatek: add support for SGMII 1Gbps auto-negotiation mode") because changes from this commit were not applied to bpi-r3 devicetree too: commit aef54ea16cac ("arm: dts: medaitek: convert gmac link mode to 2500base-x") Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
2023-08-17arm: bcm283x undefined reference to "print_cpuinfo"Naveen Kumar Chaudhary1-0/+8
Builds for Raspberry Pi targets fail when CONFIG_DISPLAY_CPUINFO is enabled and following error can be seen - common/board_f.o:(.rodata.init_sequence_f+0x90): undefined reference to `print_cpuinfo' Added implementation of function "print_cpuinfo" Signed-off-by: Naveen Kumar Chaudhary <naveenchaudhary2010@hotmail.com>
2023-08-17armv8: Skip PIE in SPL due to load alignment fault.Kevin Chen1-1/+1
When PIE is enabled in start.S, u-boot/-spl use __rel_dyn_start and _rel_dyn_end symbol to be loaded to and executed at a different address than it was linked at. u-boot-spl.lds is used in SPL build, but relocation information section(.rela*) were discarded. In line number 80 in arch/arm/cpu/armv8/u-boot-spl.lds /DISCARD/ : { *(.rela*) } If PIE enabled in SPL, __rel_dyn_start which is defined as .rel_dyn_start in sections.c will be apended to the end of .bss section. In our ASPEED case, size of .bss section would let .rel_dyn_start without 8-byte alignment, leading to alignment fault when executing ldp instuction in pie_fix_loop. Signed-off-by: Kevin Chen <kevin_chen@aspeedtech.com>
2023-08-17arm: Use builtins for ffs/flsSean Anderson7-1/+140
Since ARMv5, the clz instruction allows for efficient implementation of ffs/fls with builtins. Until ARMv7 (with Thumb-2), this instruction is only available in ARM mode. LTO makes it difficult to force specific functions to be in ARM mode, as it is effectively a form of very aggressive inlining. To work around this, fls/ffs are implemented in assembly for ARMv5 and ARMv6 when compiling U-Boot in Thumb mode. Overall, this saves around 75 bytes per call. This code is synced with v5.15 of the Linux kernel. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2023-08-17Merge branch '2023-08-17-ti-k3-am64-dt-resync' into nextTom Rini15-635/+2506
To quote the author: This series syncs AM64 DT files from Linux v6.5-rc1. Tested on AM642-EVM GP SR1.0 and AM642-SK-EVM HS-FS SR2.0.
2023-08-17arm: dts: k3-am64: Sync DT with Linux v6.5-rc1Roger Quadros11-573/+604
Sync all am642-evm/am642-sk related DT files with Linux v6.5-rc1. - drop timer1 in favor of main_timer0 in am64-main.dtsi. Need to delete clock & power domain properties of main_timer1 in -r5.dts else won't boot. This is because timer_init is done during rproc_start to start System Firmware, but we can't do any clock/power-domain operations before System Firmware starts. - same constraint applies to main_uart0 - drop cpsw3g custom DT property 'mac_efuse' and custom DT node cpsw-phy-sel as driver picks these from standard property/node. - include board dts file in -r5 dts file to avoid duplication of nodes. Include -u-boot.dtsi on top. - drop duplicate nodes in -r5 dts and -u-boot.dtsi Signed-off-by: Roger Quadros <rogerq@kernel.org> Tested-by: Nishanth Menon <nm@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com>
2023-08-17doc: board: ti: am64: Add boot flow diagramRoger Quadros3-0/+1900
Add documenatation and boot flow diagram for AM64 EVM/SoC. Suggested-by: Nishanth Menon <nm@ti.com> Signed-off-by: Roger Quadros <rogerq@kernel.org> Reviewed-by: Nishanth Menon <nm@ti.com> Tested-by: Nishanth Menon <nm@ti.com> #SK-AM64B
2023-08-17Revert "ARM: dts: k3-am642-sk-u-boot: add PMIC node"Roger Quadros1-61/+0
This reverts commit 28a4c3113445d4400639f357fae0def007a41093. This node should be in the board DT file and should come from upstream. Moreover, this PMIC is no present on all variants of am642-sk and will need a separate board DT file. Signed-off-by: Roger Quadros <rogerq@kernel.org> Reviewed-by: Nishanth Menon <nm@ti.com> Tested-by: Nishanth Menon <nm@ti.com> #SK-AM64B
2023-08-17board: ti: am64x: Recognize AM64-HSEVMRoger Quadros1-1/+2
AM64-HSEVM is AM64-GPEVM with High Security Device. Gets rid of "Unidentified board claims AM64-HSEVM in eeprom header". Signed-off-by: Roger Quadros <rogerq@kernel.org> Acked-by: Andrew Davis <afd@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Tested-by: Nishanth Menon <nm@ti.com> #SK-AM64B
2023-08-15Merge branch '2023-08-15-add-SGMII-support-for-TI-j7200' into nextTom Rini4-10/+91
To quote the author: This series adds support for SGMII mode to the CPSW driver to enable the functionality on TI's J7200 SoC. Supporting SGMII mode also requires changes to the WIZ driver which acts as a wrapper for the SerDes used by the CPSW MAC to transmit data to the Ethernet PHY daughtercard mounted on the I2C GPIO Expander 2 connector on the J7200 EVM. Powering on and resetting the Ethernet PHY requires MDIO support which is added to the CPSW driver. For supporting DMA transactions from the MAIN CPSW instance to the A72 Host on J7200 SoC, the corresponding PSI-L endpoint information is added for the J721E SoC, which is applicable to J7200 SoC as well. The SGMII daughtercard used for testing SGMII mode has TI's DP83869 PHY. Thus, enable the config for DP83869 driver functionality. Also, enable GPIO HOG config.
2023-08-15configs: j7200_evm_a72: Enable configs for SGMII support with MAIN CPSW0Siddharth Vadapalli1-0/+2
The MAIN CPSW0 instance of CPSW Ethernet Switch on TI's J7200 SoC supports SGMII mode. To enable support for utilizing the SGMII daughtercard with TI's DP83869 PHY, enable the corresponding config. Also, since the SGMII daughtercard is connected to the I2C GPIO Expander 2 connector on the J7200 EVM, powering on the Ethernet PHY and resetting it requires GPIO Hogging capability. Enable it as well. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
2023-08-15phy: ti: j721e-wiz: Add SGMII support in WIZ driver for J721ESiddharth Vadapalli1-0/+2
Enable full rate divider configuration support for J721E_WIZ_16G for SGMII. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
2023-08-15phy: ti: phy-j721e-wiz: Add SGMII support in wiz driver for J7200Siddharth Vadapalli1-6/+13
Select the same mac divider for SGMII too as the one being used for QSGMII. Enable full rate divider configuration support for J721E_WIZ_10G for SGMII. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
2023-08-15net: ti: am65-cpsw-nuss: Add logic to support MDIO resetSuman Anna1-1/+37
Enhance the AM65 CPSW NUSS driver to perform a MDIO reset using a GPIO line. Logic is also added to perform a pre and post delay around reset using the optional 'reset-delay-us' and 'reset-post-delay-us' properties. This is similar to the reset being performed in the Linux kernel. The reset is done once when the CPSW MDIO bus is being initialized. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
2023-08-15net: ti: am65-cpsw-nuss: Add support for SGMII modeSiddharth Vadapalli1-0/+23
Add support for configuring the CPSW Ethernet Switch in SGMII mode. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
2023-08-15dma: ti: Update J21E PSIL endpoint information for MAIN CPSW0Suman Anna1-3/+14
The PSIL endpoint data for J721E currently covers only the MCU domain CPSW0 instance. Add the data for the MAIN domain CPSW0 as well to allow the MAIN domain Ethernet ports to be usable on any platform using J721E SoC. Additionally, since J721E's PSIL endpoint data is applicable to J7200 SoC as well, the MAIN CPSW0 instance on J7200 will also be usable now. Signed-off-by: Suman Anna <s-anna@ti.com> [s-vadapalli@ti.com: Update commit message indicating support for J7200] Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
2023-08-15Merge branch '2023-08-14-assorted-general-updates' into nextTom Rini19-13/+329
- Assorted PCI-related fixes, add Apple Type-C PHY support, semihosting updates, fix a FAT corner-case, update the help on the pxe cmd and clean up the gpio uclass slightly.
2023-08-14Merge tag 'dm-next-14aug23' of ↵WIP/14Aug2023-nextTom Rini13-107/+845
https://source.denx.de/u-boot/custodians/u-boot-dm into next Enhance bootmeth_cros
2023-08-14gpio: Use separate bitfield array to indicate GPIO is claimedWIP/2023-08-14-assorted-general-uupdatesMarek Vasut2-5/+61
The current gpio-uclass design uses name field in struct gpio_dev_priv as an indicator that GPIO is claimed by consumer. This overloads the function of name field and does not work well for named pins not configured as GPIO pins. Introduce separate bitfield array as the claim indicator. This unbreaks dual-purpose AF and GPIO operation on STM32MP since commit 2c38f7c31806 ("pinctrl: pinctrl_stm32: Populate uc_priv->name[] with pinmux node's name") where any pin which has already been configured as AF could no longer be claimed as dual-purpose GPIO. This is important for pins like STM32 MMCI st,cmd-gpios . Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-14test: unit test for semihostingHeinrich Schuchardt2-0/+56
Provide a unit test for semihosting testing reading and writing a file. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Sean Anderson <sean.anderson@seco.com>
2023-08-14configs: enable SEMIHOSTING on qemu_arm64_defconfigHeinrich Schuchardt1-0/+1
We need a platform on which we can test our semihosting code. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Sean Anderson <sean.anderson@seco.com>
2023-08-14cmd: pxe: Update the command helpBin Meng1-2/+1
Currently the "help" displays pxe command help text like this: => help ... printenv - print environment variables pxe - commands to get and boot from pxe files To use IPv6 add -ipv6 parameter qfw - QEMU firmware interface ... This does not read clearly. Remove the IPv6 stuff as it is in the detailed help text so that it fits just a single line. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-14pci: ftpci100: add new driver implementationSergei Antonov4-0/+103
Add a new DM driver supporting FTPCI100 IP used in SoC designs. This implementation is not based on the old non-DM ftpci100 code dropped from U-Boot. Enable the driver in sandbox_defconfig to test compilability. Signed-off-by: Sergei Antonov <saproj@gmail.com>
2023-08-14fs: fat: avoid multiplication overflowHeinrich Schuchardt1-2/+2
The product of two 32 bit integers is a 32 bit integer. Hence clustcount * bytesperclust may overflow on > 4 GiB devices. Change the type of clustcount. Fixes: cb8af8af5ba0 ("fs: fat: support write with non-zero offset") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-08-14spl: add FIT support to semihosting boot methodHeinrich Schuchardt1-0/+31
Allow loading a FIT image via semihosting in SPL. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-08-14pci: Fix device_find_first_child() return value handlingMarek Vasut1-4/+3
This function only ever returns 0, but may not assign the second parameter. Same thing for device_find_next_child(). Do not assign ret to stop proliferation of this misuse. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-14phy: Add support for the Apple Type-C PHYMark Kettenis6-0/+70
This is merely a dummy driver that makes sure the DWC3 XHCI driver finds its reset and PHY controllers. We rely on iBoot to set up the PHY for us. Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
2023-08-14pci: apple: Enable CONFIG_SYS_PCI_64BITMark Kettenis1-0/+1
The Apple hardware supports 64-bit prefetchable memory windows so enable CONFIG_SYS_PCI_64BIT. This fixes BAR assignments for the Broadcom Ethernet controller used in some of the desktop machines. Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
2023-08-14Merge branch '2023-08-14-keep-fixed-gpio-regulator-count-in-balance' into nextTom Rini5-36/+37
To quote the author: The commit 4fcba5d556b4 ("regulator: implement basic reference counter") have made it more important to keep fixed/gpio regulators enable/disable state in balance. This series fixes an inbalance in the mmc_dw driver and changes to use the more relaxed regulator_set_enable_if_allowed function for a few other drivers. The regulator_set_enable_if_allowed function is more relaxed and will return ENOSYS if the provided regulator is NULL or when DM_REGULATOR was disabled. Using the following call convention should be safe: ret = regulator_set_enable_if_allowed(<supply>, <true|false>); if (ret && ret != -ENOSYS) return ret;
2023-08-14mmc: dw_mmc: Keep vqmmc-supply enable count in balanceJonas Karlman1-0/+4
With the commit 4fcba5d556b4 ("regulator: implement basic reference counter"), keeping regulator enablement in balance become more important. Disable vqmmc-supply before signal voltage is changed to keep regulator enable counter in balance. Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
2023-08-14mmc: Use regulator_set_enable_if_allowedJonas Karlman1-4/+6
With the commit 4fcba5d556b4 ("regulator: implement basic reference counter") the return value of regulator_set_enable may be EALREADY or EBUSY for fixed/gpio regulators. Change to use the more relaxed regulator_set_enable_if_allowed to continue if regulator already was enabled or disabled. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # P895 Tegra 3; Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> # rockpro64-rk3399
2023-08-14usb: ehci-generic: Use regulator_set_enable_if_allowedJonas Karlman1-12/+11
With the commit 4fcba5d556b4 ("regulator: implement basic reference counter") the return value of regulator_set_enable may be EALREADY or EBUSY for fixed/gpio regulators. Change to use the more relaxed regulator_set_enable_if_allowed to continue if regulator already was enabled or disabled. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Marek Vasut <marex@denx.de>
2023-08-14usb: dwc2: Use regulator_set_enable_if_allowedJonas Karlman1-8/+6
With the commit 4fcba5d556b4 ("regulator: implement basic reference counter") the return value of regulator_set_enable may be EALREADY or EBUSY for fixed/gpio regulators. Change to use the more relaxed regulator_set_enable_if_allowed to continue if regulator already was enabled or disabled. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> # rockpro64-rk3399 Reviewed-by: Marek Vasut <marex@denx.de>
2023-08-14adc: Use regulator_set_enable_if_allowedJonas Karlman1-12/+10
With the commit 4fcba5d556b4 ("regulator: implement basic reference counter") the return value of regulator_set_enable may be EALREADY or EBUSY for fixed/gpio regulators. Change to use the more relaxed regulator_set_enable_if_allowed to continue if regulator already was enabled or disabled. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> # rockpro64-rk3399
2023-08-11bootstd: cros: Add ARM supportSimon Glass4-8/+57
Support booting ChromiumOS on ARM devices using FIT. Add an entry into the boot implementation which does not require a command line. This can be expanded over time as the bootm code is refactored. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-08-11bootstd: Add a command to read all files for a bootflowSimon Glass7-4/+195
Some bootflows (such as EFI and ChromiumOS) delay reading the kernel until it is needed to boot. This saves time when scanning and avoids needing to allocate memory for something that may never be used. To permit reading of these files, add a new 'bootflow read' command. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-08-10bootstd: Allow display of the x86 setup informationSimon Glass6-18/+86
Provide an option to dump this information if available. Move the funciion prototype to the common x86 header. Allow the command line to be left out since 'bootflow info' show this itself and it is not in the correct place in memory until the kernel is actually booted. Fix a badly aligned heading while we are here. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-08-10bootstd: cros: Split up reading info and kernelSimon Glass1-73/+23
Use the two new functions to separate reading of the ChromiumOS info from the partition from actually reading the kernel and booting it. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-08-10bootstd: cros: Add a function to read a kernelSimon Glass1-0/+39
The code to read the ChromiumOS information from the partition is currently all in one function. Create a new function which reads the kernel, assuming that the metadata has been parsed. For now this function is not used. Future work will plumb it in. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-08-10bootstd: cros: Add a function to read info from partitionSimon Glass1-0/+121
The code to read the ChromiumOS information from the partition is currently all in one function. It reads the entire kernel, which is unnecessary unless it is to be booted. Create a new function which reads just the minimum required data from the disk, then obtains what it needs from there. For now this function is not used. Future work will plumb it in. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-08-10bootstd: Add private bootmeth data to the bootflowSimon Glass2-0/+3
Some bootmeths need to store their own information related to the bootflow, in addition to the generic information in struct bootflow. Add a pointer for this. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-08-10bootstd: cros: Add private info for ChromiumOSSimon Glass1-13/+42
Create a new private structure to hold information gleaned from the disk. This will allow separation between reading of the bootflow information and (later) reading the whole kernel. Signed-off-by: Simon Glass <sjg@chromium.org>
2023-08-10bootstd: cros: Add docs for the kernel layoutSimon Glass1-0/+29
Provide brief documentation about the ChromiumOS kernel layout. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-09-06 16:44:05 +0000