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2012-12-06x86: Add function to read time stamp counterVadim Bendebury2-0/+29
Put this function in the u-boot-x86.h header file. We could instead create timer.h perhaps. We support setting a base time, and reading the time relative to this base. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06x86: gpio: Add additional GPIO banks to the ICH6 driverBill Richardson1-62/+110
We can generally trust the ICH to have GPIO Bank 0 (the first 32 pins) in the same place across all versions. This change adds two more banks, for up to 96 GPIOS. BUT: - Not all chipsets have the same number of GPIOs - Not all chipsets have the same number of GPIO banks - Not all chipsets put the additional banks at the same offset from GPIOBASE - There so many chipset variants that it's pretty much impossible to support them all, or even keep track of the new ones. So, although this adds suppport for the additional banks that seem to work for the particular variants of CougarPoint Mobile chipsets that we've tried, there's no chance it will support everything Intel produces. Good luck. Signed-off-by: Bill Richardson <wfrichar@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06x86: Enable ICH6 GPIO controller for corebootSimon Glass1-0/+4
Coreboot uses this controller to implement GPIO access. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06x86: gpio: Add GPIO driver for Intel ICH6 and later.Bill Richardson4-0/+393
Implement <asm-generic/gpio.h> functions for Intel ICH6 and later. Only GPIOs 0-31 are handled by this code. Signed-off-by: Bill Richardson <wfrichar@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-064xx: Fix PCI memory mapping on CPCI405 boardsMatthias Fuchs4-4/+4
This patch fixes an issue with overlapping PCI regions on boards with more than 64MB RAM. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
2012-12-05Makefile: Add target for combined spl/u-boot.bin & u-boot.imgStefan Roese1-0/+3
This new make target "u-boot-img.bin" consists of the U-Boot SPL image with the real, full-blown U-Boot image directly attached to it. The full-blown U-Boot image has the mkimage header included, with its load-address and entry-point. This will be used by the upcoming a3m071 MPC5200 board port. Signed-off-by: Stefan Roese <sr@denx.de>
2012-12-05Makefile: Add possibility to set entry-point for u-boot.imgStefan Roese1-1/+10
This patch enabled boards using the SPL framework to set an entry point in the U-Boot mkimage image "u-boot.img". Until now the entry point in the header has been set to 0. By setting CONFIG_SYS_UBOOT_START in the board header, boards can override this default location. This will be used by the upcoming a3m071 MPC5200 board port. Signed-off-by: Stefan Roese <sr@denx.de>
2012-12-05mpc5200: Add a3m071 board supportStefan Roese7-0/+866
This patch adds support for the a3m071 board based on the MPC5200. Signed-off-by: Stefan Roese <sr@denx.de>
2012-12-05mpc5200: Add SPL supportStefan Roese6-0/+201
This patch adds SPL booting support (NOR flash) for the MPC5200 platforms. Signed-off-by: Stefan Roese <sr@denx.de>
2012-12-05env: Enable getenv_f() for SPL_BUILDStefan Roese1-0/+3
With this patch, getenv_f() can be included easily into the SPL binary. With this, SPL boards can now use getenv_f() to read environment variables (e.g. to detect if the OS or U-Boot shall be executed). In the approach this is done for env stored in NOR flash, as this will be used by an upcoming MPC5200 board port. Signed-off-by: Stefan Roese <sr@denx.de>
2012-12-05SPL: Port SPL framework to powerpcStefan Roese3-0/+62
This patch enables the SPL framework to be used on powerpc platforms and not only ARM. timer_init() does not exist on PPC systems. The timer (decrementer) is initialized and enabled in interrupt_init() here. And currently interrupt_init() is called after relocation to SDRAM. Since the only powerpc SPL implementation (a3m071) doesn't need a timer, let's remove this timer_init() call for PPC systems. Signed-off-by: Stefan Roese <sr@denx.de>
2012-12-05powerpc: Extract EPAPR_MAGIC constants into processor.hStefan Roese3-7/+6
By extracting these defines into a header, they can be re-used by other C sources as well. This will be done by the SPL framework OS boot support. Signed-off-by: Stefan Roese <sr@denx.de>
2012-12-03Merge branch 'master' of git://git.denx.de/u-boot-x86Tom Rini26-112/+460
2012-11-30x86: Don't spam POST80 codes with slow IO functionsStefan Reinauer1-1/+1
This patch prevents u-boot from "spamming" random progress codes on a port 80 "post card". The previous version of this patch just removed the delays in the "slow" IO functions, as they do not need to be slow, however, this patch is less intrusive. It uses another unused port that is often used by BIOSes (and the Linux Kernel) for small delay timing purposes. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30x86: Define CONFIG_SYS_VSNPRINTF for corebootSimon Glass1-0/+1
This option protects the printf() functions from overflow. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30x86: Fix typo in pcat_timer.cStefan Reinauer1-1/+1
Fix a small comment typo. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30x86: Include types.h explicitly in the i386 version of io.hGabe Black1-0/+2
The i386 version of io.h depends on the phys_addr_t type which is defined in types.h. It wasn't including that explicitly, and was working presumably because the other files including it had already included types.h themselves directly or indirectly. This change fixes that. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30x86: Add a dummy implementation for timer_get_usGabe Black2-1/+18
The microsecond timer is not currently implemented, but add a dummy implementation for now. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30x86: Add a default implementation for cleanup_before_linux()Gabe Black2-0/+6
This function provides an opportunity for some last minute cleanup and reconfiguration before control is handed over to Linux. It's possible this may need to do something in the future, but for now it's left empty. It's set up as a weak symbol so it can be overridden if necessary on a case by case basis. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30x86: Add a minimal device tree for alex x86Gabe Black1-0/+30
The device tree now includes the necessary console configuration information. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30x86: Add an fdt pointer to the global data structureGabe Black1-0/+1
This change adds a pointer to the global data structure in x86 to point to the device tree. This mirrors an identical pointer in ARM. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30x86: video: Add coreboot framebuffer supportStefan Reinauer2-0/+102
Add a basic driver for the coreboot framebuffer. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30x86: Remove coreboot start16 codeSimon Glass2-34/+0
This file is no longer needed for coreboot. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30x86: Allow compiling out realmode/bios codeGabe Black4-5/+16
We don't want this for coreboot, so provide a way of compiling it out. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30x86: Select stdio devices for corebootSimon Glass1-0/+12
We want to support VGA, serial, USB keyboard and the Coreboot memory console buffer. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30x86: Add console command to display CBMEM console bufferVadim Bendebury1-0/+67
This command is useful to allow to observe messages generated by coreboot and u-boot until present. In particular it is handy when u-boot is instrumented to fall through into console mode on startup errors. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30x86: Add CBMEM console driver for corebootVadim Bendebury3-1/+7
This patch builds upon the recently introduced CBMEM console feature of coreboot. CBMEM console uses a memry area allocated by coreboot to store the console output. The memory area has a certain structure, which allows to determine where the buffer is, the buffer size and the location of the pointer in the buffer. This allows different phases of the firmware (rom based coreboot, ram based coreboot, u-boot after relocation with this change) to keep adding text to the same buffer. Note that this patch introduces a new console driver and adds the driver to the list of drivers to be used for console output, i.e. it engages only after u-boot relocates. Usiong CBMEM console for capturing the pre-relocation console output will be done under a separate change. >From Linux, run the cbmem.py utility (which is a part of the coreboot package) to see the output, e.g.: vvvvvvvvvvvvvvvvv SCSI: AHCI 0001.0300 32 slots 6 ports ? Gbps 0xf impl SATA mode flags: 64bit ilck stag led pmp pio ... Magic signature found Kernel command line: "cros_secure quiet loglevel=1 console=tty2... ^^^^^^^^^^^^^^^^^ Note that the entire u-boot output fits into the buffer only if the coreboot log level is reduced from the most verbose. Ether the buffer size will have to be increased, or the coreboot verbosity permanently reduced. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30x86: coreboot: Decode additional coreboot sysinfo tagsSimon Glass3-29/+188
Add support for decoding tags for GPIOs, compile/build info, cbmem and other features. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30x86: coreboot: Drop sysinfo.cStefan Reinauer3-40/+8
sysinfo.c only contains the lib_sysinfo data structure which is used/filled by tables.c. This split was introduced by importing code from libpayload originally, but to keep the code simple, add the single line of actual code to tables.c Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-30Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini2-8/+14
2012-11-30include/linux/byteorder: Always defines __fswab64, __swab64p and __swab64sNobuhiro Iwamatsu1-2/+0
When __BYTEORDER_HAS_U64__ is not defined, we got warning following: ----- /tmp/include/linux/byteorder/little_endian.h: In function ‘__cpu_to_be64p’: /tmp/include/linux/byteorder/little_endian.h:71:2: warning: implicit declaration of function ‘__swab64p’ [-Wimplicit-function-declaration] ----- Usually, __arch__swab64* required for __fswab64, __swab64p and __swab64s is defined. Therefore, __BYTEORDER_HAS_U64__ is unnecessary. This removes __BYTEORDER_HAS_U64__. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> CC: Kim Phillips <kim.phillips@freescale.com> Reviewed-by: Kim Phillips <kim.phillips@freescale.com>
2012-11-30serial: serial_sh: bugfix: autoboot fails if serial console is not connectedTetsuyuki Kobayashi1-7/+13
On kzm9g board (rmobile SoC), autoboot fails if serial console cable is not connected. When serial cable is not connected, serial error occurs and some garbage comes in data register. sh_serial_tstc() in serial_sh.c does not check error status and misunderstand there is some input data. It is the reason that autoboot fails. This patch adds checking error status in sh_serial_tstc(). This patch is based on v2013.01-rc1 tag of u-boot master git. Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-11-30sh: fix trigger_address_error()Yoshihiro Shimoda1-1/+1
The function should set BL bit, but it should not clear other flags. So, the patch uses set_bl_bit() instead of a local asm code. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2012-11-29Merge branch 'master' of git://git.denx.de/u-boot-fdtTom Rini1-2/+0
2012-11-28fdt: Correct global_data condition in mainSimon Glass1-2/+0
We need an extra condition here in case we want to use fdt without the silent console/cmdline editing/post options. It is easier to just remove the #ifdef. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-28Merge branch 'master' of git://www.denx.de/git/u-boot-x86Tom Rini23-89/+181
2012-11-28x86: coreboot: Enable LPC TPMSimon Glass1-0/+4
Coreboot boards have an LPC TPM connected, so enable this. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-28x86: Remove coreboot start16 codeSimon Glass2-14/+1
Now that coreboot doesn't need the start16 code, remove it. We need to remove the CONFIG_SYS_X86_RESET_VECTOR option from coreboot.h also. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-28x86: coreboot: Implement recursively scanning PCI bussesGabe Black1-3/+23
A hook is installed to configure PCI bus bridges as they encountered by u-boot. The hook extracts the secondary bus number from the bridge's config space and then recursively scans that bus. On Coreboot, the PCI bus address space has identity mapping with the physical address space, so declare it as such to ensure that the "pci_map_bar" function used by some PCI drivers is behaving properly. This fixes the EHCI PCI driver initialization on Stumpy. This was tested as follows: Ran the PCI command on Alex, saw devices on bus 0, the OXPCIe 952 on bus 1, and empty busses 2 through 5. This matches the bridges reported on bus 0 and the PCI configuration output from coreboot. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-28x86: coreboot: Modify u-boot code to allow building coreboot payloadVadim Bendebury1-0/+37
This prevents the preprocessor from complaining when processing variadic macros Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Graeme Russ <graeme.russ@gmail.com>
2012-11-28x86: coreboot: Tell u-boot about PCI bus 0 when initializingGabe Black2-1/+16
U-boot needs a host controller or "hose" to interact with the PCI busses behind them. This change installs a host controller during initialization of the coreboot "board" which implements some of X86's basic PCI semantics. This relies on some existing generic code, but also duplicates a little bit of code from the sc520 implementation. Ideally we'd eliminate that duplication at some point. It looks like in order to scan buses beyond bus 0, we'll need to tell u-boot's generic PCI configuration code what to do if it encounters a bridge, specifically to scan the bus on the other side of it. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Graeme Russ <graeme.russ@gmail.com>
2012-11-28x86: coreboot: Move non-board specific files to coreboot arch directoryStefan Reinauer4-2/+2
coreboot.c and coreboot_pci.c don't contain board specific but only coreboot specific code. Hence move it to the coreboot directory in arch/x86/cpu (which should probably be moved out of cpu/ in another commit) Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-28x86: Add some missing includesGabe Black2-0/+5
I suspect these includes were usually available because something else included them earlier or because they were brought in transitively. Change-Id: I6aae2ac94dc792eac6febb4345e8125f69f70988 Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-28x86: Allow excluding reset vector code from u-bootGabe Black4-5/+13
When running from coreboot we don't want this code. This version works by ifdef-ing out all of the code that would go into those sections and all the code that refers to it. The sections are then empty, and the linker will either leave them empty for the loader to ignore or remove them entirely. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-28x86: Add initial memory barrier macrosSimon Glass1-0/+8
These are available on other architectures, so add them on x86. Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-28x86: Add ilog2 to bitopsGraeme Russ1-0/+5
ilog2 is required by AHCI driver Signed-off-by: Graeme Russ <graeme.russ@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-28x86: Remove duplicate PCI initGraeme Russ1-3/+0
Signed-off-by: Graeme Russ <graeme.russ@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-28x86: Put global data on the stackGraeme Russ9-61/+65
Putting global data on the stack simplifies the init process (and makes it slightly quicker). During the 'flash' stage of the init sequence, global data is in the CAR stack. After SDRAM is initialised, global data is copied from CAR to the SDRAM stack Signed-off-by: Graeme Russ <graeme.russ@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-11-28x86: Forward declare gd_tGraeme Russ3-5/+7
So it can be used as a type in struct global_data and remove an ugly typecast Signed-off-by: Graeme Russ <graeme.russ@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Marek Vasut <marex@denx.de>
2012-11-28Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xxTom Rini46-109/+1207
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