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2021-08-25Merge branch 'next-socfpga' of https://github.com/tienfong/uboot_mainlineWIP/25Aug2021Tom Rini43-89/+4467
2021-08-25arm: socfpga: Enable Intel N5X device buildSiew Chin Lim5-6/+257
Add defconfig for N5X to support legacy, ATF and VAB boot flow. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-08-25include: configs: Add Intel N5X device CONFIGsSiew Chin Lim1-0/+45
Add CONFIGs for N5X. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-08-25arm: dts: Add base dtsi and devkit dts for Intel N5X deviceSiew Chin Lim4-0/+377
Add device tree for N5X. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Ley Foon Tan <lftan.linux@gmail.com>
2021-08-25board: intel: Add socdk board support for Intel N5X deviceSiew Chin Lim3-0/+21
Add N5X SoC devkit board. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-08-25arm: socfpga: Add SPL for Intel N5X deviceSiew Chin Lim1-0/+94
Add SPL for N5X. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-08-25ddr: altera: Add SDRAM driver for Intel N5X deviceTien Fong Chee6-2/+2386
The DDR subsystem in Diamond Mesa is consisted of controller, PHY, memory reset manager and memory clock manager. Configuration settings of controller, PHY and memory reset manager is come from DDR handoff data in bitstream, which contain the register base addresses and user settings from tool. Configuration settings of memory clock manager is come from the HPS handoff data in bitstream, however the register base address is defined in device tree. The calibration is fully done in HPS, which requires IMEM and DMEM binaries loading to PHY SRAM for running this calibration, both IMEM and DMEM binaries are also part of bitstream, this bitstream would be loaded to OCRAM by SDM, and configured by DDR driver. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2021-08-25ddr: socfpga: Enable memory test on memory size less than 1GBTien Fong Chee1-3/+21
Minimum 1GB memory size is required in current memory test, so this patch improves the memory test for processing memory size less than 1GB, and the size in power of two. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2021-08-25arm: socfpga: Changed misc_s10.c to misc_soc64.cSiew Chin Lim2-8/+8
Rename to common file name to used by all SOC64 devices. No functionality change. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-08-25arm: socfpga: Add clock manager for Intel N5X deviceSiew Chin Lim3-0/+94
Add clock manager for N5X. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-08-25arm: socfpga: Move cm_get_mpu_clk_hz function declaration to clock_manager.hSiew Chin Lim5-5/+1
Move cm_get_mpu_clk_hz function declaration from individual device's clock manager header file to common clock_manager.h. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-08-25drivers: clk: Add memory clock driver for Intel N5X deviceSiew Chin Lim3-0/+221
Add memory clock manager driver for N5X. Provides memory clock initialization and enable functions. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-08-25arm: socfpga: Get clock manager base address for Intel N5X deviceSiew Chin Lim1-0/+3
Add N5X clock manager to socfpga_get_managers_addr function. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-08-25drivers: clk: Add clock driver for Intel N5X deviceSiew Chin Lim4-1/+779
Add clock manager driver for N5X. Provides clock initialization and get_rate functions. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-08-24arm: socfpga: Add handoff data support for Intel N5X deviceTien Fong Chee3-48/+140
N5X support both HPS handoff data and DDR handoff data. Existing HPS handoff functions are restructured to support both existing devices and N5X device. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2021-08-24arm: socfpga: Add base address for Intel N5X deviceSiew Chin Lim1-1/+2
Reuse base_addr_soc64.h for Intel N5X device, the address is the same as Agilex. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-08-24arm: socfpga: Changed base_addr_s10.h to base_addr_soc64.hSiew Chin Lim2-5/+5
Rename to common file name to used by all SOC64 devices and change "_S10_" to "_SOC64_" in base_addr_soc64.h. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-08-24arm: socfpga: Move linux_qspi_enable from bootcommand to board_prep_linux ↵Siew Chin Lim3-10/+11
function Move 'linux_qspi_enable' from bootcommand to board_prep_linux function when OS booted from FIT image for Stratix 10 and Agilex. This flow is common for all Intel SOC64 devices. U-Boot will update 'fdt_addr' environment value based on FIT image in board_prep_linux function, and 'linux_qspi_enable' will refer to 'fdt_addr' environment value to retrieve the device tree node. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-08-23Merge tag 'efi-2021-10-rc3' of ↵WIP/23Aug2021Tom Rini27-53/+100
https://source.denx.de/u-boot/custodians/u-boot-efi Pull request for efi-2021-10-rc3 Documentation: * Rename Freescale to NXP * Document structures used for the UEFI TCG2 protocol UEFI: * Device paths must use EfiBootServicesData
2021-08-23Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini41-103/+237
fsl-qoriq: Fixes related to env, spi, usb, crypto, configs, distro-boot for Layerscape Boards like lx2, sl28, ls2088ardb. powerpc: Fixes for t208xrdb revd board and cortina related configs update for T208xRDB, T4240RDB.
2021-08-23Merge tag 'for-v2021.10-rc3' of ↵Tom Rini14-3/+569
https://source.denx.de/u-boot/custodians/u-boot-i2c i2c changes for for-v2021.10-rc3 new driver: - Introduce mcp230xx support from Sebastian Reichel new feature: - i2c-gpio: add support for "sda-gpios" + "scl-gpios" i2c-gpio bindings. from Samuel Holland - bootcount: add a new driver with syscon as backend from Nandor Han
2021-08-22Merge branch '2021-08-21-assorted-changes'WIP/22Aug2021Tom Rini6-23/+1146
2021-08-22bootcount: add a new driver with syscon as backendNandor Han7-3/+256
The driver will use a syscon regmap as backend and supports both 16 and 32 size value. The value will be stored in the CPU's endianness. Signed-off-by: Nandor Han <nandor.han@vaisala.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-08-22i2c: i2c-gpio: Support the named GPIO bindingSamuel Holland1-0/+9
To avoid confusion about the order of the GPIOs, the i2c-gpio binding was updated to use a separate property for each GPIO instead of an array. However, the driver only supports the old binding. Add support for the new binding as well, so the driver continues to work as device trees are updated. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Heiko Schocher <hs@denx.de>
2021-08-22gpio: mcp230xx: Introduce new driverSebastian Reichel3-0/+246
Introduce driver for I2C based MCP230xx GPIO chips, which are quite common and already well supported by the Linux kernel. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-08-22i2c: add dm_i2c_reg_clrsetSebastian Reichel3-0/+58
Add function to apply a bitmask to an i2c register, so that specific bits can be cleared and/or set. Suggested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-08-21display_options: Do not use %llu in print_sizeWIP/2021-08-21-assorted-changesMatwey V. Kornilov1-1/+6
tiny-printf variant doesn't know how to handle %llu format string, but both tiny-printf and print_size can meet in SPL when TFTP is used to obtain main u-boot image. This is known to lead to critical boot issue at AM335x platform when printf is catched in infinite loop. To avoid such issues and make print_size function tiny-printf friendly, use %u instead of %luu. Note, that the size value is guaranteed to be less than 1024 in this conditional branch, so the cast to unsigned int is safe. Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-08-21tiny-printf: Handle %pM format when CONFIG_SPL_NET_SUPPORT is enabledMatwey V. Kornilov1-13/+13
%pM format string is used to print MAC-address and this is required while SPL network boot. This patch fixes the SPL boot issues like the following: Trying to boot from USB eth ## Error: flags type check failure for "ethaddr" <= "40309614M" (type: m) ## Error inserting "ethaddr" variable, errno=1 eth0: eth_cpsw## Error: flags type check failure for "eth1addr" <= "81f01114M" (type: m) ## Error inserting "eth1addr" variable, errno=1 , eth1: usb_ether eth_cpsw Waiting for PHY auto negotiation to complete......... TIMEOUT ! Problem booting with BOOTP SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ### Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-08-21Fix flashing of eMMC user area with FastbootOleh Kravchenko1-7/+15
'gpt' and 'mmc0' fastboot partitions have been treated as the same device, but it is wrong. Fill disk_partition structure with eMMC user partition info to properly flash data. Signed-off-by: Oleh Kravchenko <oleg@kaa.org.ua> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Marek Vasut <marex@denx.de> Cc: Sean Anderson <sean.anderson@seco.com> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Sean Anderson <sean.anderson@seco.com>
2021-08-21Fix flash and erase of eMMC Boot2 with FastbootOleh Kravchenko1-2/+2
The current U-Boot version has the next matches for boot partitions: > mmc0boot0 to EMMC_BOOT1 > mmc0boot1 to EMMC_BOOT1 (should be EMMC_BOOT2) This patch fixes a typo for the boot partition number. Signed-off-by: Oleh Kravchenko <oleg@kaa.org.ua> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Marek Vasut <marex@denx.de> Reviewed-by: Sean Anderson <sean.anderson@seco.com>
2021-08-21clk: clk_versaclock: Add support for versaclock driverAdam Ford3-0/+1110
The driver is based on the Versaclock driver from the Linux code, but due differences in the clock API between them, some pieces had to be changed. This driver creates a mux, pfd, pll, and a series of fod ouputs. Rate Usecnt Name ------------------------------------------ 25000000 0 `-- x304-clock 25000000 0 `-- clock-controller@6a.mux 25000000 0 |-- clock-controller@6a.pfd 2800000000 0 | `-- clock-controller@6a.pll 33333333 0 | |-- clock-controller@6a.fod0 33333333 0 | | `-- clock-controller@6a.out1 33333333 0 | |-- clock-controller@6a.fod1 33333333 0 | | `-- clock-controller@6a.out2 50000000 0 | |-- clock-controller@6a.fod2 50000000 0 | | `-- clock-controller@6a.out3 125000000 0 | `-- clock-controller@6a.fod3 125000000 0 | `-- clock-controller@6a.out4 25000000 0 `-- clock-controller@6a.out0_sel_i2cb A translation function is added so the references to <&versaclock X> get routed to the corresponding clock-controller@6a.outX. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Sean Anderson <sean.anderson@seco.com>
2021-08-20configs: lx2160a: load device-tree in RAM for distro bootPriyanka Jain1-0/+3
Update boot-commands to load device-tree from boot-device at 'fdt_addr_r' address in DDR during distro-boot. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-08-19Merge https://source.denx.de/u-boot/custodians/u-boot-riscvWIP/19Aug2021Tom Rini6-4/+29
2021-08-18crypto/fsl: fix missed dma_addr_t -> caam_dma_addr_t conversionHoria Geantă1-1/+1
One of the "dma_addr_t" instances was left out when converting to "caam_dma_addr_t". Fixes: 2ff17d2f74c5 ("crypto: fsl: refactor for 32 bit version CAAM support on ARM64") Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-08-18board: T4240rdb: Extend cs4340_get_fw_addr() functionalityKuldeep Singh2-0/+22
T4240RDB supports booting from 2 nor banks(default and altbank). The corresponding defconfig can only have one entry defined and therefore, extend cs4340_get_fw_addr() function to overwrite firmware address which will be later used in cortina firmware. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-08-18board: t208x: Extend cs4340_get_fw_addr() functionalityKuldeep Singh2-0/+23
T2080RDB supports booting from 2 nor banks(default and altbank). The corresponding defconfig can only have one entry defined and therefore, extend cs4340_get_fw_addr() function to overwrite firmware address which will be later used in cortina firmware. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-08-18board: ls2088ardb: Extend cs4340_get_fw_addr() functionalityKuldeep Singh1-0/+38
LS2088A-RDB supports TFA boot source and has 2 nor banks(default and altbank) and QSPI as boot source. The corresponding defconfig can only have one entry defined and therefore, extend cs4340_get_fw_addr() function to overwrite firmware address which will be later used in cortina firmware. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-08-18net: cortina: Add support for tfa boot in cortina firmwareKuldeep Singh1-10/+69
Add support for boards supporting TFA boot separately in cortina firmware. Please note, a weak function is defined to retrieve firmware address values as CONFIG_CORTINA_FW_ADDR is now defined in defconfig and can only have one possible value defined. This weak function will help in overwrting the values to get proper addresses as per boot source. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-08-18configs: Migrate CORTINA_FW_ADDR and CORTINA_FW_LENGTH to KconfigKuldeep Singh21-20/+26
Use moveconfig.py script to convert below defines to Kconfig and move these entries to defconfigs. CONFIG_CORTINA_FW_ADDR CONFIG_CORTINA_FW_LENGTH Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-08-18env: Kconfig: Add default option for PHY_CORTINAKuldeep Singh1-1/+1
Add PHY_CORTINA as default option in SYS_MMC_ENV_DEV Kconfig entry as PHY_CORTINA require SYS_MMC_ENV_DEV value similar to FMAN_ENET or QE. This helps in resolving compilation failure. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-08-18armv8: fsl : create bootcmd and mcinitcmd as per boot sourceWasim Khan1-3/+6
NXP platforms expect custom bootcmd and mcinitcmd to be updated as per boot source with default environment. Check env variable fsl_bootcmd_mcinitcmd_set to prepare bootcmd and mcinitcmd Fixes: cbf77d201870 (armv8: fsl-layerscape: Fix automatic setting of bootmcd with TF-A) Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-08-18board: fsl_validate: Fix resource leak issueKshitiz Varshney1-9/+27
Free dynamically allocated memory before every return statement in calc_img_key_hash() and calc_esbchdr_esbc_hash() function. Verified the secure boot changes using ls1046afrwy board. Signed-off-by: Kshitiz Varshney <kshitiz.varshney@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-08-18board: freescale: t208xrdb: enable Power-On Reset for rev D boardsCamelia Groza2-0/+11
Starting with board revision D, the MISCCSR CPLD register needs to be configured to enable Power-on Reset for software reset commands. Signed-off-by: Camelia Groza <camelia.groza@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-08-18lx2160a: Enable CONFIG_SPI_FLASH_MT35XU for lx2160a-rdb/qdsKuldeep Singh5-0/+5
LX2160A-RDB/QDS has micron mt35xu512aba flash which requires flag CONFIG_SPI_FLASH_MT35XU on to probe flash successfully. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-08-18board: sl28: drop unneeded and outdated flash partitionsMichael Walle1-55/+0
This board doesn't use the MTD subsystem in u-boot, thus there is no need to specify the partitions. They are outdated anyway. Just drop them. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-08-18arm: Finish migration of HAS_FSL_XHCI_USBTom Rini2-3/+4
This symbol was largely migrated, except for one case. Update it. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-08-18spi: nxp_fspi: Ensure width is respected in spi-mem operationsMichael Walle1-1/+1
Import linux commit 007773e16a6f ("spi: nxp-fspi: Ensure width is respected in spi-mem operations") to fix SPI access on boards which don't have all SPI I/O lines connected to the flash. Since commit 71025f013ccb ("mtd: spi-nor-core: Rework hwcaps selection") u-boot figures out the capabilities by looking at spi_mem_supports_op(). The FlexSPI driver doesn't take the board layout into account. Fix that. Fixes: 383fded70c4f ("spi: nxp_fspi: new driver for the FlexSPI controller") Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-08-17efi_loader: use EfiBootServicesData for DP to textHeinrich Schuchardt1-1/+1
Memory allocated in the implementation of the EFI_DEVICE_PATH_TO_TEXT_PROTOCOL must be of type EfiBootServicesData. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2021-08-17efi_loader: use EfiBootServicesData for device pathHeinrich Schuchardt1-1/+1
dp_alloc() was using a constant from the wrong enum resulting in creating device paths in EfiReservedMemory. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2021-08-17efi_loader: use correct type for AllocatePages, AllocatePoolHeinrich Schuchardt2-6/+8
Use enum efi_memory_type and enum_allocate_type in the definitions of the efi_allocate_pages(), efi_allocate_pool(). In the external UEFI API leave the type as int as the UEFI specification explicitely requires that enums use a 32bit type. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
generated by cgit v1.1 at 2024-08-05 14:19:52 +0000