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2019-10-25mips: mtmips: change baudrate table for all boardsWeijie Gao2-2/+2
This patch changes baudrate table for all boards preparing for using mtk highspeed uart driver. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25dts: mtmips: add default pinctrl to eth nodes for all boardsWeijie Gao2-0/+4
This patch adds default eth pinctrl for all boards. There are two pinctrl nodes used for two scenarios: ephy_iot_mode - for IOT boards which have only one port (PHY0) ephy_router_mode - For routers which have more than one ports Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25dts: mtmips: add default pinctrl for gardena-smart-gateway-mt7688Weijie Gao1-0/+3
This adds default pinctrl (dual SPI chip select) for gardena smart gateway Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25dts: mtmips: add mmc related nodes for mt7628an.dtsiWeijie Gao1-0/+22
This patch adds mmc related nodes for mt7628an.dtsi Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25mmc: mtk-sd: add a dts property cd-active-high for builtin-cd modeWeijie Gao1-1/+5
This patch adds a dts property cd-active-high for builtin-cd mode to make it configurable instead of using hardcoded active-low. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25mmc: mtk-sd: add support for MediaTek MT7620/MT7628 SoCsWeijie Gao2-4/+21
This patch adds mmc support for MediaTek MT7620/MT7628 SoCs. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25dts: mtmips: enable eth port0 led and link poll functions for all boardsWeijie Gao3-1/+27
This patch adds default p0led status and phy0 link polling for all boards. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25net: mt7628-eth: add support to isolate LAN/WAN portsWeijie Gao1-0/+32
This patch add support for mt7628-eth to isolate LAN/WAN ports mainly to prevent LAN devices from getting IP address from WAN. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25net: mt7628-eth: free rx descriptor on receiving failureWeijie Gao1-0/+3
When received a packet with an invalid length recorded in rx descriptor, we should free this rx descriptor to allow us to continue to receive following packets. Without doing so, u-boot will stuck in a dead loop trying to process this invalid rx descriptor. This patch adds a call to mt7628_eth_free_pkt() after received an invalid packet length. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25net: mt7628-eth: make phy link up detection optional via DTWeijie Gao2-29/+31
The mt7628 has an embedded ethernet switch (5 phy ports + 1 cpu port). Although in IOT mode only port0 is usable, the phy0 is still connected to the switch, not the ethernet gmac directly. This patch rewrites it and makes it optional. It can be turned on by adding mediatek,poll-link-phy = <?> explicitly into the eth node. By default the driver is switch mode with all 5 phy ports working without link detection. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25net: mt7628-eth: remove hardcoded gpio settings and regmap-based phy resetWeijie Gao1-37/+8
This patch removes hardcoded gpio settings as they have been replaced by pinctrl in dts, and also replaces regmap-based phy reset with a more generic reset controller. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25phy: mt76x8-usb-phy: add slew rate calibration and remove non-mt7628 partWeijie Gao2-68/+158
This patch adds slew rate calibration for mt76x8-usb-phy, removes code which belongs to mt7620, and gets rid of using syscon and regmap by using clock driver and reset controller. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25dts: mtmips: update reset controller node for mt7628Weijie Gao1-12/+24
This patch updates reset controller node for mt7628 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25reset: add reset controller driver for MediaTek MIPS platformWeijie Gao4-0/+126
This patch adds reset controller driver for MediaTek MIPS platform and header file for mt7628. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25dts: mtmips: add default pinctrl for uart nodesWeijie Gao1-0/+9
This patch adds default pinctrl for uart nodes Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25dts: mtmips: add pinctrl node for mt7628Weijie Gao1-0/+150
This patch adds pinctrl node with default pin state for mt7628an.dtsi. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25pinctrl: add support for MediaTek MT7628Weijie Gao7-0/+747
This patch adds pinctrl support for mt7628, with a file for common pinmux functions and a file for mt7628 which has additional support for pinconf. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25spi: mt7621-spi: restore default register value after each xferWeijie Gao1-13/+17
Currently this driver uses a different way to implement the spi xfer, by modifying some fields of two registers, which is incompatible with the MTK's original SDK linux driver. This will cause the flash data being damaged by the SDK driver. This patch lets the mt7621_spi_set_cs() restore the original register fields after cs deactivated. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25spi: mt7621-spi: remove data cache and rewrite its xfer functionWeijie Gao1-106/+91
The mt7621 spi controller supports continuous generic half-duplex spi transaction. There is no need to cache xfer data at all. To achieve this goal, the OPADDR register must be used as the first data to be sent. And follows the eight generic DIDO registers. But one thing different between OPADDR and DIDO registers is OPADDR has a reversed byte order. With this patch, any amount of data can be read/written in a single xfer function call. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25spi: mt7621-spi: use clock frequency from clk driverWeijie Gao1-7/+13
This patch lets the spi driver to use clock provided by the clk driver since the new clk-mt7628 driver provides accurate sys clock frequency. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25dts: mtmips: add clock node for mt7628Weijie Gao1-4/+17
This patch adds clkctrl node for mt7628 and adds clocks property for some node. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25clk: add clock driver for MediaTek MT76x8 platformWeijie Gao4-0/+199
This patch adds a clock driver for MediaTek MT7628/7688 SoC. It provides clock gate control as well as getting clock frequency for CPU/SYS/XTAL and some peripherals. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25dts: mtmips: enable high-speed UART support for mt7628Weijie Gao1-3/+3
All three UARTs of mt7628 are actually MediaTek's high-speed UARTs which support baudrate up to 921600. The high-speed UART is compatible with ns16550 when baudrate <= 115200. Add compatible string to dtsi file so u-boot can use it when serial_mtk driver is built in. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25dts: mtmips: move uart property clock-frequency into mt7628an.dtsiWeijie Gao3-2/+6
The UART of MT7628 has fixed 40MHz input clock so there is no need to put clock-frequency in every dts files. Just put it into the common dtsi file. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25serial: serial_mtk: add non-DM version for SPLWeijie Gao2-17/+187
This patch adds non-DM version for mtk hsuart driver and makes it compatible with ns16550a driver in configuration. This is needed in SPL with CONFIG_SPL_DM disabled for reducing size. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25serial: serial_mtk: enable FIFO and disable flow controlWeijie Gao1-0/+21
This patch adds codes to enable FIFO and disable flow control taken from ns16550 driver. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25drivers: nand: brcmnand: fix nand_chip ecc layout structureWilliam Zhang1-156/+104
The current brcmnand driver is based on 4.18 linux kernel which uses mtd_set_ooblayout to set ecc layout. But nand base code in u-boot is from old kernel which does not use this new API and expect nand_chip.ecc.layout structure to be set. This cause nand_scan_tail function running into a bug check if the device has a different oob size than the default ones. This patch ports the brcmstb_choose_ecc_layout function from kernel 4.6.7 that supports the ecc layout struture and replaces the mtd_set_ooblayout method Signed-off-by: William Zhang <william.zhang@broadcom.com> Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-10-25mips: bmips: switch to board defines for dtbÁlvaro Fernández Rojas1-2/+2
Fixes commit 344db3f, which added missing bmips dtbs depending on their SoCs. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2019-10-25bmips: correct name charactersÁlvaro Fernández Rojas7-7/+7
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2019-10-25bmips: configs: switch to size definitionsÁlvaro Fernández Rojas22-45/+58
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-10-25mips: bmips: remove unneeded definitionsÁlvaro Fernández Rojas1-4/+0
These are no longer needed. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-10-25bmips: enable vr-3032u nand supportÁlvaro Fernández Rojas3-0/+23
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2019-10-25bmips: bcm63268: add support for brcmnandÁlvaro Fernández Rojas1-0/+18
BCM63268 uses 4.0 HW nand controller, which is currently supported by brcmnand driver. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2019-10-25bmips: bcm6362: add support for brcmnandÁlvaro Fernández Rojas1-0/+18
BCM6362 uses old 2.2 HW nand controller, which isn't currently supported by brcmnand driver. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2019-10-25bmips: bcm6328: add support for brcmnandÁlvaro Fernández Rojas1-0/+16
BCM6328 uses old 2.2 HW nand controller, which isn't currently supported by brcmnand driver. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2019-10-25bmips: bcm6368: add support for brcmnandÁlvaro Fernández Rojas1-0/+18
BCM6368 uses old 2.1 HW nand controller, which isn't currently supported by brcmnand driver. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2019-10-25nand: brcm: add BCM6368 supportÁlvaro Fernández Rojas3-0/+124
This adds support for BCM6368, BCM6328, BCM6362 and BCM63268 SoCs. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-10-25MIPS: add compile time definition of L2 cache sizeRamon Fried2-2/+10
If configuration is set to skip low level init, automatic probe of L2 cache size is not performed and the size is set to 0. Flushing or invalidating the L2 cache will fail in this case. Add a static configuration (SYS_DCACHE_LINE_SIZE) with default set to 0. Signed-off-by: Ramon Fried <rfried.dev@gmail.com>
2019-10-25sunxi: set PIO voltage to hardware-detected value on startup on H6Icenowy Zheng2-0/+12
The Allwinner H6 SoC has a register to set the PIO banks' voltage. When it mismatches the real voltage supplied to the VCC to the PIO supply, the PIO will work improperly. The PIO controller also has a register that contains the status of each VCC rail of the PIO supplies, and it has the same definition with the configuration register. so we can just copy the content of this register to the configuration register at startup, to ensure the configuration is correct at startup stage. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> [jagan: s/__maybe__unused/__maybe_unused] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25arm: dts: sync dts for Allwinner H6Clément Péron3-3/+131
Sync Kernel DTS for Allwinner H6 boards. Drop /omit-if-no-ref/ keyword as it's not supported by U-boot. commit <d45331b00ddb> Linux 5.3-rc4 Signed-off-by: Clément Péron <peron.clem@gmail.com> Acked-by: Maxime Ripard <mripard@kernel.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25sunxi: Fix pll1 clock calculationStefan Mavrodiev1-1/+1
clock_sun6i.c is used for sun6i, sun8i and sun50i SoC families. PLL1 clock sets the default system clock, defined as: sun6i: 1008000000 sun8i: 1008000000 sun50i: 816000000 With the current calculation, m = 2 and k = 3. Solving for n, this results 28. Solving back: (24MHz * 28 * 3) / 2 = 1008MHz However if the requested clock is 816, n is 22.66 rounded to 22, which results: (24MHz * 28 * 3) / 2 = 792MHz Changing k to 4 satisfies both system clocks: (24E6 * 21 * 4) / 2 = 1008MHz (24E6 * 17 * 4) / 2 = 816MHz Signed-off-by: Stefan Mavrodiev <stefan@olimex.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25arm64: dts: sun50i: Add support for A64 OLinuXino (with eMMC)Sunil Mohan Adapa4-0/+46
A64 OLinuXino board from Olimex has three variants with onboard eMMC: A64-OLinuXino-1Ge16GW, A64-OLinuXino-1Ge4GW and A64-OLinuXino-2Ge8G-IND. In addition, there are two variants without eMMC. One without eMMC and one with SPI flash. This suggests the need for separate device tree for the three eMMC variants. The Linux kernel upstream has chosen to create and use a separate device tree for the eMMC variants instead of adding eMMC support existing device tree. These changes to Linux kernel are queued for Linux 5.4. commit <02bb66b347ff8115f53948f86b884e008ba385b9> ("arm64: dts: allwinner: a64: Add A64 OlinuXino board (with eMMC)") This patch has been tested on A64-OLinuXino-1Ge16GW and is based on Linux device-tree and a64-olinuxino_defconfig. Signed-off-by: Sunil Mohan Adapa <sunil@medhas.org> [jagan: updated linux-next commit details] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25sunxi: H6: DRAM: Add support for half DQJernej Skrabec2-25/+54
Half DQ configuration seems to be very rare for H6 based boards/STBs, but exists nevertheless. Currently the only known product which needs this support is Tanix TX6 mini. This commit adds support for half DQ configuration. Code was tested for regressions on other configurations (OrangePi 3 1 GiB/LPDDR3, Tanix TX6 4 GiB/DDR3) and none were found. Thanks to Icenowy Zheng for help with this code. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Tested-by: thomas graichen <thomas.graichen@gmail.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Maxime Ripard <mripard@kernel.org>
2019-10-25spi-nor-ids: Add support for Adesto AT25SL321Fabio Estevam1-0/+1
Add an entry for the Adesto AT25SL321 SPI NOR chip. This SPI NOR chip is found in the Embedded Artist i.MX7ULP COM board. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25mtd: spi: Clean up usage of CONFIG_SPI_FLASH_MTDFrieder Schrempf26-37/+23
Most boards currently use SPI_FLASH_MTD only in U-Boot proper, not in SPL. They often rely on hacks in the board header files to include this option conditionally. To be able to fix this, we previously introduced a separate option SPL_SPI_FLASH_MTD. Therefore we can now adjust the Makefile and change the code in sf_probe.c and sf_internal.h to use CONFIG_IS_ENABLED(SPI_FLASH_MTD). We also need to move all occurences of CONFIG_SPI_FLASH_MTD from the header files to the according defconfigs. The affected boards are socfpga, aristainetos, cm_fx6, display5, ventana, rcar-gen2, dh_imx6 and da850evm. We do this all in one patch to guarantee bisectibility. This change was tested with buildman to make sure it does not introduce any regressions by comparing the resulting binary sizes. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25spi-nor: spi-nor-ids: Add USE_FSR flag for mt25q* and n25q* entryVignesh Raghavendra1-5/+6
n25q* and mt25q* (both 256Mb and 512Mb) flashes support Flag status register that indicates various errors that may be encountered during erase/write operations. Therefore add USE_FSR flag wherever missing. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25spi-nor: spi-nor-ids: Add entries for mt25q variantsVignesh Raghavendra1-0/+3
mt25q* flashes support stateless 4 byte addressing opcodes. Add entries for the same. These flashes have bit 6 set in 5th byte of READ ID response when compared to n25q* variants. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25spi-nor: spi-nor-ids: Disable SPI_NOR_4B_OPCODES for n25q512* and n25q256*Vignesh Raghavendra1-4/+4
Per datasheets of n25q256* and n25q512* not all variants of n25q256* and n25q512* support 4 Byte stateless addressing opcodes. Therefore drop SPI_NOR_4B_OPCODES flag from these entries Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25spi: designware_spi: Disable and free clock when remove driverLey Foon Tan1-1/+15
Disable and free clock when remove driver. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25mtd: spi-nor-core: Replace MTD_SPI_NOR_USE_4K_SECTORS with ↵Vignesh Raghavendra2-2/+2
SPI_FLASH_USE_4K_SECTORS U-Boot uses CONFIG_SPI_FLASH_USE_4K_SECTORS to enable 4K small sector support. Use that instead of MTD_SPI_NOR_USE_4K_SECTORS. Reported-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
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