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2018-02-23configs: Re-sync with CONFIG_DISTRO_DEFAULTSTom Rini111-753/+223
A number of platforms include config_distro_defaults.h but do not enable CONFIG_DISTRO_DEFAULTS. As they plainly intended to, set that flag and re-sync config files. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-02-20Prepare v2018.03-rc3v2018.03-rc3Tom Rini1-1/+1
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-02-20script: Make the get_default_envs.sh script working with newest u-bootLukasz Majewski1-6/+15
This commit fixes several issues: - After moving env related code to ./env directory the env_common.o file is no longer present in the system (has been replaced with built-in.o). - Use ${OBJCOPY} if available, fallback to system default's objcopy if not present. - Extend the script to accept different build directory than current one. It is extremely handy with OE usage, where source code is separated from build. Signed-off-by: Lukasz Majewski <lukma@denx.de> Tested-by: Alex Kiernan <alex.kiernan@gmail.com>
2018-02-20env: mmc/fat/ext4: make sure that the MMC sub-system is initialized before ↵Faiz Abbas3-0/+8
using it When booting from a non-MMC device, the MMC sub-system may not be initialized when the environment is first accessed. We need to make sure that the MMC sub-system is ready in even a non-MMC boot case. Therefore, initialize mmc before loading environment from it. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2018-02-19Merge git://git.denx.de/u-boot-mmcTom Rini18-111/+1125
2018-02-19Merge git://git.denx.de/u-boot-dmTom Rini24-58/+593
2018-02-19Merge git://git.denx.de/u-boot-ubiTom Rini3-25/+40
2018-02-19Merge git://git.denx.de/u-boot-i2cTom Rini1-1/+4
2018-02-19Merge git://git.denx.de/u-boot-shTom Rini1-32/+21
2018-02-19vexpress: Sign up as maintainerLinus Walleij1-6/+2
These ARM boards are in nice shape and still being used a lot with e.g. QEMU, so I can maintain them. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-02-19mmc: Fix uninitialised priv memberAlex Kiernan1-1/+1
When using omap_hsmmc without the device model then the allocation of mmc->priv ends up uninitialised. Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com> Tested-by: Robert Nelson <robertcnelson@gmail.com> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
2018-02-19mmc: fix bug in mmc_startup_v4()Jean-Jacques Hiblot2-0/+2
The correspondence between mmc versions as used in u-boot and the version numbers reported in register EXT_CSD_REV is wrong for versions above and including MMC_VERSION_4_41. All those versions were shifted by one: real 4.5 hardware appeared to be MMC_VERSION_5_0. Fix this by adding the missing version in the correspondence table. Reported-by: eil Eilmsteiner Heribert <eil@keba.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
2018-02-19mmc: Fix bug in sd_set_card_speed()Jean-Jacques Hiblot1-1/+1
After settings the speed of the sd with the switch command, a check is done to make sure that the new speed has been set. The current check has a masking error: speed are encoded on 4 bits only. Fix it by masking the upper bits. This fixes a problem seen with QEmu emulating a vexpress-a15. Reported-by: Jonathan Gray <jsg@jsg.id.au> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Tested-by: Jonathan Gray <jsg@jsg.id.au>
2018-02-19configs: dra7xx_evm/dra7xx_hs_evm: Enable MMC HS200 and SD UHS supportJean-Jacques Hiblot2-0/+6
By default UHS and HS200 are not enabled. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-02-19ARM: DRA7x/AM57x: Add MMC/SD fixups for rev1.0 and rev 1.1Kishon Vijay Abraham I2-0/+59
Since DRA7xx/AM57xx SR1.1 and SR1.0 has errata to limit the frequency of MMC1 to 96MHz and frequency of MMC2 to 48MHz for AM572x SR1.1, limit the frequency and disable higher speed modes for those revision. Also use the recommended IO delays (those tagged with "rev11") Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-02-19dts: am57xx-idk: disable HS200 supportJean-Jacques Hiblot1-0/+2
HS200 cannot be supported on mmc2, because the IO lines of mmc2 are connected to 3.3v. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-02-19dts: am57xx-beagle-x15: disable UHS and HS200 supportJean-Jacques Hiblot1-0/+6
The UHS modes are not supported in beagle-x15 because it's not possible to switch the IO lines supply voltage to 1.8v. Also HS200 cannot be supported on mmc2, because the IO lines of mmc2 are connected to 3.3v. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-02-19ARM: dts: dra7: Add supported MMC/SD modes in MMC dt nodesJean-Jacques Hiblot1-0/+14
On DRA7 family SoCs, MMC1 controller supports SDR104, SDR50, DDR50, SDR25 and SDR12 UHS modes. MMC2 controller supports HS200 and DDR modes. MMC3 controller supports SDR12, SDR25 and SDR50 modes. MMC4 controller supports SDR12 and SDR25 modes. Add these supported modes in device-tree file. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-02-19ARM: dts: DRA7: use new dra7-specific compatible stringKishon Vijay Abraham I1-4/+4
Use the new compatible string "ti,dra7-hsmmc" that was specifically added for dra7 and dra72. This is required since for dra7 and dra72 processors iodelay values has to be set unlike other processors. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-02-19ARM: OMAP5: set mmc clock frequency to 192MHzKishon Vijay Abraham I3-6/+10
Now that omap_hsmmc has support for hs200 mode, change the clock frequency to 192MHz. Also change the REFERENCE CLOCK frequency to 192MHz based on which the internal mmc clock divider is calculated. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-02-19mmc: omap_hsmmc: add signal voltage selection supportJean-Jacques Hiblot2-26/+160
I/O data lines of UHS SD card operates at 1.8V when in UHS speed mode (same is true for eMMC in DDR and HS200 modes). Add support to switch signal voltage to 1.8V in order to support UHS cards and eMMC HS200 and DDR modes. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-02-19mmc: omap_hsmmc: allow mmc clock to be gatedKishon Vijay Abraham I1-0/+6
mmc core has defined a new parameter *clk_disable* to gate the clock. Disable the clock here if *clk_disable* is set. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-02-19mmc: omap_hsmmc: implement send_init_stream callbackJean-Jacques Hiblot1-0/+13
This callback is used to send the 74 clock cycles after power up. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-02-19mmc: omap_hsmmc: update mmc->clock with the actual bus speedJean-Jacques Hiblot1-1/+2
When the clock is applied, compute the actual value of the clock. It may be slightly different from the requested value (max freq, divisor threshold) Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-02-19mmc: omap_hsmmc: allow the simple HS modes to use the default pinctrlJean-Jacques Hiblot1-10/+13
The default configuration is usually working fine for the the HS modes. Don't enforce the presence of a dedicated pinmux for the HS modes. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-02-19mmc: omap_hsmmc: Add support to get pinctrl values and max frequency for ↵Kishon Vijay Abraham I3-14/+52
different hw revisions AM572x SR1.1 requires different IODelay values to be used than that used in AM572x SR2.0. These values are populated in device tree. Add capability in omap_hsmmc driver to extract IOdelay values for different silicon revision. The maximum frequency is also reduced when using a ES1.1. To keep the ability to boot both revsions with the same dtb, those values can be provided by the platform code. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-02-19mmc: omap_hsmmc: Add support to set IODELAY valuesKishon Vijay Abraham I1-0/+372
The data manual of J6/J6 Eco recommends to set different IODELAY values depending on the mode in which the MMC/SD is enumerated in order to ensure IO timings are met. Add support to parse mux values and iodelay values from device tree and set these depending on the enumerated MMC mode. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-02-19ARM: OMAP5/DRA7: Enable iodelay recalibration to be done from ubootKishon Vijay Abraham I4-4/+33
Add a new API to perform iodelay recalibration without isolate io to be used in uboot. The data manual of J6/J6 Eco recommends to set different IODELAY values depending on the mode in which the MMC/SD is enumerated in order to ensure IO timings are met. The MMC driver can use the new API to set the IO delay values depending on the MMC mode. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-02-19mmc: omap_hsmmc: use mmc_of_parse to populate mmc_configKishon Vijay Abraham I1-19/+5
Use the mmc_of_parse library function to populate mmc_config instead of repeating the same code in host controller driver. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-02-19mmc: omap_hsmmc: Reduce the max timeout for reset controller fsmJean-Jacques Hiblot1-1/+2
>From OMAP3 SoCs (OMAP3, OMAP4, OMAP5, AM572x, AM571x), the DAT/CMD lines reset procedure section in TRM suggests to first poll the SRD/SRC bit until it is set to 0x1. But looks like that bit is never set to 1 and there is an observable delay of 1sec everytime the driver tries to reset DAT/CMD. (The same is observed in linux kernel). Reduce the time the driver waits for the controller to set the SRC/SRD bits to 1 so that there is no observable delay. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-02-19mmc: omap_hsmmc: Workaround for errata id i802Jean-Jacques Hiblot2-6/+26
According to errata i802, DCRC error interrupts (MMCHS_STAT[21] DCRC=0x1) can occur during the tuning procedure. The DCRC interrupt, occurs when the last tuning block fails (the last ratio tested). The delay from CRC check until the interrupt is asserted is bigger than the delay until assertion of the tuning end flag. Assertion of tuning end flag is what masks the interrupts. Because of this race, an erroneous DCRC interrupt occurs. The suggested workaround is to disable DCRC interrupts during the tuning procedure which is implemented here. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-02-19mmc: omap_hsmmc: Add tuning supportJean-Jacques Hiblot2-2/+141
HS200/SDR104 requires tuning command to be sent to the card. Use the mmc_send_tuning library function to send the tuning command and configure the internal DLL. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-02-19mmc: omap_hsmmc: Enable DDR mode supportKishon Vijay Abraham I2-0/+6
In order to enable DDR mode, Dual Data Rate mode bit has to be set in MMCHS_CON register. Set it here. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-02-19mmc: omap_hsmmc: set MMC mode in the UHSMS bit fieldJean-Jacques Hiblot2-1/+58
Use the timing parameter set in the MMC core to set the mode in UHSMS bit field. This is in preparation for adding HS200 support in omap hsmmc driver. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-02-19mmc: omap_hsmmc: add support to set default io voltageKishon Vijay Abraham I2-2/+77
"ti,dual-volt" is used in linux kernel to set the voltage capabilities. For host controller dt nodes that doesn't have "ti,dual-volt", it's assumed 1.8v is the io voltage. This is not always true (like in the case of beagle-x15 where the io lines are connected to 3.3v). Hence if "no-1-8-v" property is set, io voltage will be set to 3v. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-02-19mmc: omap_hsmmc: cleanup omap_hsmmc_set_iosKishon Vijay Abraham I1-9/+20
No functional change. Move bus width configuration setting to a separate function and invoke it only if there is a change in the bus width. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-02-19mmc: omap_hsmmc: cleanup clock configurationJean-Jacques Hiblot2-24/+54
Add a separate function for starting the clock, stopping the clock and setting the clock. Starting the clock and stopping the clock can be used irrespective of setting the clock (For example during iodelay recalibration). Also set the clock only if there is a change in frequency. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-02-19mmc: use pr_* log functionsMasahiro Yamada1-34/+34
Use pr_* log functions from Linux. They can be enabled/disabled via CONFIG_LOGLEVEL. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2018-02-19mtd: ubi: Fix worker handlingRichard Weinberger3-25/+40
Fixes a bug found on thuban boards, which were for 2 years in a long-term test with varying temperatures. They showed problems in u-boot when attaching the ubi partition: U-Boot# run flash_self_test Booting from nand set A... UBI: attaching mtd1 to ubi0 UBI: scanning is finished data abort pc : [<87f97c3c>] lr : [<87f97c28>] reloc pc : [<8012cc3c>] lr : [<8012cc28>] sp : 85f686e8 ip : 00000020 fp : 000001f7 r10: 8605ce40 r9 : 85f68ef8 r8 : 0001f000 r7 : 00000001 r6 : 00000006 r5 : 0001f000 r4 : 85f6ecc0 r3 : 00000000 r2 : 44e35000 r1 : 87fcbcd4 r0 : 87fc755b Flags: nZCv IRQs off FIQs on Mode SVC_32 Resetting CPU ... Reason is, that accidentially the U-Boot implementation from __schedule_ubi_work() did not check the flag ubi->thread_enabled and started with wearleveling work, but ubi did not have setup all structures at this point and crashes. Solve this problem by splitting work scheduling and processing. Signed-off-by: Richard Weinberger <richard@nod.at> Signed-off-by: Heiko Schocher <hs@denx.de>
2018-02-19i2c: mvtwsi.c: Fix set speedStefan Mavrodiev1-1/+4
Previous patch for this driver breaks i2c initialization. commit 8bcf12ccce89 ("i2c: mvtwsi.c: Avoid NULL dereference") If actual_speed is passed as NULL in this function: static void __twsi_i2c_init(struct mvtwsi_registers *twsi, int speed, int slaveadd, uint *actual_speed) than __twsi_i2c_set_bus_speed never get called. This causes i2c clock to run on default speed - 2MHz (measured with oscilloscope). This is issue on some boards, sunxi for example, since on I2C0 bus PMU is connected. The bootlogs with and without the patch are as follows: Wihtout the patch: U-Boot SPL 2018.03-rc2 (Feb 13 2018 - 09:23:17 +0200) DRAM: 1024 MiB Failed to set core voltage! Can't set CPU frequency Trying to boot from FEL U-Boot 2018.03-rc2 (Feb 13 2018 - 09:23:17 +0200) Allwinner Technology CPU: Allwinner A20 (SUN7I) Model: Olimex A20-OLinuXino-LIME2 I2C: ready DRAM: 1 GiB MMC: SUNXI SD/MMC: 0 With the patch: U-Boot SPL 2018.03-rc2-00001-g838ff85 (Feb 13 2018 - 09:24:34 +0200) DRAM: 1024 MiB CPU: 912000000Hz, AXI/AHB/APB: 3/2/2 Trying to boot from FEL U-Boot 2018.03-rc2-00001-g838ff85 (Feb 13 2018 - 09:24:34 +0200) Allwinner Technology CPU: Allwinner A20 (SUN7I) Model: Olimex A20-OLinuXino-LIME2 I2C: ready DRAM: 1 GiB MMC: SUNXI SD/MMC: 0 Signed-off-by: Stefan Mavrodiev <stefan@olimex.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2018-02-18sandbox: Add 64-bit sandboxMario Six12-17/+571
To debug device tree issues involving 32- and 64-bit platforms, it is useful to have a generic 64-bit platform available. Add a version of the sandbox that uses 64-bit integers for its physical addresses as well as a modified device tree. Signed-off-by: Mario Six <mario.six@gdsys.cc> Added CONFIG_SYS_TEXT_BASE to configs/sandbox64_defconfig Signed-off-by: Simon Glass <sjg@chromium.org>
2018-02-18sandbox: Rename 'num-gpios' property to avoid dtc warningSimon Glass3-5/+6
At present dtc produces these warnings when compiling sandbox: arch/sandbox/dts/test.dtb: Warning (gpios_property): Could not get phandle node for /base-gpios:num-gpios(cell 0) arch/sandbox/dts/test.dtb: Warning (gpios_property): Missing property '#gpio-cells' in node /reset-ctl or bad phandle (referred from /extra-gpios:num-gpios[0]) Both are due to it assuming that the 'num-gpios' property holds a phandle pointing to a GPIO node. To avoid these warnings, rename the sandbox property so that it does not include the string 'gpios'. Signed-off-by: Simon Glass <sjg@chromium.org>
2018-02-18sandbox: Correct dtc warning in /chosen nodeSimon Glass1-0/+2
At present dtc produces these warnings when compiling sandbox: arch/sandbox/dts/test.dtb: Warning (reg_format): "reg" property in /chosen/chosen-test has invalid length (8 bytes) (#address-cells == 2, #size-cells == 1) arch/sandbox/dts/test.dtb: Warning (avoid_default_addr_size): Relying on default #address-cells value for /chosen/chosen-test arch/sandbox/dts/test.dtb: Warning (avoid_default_addr_size): Relying on default #size-cells value for /chosen/chosen-test Add the missing properties to avoid this. Signed-off-by: Simon Glass <sjg@chromium.org> Fixes: f200680 (dm: core: parse chosen node)
2018-02-18fdt: Fixup only valid memory banksThierry Reding1-1/+7
Memory banks with address 0 and size 0 are empty and should not be passed to the OS via device tree. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com>
2018-02-18fdt: Implement weak arch_fixup_fdt()Alexey Brodkin8-35/+7
Only ARM and in some configs MIPS really implement arch_fixup_fdt(). Others just use the same boilerplate which is not good by itself, but what's worse if we try to build with disabled CONFIG_CMD_BOOTM and enabled CONFIG_OF_LIBFDT we'll hit an unknown symbol which was apparently implemented in arch/xxx/lib/bootm.c. Now with weak arch_fixup_fdt() right in image-fdt.c where it is used we get both items highlighted above fixed. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: York Sun <york.sun@nxp.com> Cc: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-02-18net: sh_eth: Fix DT base address fetchingMarek Vasut1-10/+4
Drop the whole map/unmap_physmem stuff and just use the address already obtained from DT in ofdata_to_platdata(), instead of repeating that, wrongly, in probe. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Joe Hershberger <joe.hershberger@ni.com>
2018-02-18net: sh_eth: Fix checkpatch warningMarek Vasut1-1/+1
Fix minor checkpatch warning about udelay(3000) being too long and should be replaced by mdelay(3). Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Joe Hershberger <joe.hershberger@ni.com>
2018-02-18net: sh_eth: Return directly from sh_eth_recv_startMarek Vasut1-4/+1
Drop the len variable, it's useless. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Joe Hershberger <joe.hershberger@ni.com>
2018-02-18net: sh_eth: Zap port variableMarek Vasut1-18/+16
Inline this variable which is quite useless. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Joe Hershberger <joe.hershberger@ni.com>
2018-02-17Merge git://git.denx.de/u-boot-shTom Rini6-21/+44
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