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2021-05-23Merge https://source.denx.de/u-boot/custodians/u-boot-shWIP/23May2021Tom Rini25-377/+452
- Various clk/pinctrl updates to re-sync with Linux and other fixes
2021-05-21pinctrl: renesas: Implement unlock register masksMarek Vasut2-21/+20
The V3U SoC has several unlock registers, one per register group. They reside at offset zero in each 0x200 bytes-sized block. To avoid adding yet another table to the PFC implementation, this patch adds the option to specify an address mask instead of the fixed address in sh_pfc_soc_info::unlock_reg. This is a direct port of Linux 5.12 commit e127ef2ed0a6 ("pinctrl: renesas: Implement unlock register masks") by Ulrich Hecht <uli+renesas@fpond.eu> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-21pinctrl: renesas: Fix R-Car Gen2 help textMarek Vasut1-5/+5
The help text for Gen2 entries had a copy paste error, still containing the Gen3 string, while the description was correctly listing Gen2. Fix the help text. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-21pinctrl: renesas: Deduplicate KconfigMarek Vasut1-69/+5
The help text in the Kconfig file was always a copy of the same thing. Move single copy into the common PFC driver entry instead. Also fix a copy-paste error in the PFC help text, which identified PFC as clock. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-21gpio: renesas: Pass struct udevice to rcar_gpio_set_direction()Marek Vasut1-7/+6
Pass struct udevice to rcar_gpio_set_direction() in preparation of quirk handling in rcar_gpio_set_direction(). No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-21clk: renesas: Deduplicate gen3_clk_get_rate64() PLL handlingMarek Vasut1-43/+43
Most of the PLLx, MAIN, FIXED clock handlers are calling very similar code, which determines parent rate and then applies multiplication and division. The only difference is whether multiplication is fixed factor or coming from CRx register. Deduplicate the code into a single function. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-21clk: renesas: Add register pointers into struct cpg_mssr_infoHai Pham3-45/+65
Base on Linux v5.10-rc2, commit 8b652aa8a1fb by Yoshihiro Shimoda To support other register layouts in the future, add register pointers of {control,status,reset,reset_clear}_regs into struct cpg_mssr_info Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-21clk: renesas: Introduce enum clk_reg_layoutHai Pham1-0/+6
From Linux v5.10-rc2, commit ffbf9cf3f946 by Yoshihiro Shimoda Introduce enum clk_reg_layout to support multiple register layout variants Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-21clk: renesas: Pass struct cpg_mssr_info to renesas_clk_endisable()Hai Pham4-6/+8
CPG IP in some specific Renesas SoCs (i.e. new R8A779A0 V3U SoC) requires a different setting procedure. Make struct cpg_mssr_info accessible to handle the clock setting in that case. Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-21clk: renesas: Make reset controller modemr register offset configurableMarek Vasut20-5/+21
The MODEMR register offset changed on R8A779A0, make the MODEMR offset configurable. Fill the offset in on all clock drivers. No functional change. Based off "clk: renesas: Make CPG Reset MODEMR offset accessible from struct cpg_mssr_info" by Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-21clk: renesas: Add support for RPCD2 clockHai Pham2-5/+17
This supports RPCD2 clock handling. While at it, add the check point for RPC-IF clock RPCD2 Frequency Division Ratio, since it must be odd number Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-21clk: renesas: Fix Realtime Module Stop Control Register offsetsHai Pham1-1/+1
This patch fixes Realtime Module Stop Control Register (RMSTPCR) offsets based on R-Car Gen3, H2/M2/M2N/E2/E2X hardware user's manual. The r8a73a4 only has RMSTPCR0 - RMSTPCR5 so this calculation change doesn't affect it. Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-21clk: renesas: Fix incorrect return RPC clk_get_rateHai Pham1-1/+1
RPC clk_get_rate will return error code instead of expected clock rate. Fix this. Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-21clk: renesas: Reinstate RPC clock on R-Car D3/E3Marek Vasut2-0/+18
Reinstate RPC clock on D3/E3 after Linux 5.12 synchronization. The D3 and E3 clock drivers do not contain RPC clock entries mainline Linux yet. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-21clk: renesas: Synchronize R-Car Gen3 tables with Linux 5.12Marek Vasut7-163/+212
Synchronize R-Car Gen3 clock tables with Linux 5.12, commit 9f4ad9e425a1 ("Linux 5.12") . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-21clk: renesas: Synchronize R-Car Gen2 tables with Linux 5.12Marek Vasut5-9/+6
Synchronize R-Car Gen2 clock tables with Linux 5.12, commit 9f4ad9e425a1 ("Linux 5.12") . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-21clk: renesas: Synchronize RZ/G2 tables with Linux 5.12Marek Vasut3-5/+26
Synchronize RZ/G2 clock tables with Linux 5.12, commit 9f4ad9e425a1 ("Linux 5.12") . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2021-05-20Merge https://source.denx.de/u-boot/custodians/u-boot-marvellWIP/20May2021Tom Rini3-100/+165
- Sync Armada mvpp2 ethernet driver with Marvell version (misc Marvell authors)
2021-05-20Merge https://source.denx.de/u-boot/custodians/u-boot-riscvTom Rini27-114/+219
2021-05-20arm: mvebu: armada-3720-uDPU.dts: Change back to phy-mode "2500base-x"Stefan Roese1-2/+2
With commit 8678776df6f5 (arm: mvebu: armada-3720-uDPU: fix PHY mode definition to sgmii-2500) the PHY mode was switch to "sgmii-2500", even when this is functionally incorrect since "2500base-x" was not supported in U-Boot at that time. As this mode is now supported (at least present in the headers), this patch moves back to the orinal version. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Jakov Petrina <jakov.petrina@sartura.hr> Cc: Vladimir Vid <vladimir.vid@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
2021-05-20net: mvpp2: add explicit sgmii-2500 supportMarcin Wojtas1-16/+12
Until now the mvpp2 driver used an extra 'phy-speed' DT property in order to differentiate between the SGMII and SGMII @2.5GHz. As there is a dedicated PHY_INTERFACE_MODE_SGMII_2500 flag to mark the latter start using it and drop the custom flag. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Stefan Chulski <stefanc@marvell.com> Reviewed-by: Nadav Haklai <nadavh@marvell.com> Tested-by: Nadav Haklai <nadavh@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-05-20net: mvpp2: allow MDIO registration for fixed linksStefan Chulski1-4/+13
Currently, there are 2 valid cases for interface, PHY and mdio relation: - If an interface has PHY handler, it'll call mdio_mii_bus_get_from_phy(), which will register MDIO bus. - If we want to use fixed-link for an interface, PHY handle is not defined in the DTS, and no MDIO is registered. There is a third case, for some boards (with switch), the MDIO is used for switch configuration, but the interface itself uses fixed link. This patch allows this option by checking if fixed-link subnode is defined, in this case, MDIO bus is registers, but the PHY address is set to PHY_MAX_ADDR for this interface, so this interface will not try to access the PHY later on. Signed-off-by: Stefan Chulski <stefanc@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2021-05-20net: mvpp2: fix missing switch case breakBen Peled1-0/+2
Signed-off-by: Ben Peled <bpeled@marvell.com> Reviewed-by: Stefan Chulski <stefanc@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-05-20net: mvpp2: remove unused define MVPP22_SMI_PHY_ADDR_REGBen Peled1-3/+0
Signed-off-by: Ben Peled <bpeled@marvell.com> Reviewed-by: Stefan Chulski <stefanc@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-05-20net: mvpp2: AN Bypass in 1000 and 2500 basex modeBen Peled1-2/+4
Signed-off-by: Ben Peled <bpeled@marvell.com> Reviewed-by: Stefan Chulski <stefanc@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2021-05-20net: mvpp2: Fix 2.5G GMII_SPEED configurationsStefan Chulski1-1/+2
GMII_SPEED should be enabled for 2.5G speed Signed-off-by: Stefan Chulski <stefanc@marvell.com> Reviewed-by: Yan Markman <ymarkman@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2021-05-20net: mvpp2: remove redundant SMI address configurationMarcin Wojtas1-12/+0
Because the mvpp2 driver now relies on the PHYLIB and the external MDIO driver, configuring low level SMI bus settings is redundant. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-by: Stefan Chulski <stefanc@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-05-20net: mvpp2: add 1000BaseX and 2500BaseX ppv2 supportStefan Chulski1-5/+112
Signed-off-by: Stefan Chulski <stefanc@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-05-20net: mvpp2: add CP115 port1 10G/5G SFI supportStefan Chulski1-58/+17
1. Differ between Port1 RGMII and SFI modes in Netcomplex config. 2. Remove XPCS config from SFI mode. Port1 doesn't XPCS domain, XPCS config should be removed. Access to Port1 XPCS can cause stall. 3. Add Port1 MPCS configurations. Signed-off-by: Stefan Chulski <stefanc@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2021-05-20phy: introduce 1000BaseX and 2500BaseX modesStefan Chulski1-0/+4
Signed-off-by: Stefan Chulski <stefanc@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2021-05-19Merge tag 'xilinx-for-v2021.07-rc3' of ↵WIP/19May2021Tom Rini28-24/+3797
https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2021.07-rc3 ZynqMP: - Syncup DT with Linux kernel - Fix mmc mini configurations via DT - Add pinctrl/psgtr description to DTs - Add DTs for Kria boards - Enable RTC and Time commands Versal: - Fix early BSS section location
2021-05-19riscv: ae350: Increase malloc size for binman spl flowRick Chen4-0/+4
It will need larger heap size for u-boot-spl to load u-boot.itb which be generated from binman than USE_SPL_FIT_GENERATOR. Signed-off-by: Rick Chen <rick@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-05-19riscv: Drop USE_SPL_FIT_GENERATORBin Meng9-109/+1
Now that we have switched to binman to generate u-boot.itb for all RISC-V boards, USE_SPL_FIT_GENERATOR is no longer needed and can be dropped. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-05-19riscv: ae350: Switch to use binman to generate u-boot.itbBin Meng7-0/+13
Use the new BINMAN_STANDALONE_FDT option for AE350 based SPL defconfigs, so that binman is now used to generate u-boot.itb. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com>
2021-05-19riscv: qemu: Switch to use binman to generate u-boot.itbBin Meng6-0/+22
By utilizing the newly introduced BINMAN_STANDALONE_FDT option, along with a new dedicated device tree source file for the QEMU virt target used for binman only, we can now use binman to generate u-boot.itb. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-05-19riscv: dts: Sort build targets in alphabetical orderBin Meng1-1/+1
Sort the RISC-V DTS build targets by their Kconfig target names in alphabetical order. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-05-19binman: Support packaging U-Boot for scenarios like OF_BOARD or OF_PRIOR_STAGEBin Meng3-1/+44
For scenarios like OF_BOARD or OF_PRIOR_STAGE, no device tree blob is provided in the U-Boot build phase hence the binman node information is not available. In order to support such use case, a new Kconfig option BINMAN_STANDALONE_FDT is introduced, to tell the build system that a device tree blob containing binman node is explicitly required when using binman to package U-Boot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-05-19lib: kconfig: Limit BINMAN_FDT for OF_SEPARATE or OF_EMBEDBin Meng1-1/+1
Generally speaking BINMAN_FDT makes sense for OF_SEPARATE or OF_EMBED. For the other OF_CONTROL methods, it's quite possible binman node is not available as binman is invoked during the build phase instead of runtime. Let's only turn it on for OF_SEPARATE or OF_EMBED by default. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-05-19riscv: sifive: unleashed: Switch to use binman to generate u-boot.itbBin Meng4-0/+73
At present SiFive Unleashed board uses the Makefile to create the FIT, using USE_SPL_FIT_GENERATOR, which is deprecated as per the Makefile warning. Update to use binman instead. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-05-19makefile: Pass OpenSBI blob to binman make rulesBin Meng1-0/+1
This updates the make rules to pass OpenSBI blob to binman. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-05-19binman: Add support for RISC-V OpenSBI fw_dynamic blobBin Meng4-0/+57
Add an entry for RISC-V OpenSBI's 'fw_dynamic' firmware payload. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2021-05-19binman: test: Rename 172_fit_fdt.dts to 170_fit_fdt.dtsBin Meng2-5/+5
Currently there are 2 binman test cases using the same 172 number. It seems that 172_fit_fdt.dts was originally named as 170_, but commit c0f1ebe9c1b9 ("binman: Allow selecting default FIT configuration") changed its name to 172_ for no reason. Let's change it back. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-05-19binman: Correct the comment for ATF entry typeBin Meng1-1/+1
This is wrongly referring to Intel ME, which should be ATF. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-05-19binman: Correct '-a' description in the docBin Meng1-2/+2
It needs a space around '-a'. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com>
2021-05-19common: kconfig: Correct a typo in SPL_LOAD_FITBin Meng1-1/+1
It should be FDT, not FTD. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com>
2021-05-19xilinx: zynqmp: Enable DM_RTC/emul driver/cmd date/gettime and efi settimeMichal Simek1-0/+4
Right now U-Boot is not aware about date/time that's why enable it by default also with EFI runtime service for setting time. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-05-19xilinx: versal: Enable CONFIG_POSITION_INDEPENDENTT Karthik Reddy1-0/+1
U-Boot expects to be linked to a specific hard-coded address and to be loaded to and run from that address. CONFIG_POSITION_INDEPENDENT config lifts that restriction & allowing the code to be loaded to and executed from almost any address. As we enabled CONFIG_POSITION_INDEPENDENT, CONFIG_INIT_SP_RELATIVE is enabled by default, where it will set the early stack pointer at runtime by adding an offset value to &_bss_start. The offset value is taken from SYS_INIT_SP_BSS_OFFSET. SYS_INIT_SP_BSS_OFFSET offset should be large enough so that the early malloc region, global data (gd), and early stack should fit. With commit d8fabcc424bd ("arm64: versal: Increase SYS_MALLOC_F_LEN") SYS_MALLOC_F_LEN is increased from 32KB to 1MB, so we need to accommodate this space with SYS_INIT_SP_BSS_OFFSET. Hence increasing SYS_INIT_SP_BSS_OFFSET to 1.5MB. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-05-19arm64: zynqmp: Add description for SOM/Kria boardsMichal Simek8-1/+1110
The patch contains several DT files for SOM platform. Carrier card is sck-kv (KV260) revA/B. SMK-K26 is description for starter kit which doesn't have EMMC populated. And SM-K26 is full som with EMMC. Files are divided in this way to make sure that SOM can be plugged to different carrier card and all peripherals on SOM (or defined by a spec) can be used by U-Boot. Full DT for SOM+CC can be merged together as overlays. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-05-19arm64: zynqmp: Add psgtr DT descriptionsMichal Simek10-1/+79
Mainline kernel has psgtr driver that's why it is good to add description to DT files. Some boards are just missing description for USB3 and sata. zc1751-dc1 and p-a2197 are also missing clock descriptions for input clocks. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-05-19arm64: zynqmp: Add pinctrl descriptionMichal Simek12-1/+2489
ZynqMP pinctrl Linux driver has been merged to 5.13-rc1 kernel. Based on it DT files can be extended by pinctrl configurations. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
generated by cgit v1.1 at 2024-07-10 21:29:25 +0000