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2023-02-23Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-tegraWIP/23Feb2023Tom Rini58-309/+1051
2023-02-23Merge branch '2023-02-23-assorted-fixes'Tom Rini5-7/+16
- btrfs bugfix, silence a bunch of gcc-12.2 linker warnings finally, relax one of the trace test time requirements (so CI doesn't fail due to test being slightly slow, but still correct), and correct env on MMC and checking for where GPT can be
2023-02-23ARM: tegra20: implement BCT patchingSvyatoslav Ryhel5-4/+193
This function allows updating bootloader from u-boot on production devices without need in host PC. Be aware! It works only with re-crypt BCT. Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20 Signed-off-by: Ramin Khonsari <raminterex@yahoo.com> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23ARM: tegra30: implement BCT patchingRamin Khonsari4-0/+131
This function allows updating bootloader from u-boot on production devices without need in host PC. Be aware! It works only with re-crypted BCT. Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30 Signed-off-by: Ramin Khonsari <raminterex@yahoo.com> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23ARM: tegra: crypto: extend crypto functionalSvyatoslav Ryhel3-38/+91
Add support for encryption, decryption and signinig with non-zero key saving backward compatibility. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23ARM: tegra: expose crypto module for all Tegra SoCsSvyatoslav Ryhel6-1/+8
Move crypto module from T20 only into common Tegra dir. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23board: tegra30: switch to updated pre-dm i2c writeSvyatoslav Ryhel12-46/+200
Configure PMIC voltages for early stages using updated early i2c write. Tested-by: Thierry Reding <treding@nvidia.com> # Beaver T30 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23board: tegra124: switch to updated pre-dm i2c writeSvyatoslav Ryhel4-145/+88
Configure PMIC for early stages using updated i2c write. Tested-by: Thierry Reding <treding@nvidia.com> # Jetson TK1 T124 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23ARM: tegra: create common pre-dm i2c writeSvyatoslav Ryhel4-26/+33
This implementation allows pwr i2c writing on early SPL stages when DM is not yet setup. Such writing is needed to configure main voltages of PMIC on early SPL for bootloader to boot properly. Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30 Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30 Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23ARM: tegra: add late init supportSvyatoslav Ryhel2-0/+8
Late init function allows passing values like identifiers and perform device specific configurations of pre-boot stage. Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23ARM: tegra: provide default USB gadget setupMaxim Schwalm11-30/+3
All Nvidia boards use the same manufacturer, vendor ID and product ID for the gadgets. Make them the defaults to remove some boilerplate from the defconfigs. Inspired by commit e02687bda96c ("sunxi: provide default USB gadget setup") which did the same for Allwinner boards. Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124 Signed-off-by: Maxim Schwalm <maxim.schwalm@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23spi: tegra20_slink: accept any word lengthSvyatoslav Ryhel1-8/+11
Original t20 slink could work with commands only fully divisible by 8. This patch removes such restriction, so commands of any bitlength now can be passed and processed. Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30 Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23ARM: tegra: Fix Tegra PWM parent clockSvyatoslav Ryhel8-11/+13
Default parent clock for the PWM on Tegra is a 32kHz clock and is unable to support the requested PWM period. Fix PWM support on Tegra20, Tegra30, Tegra114, Tegra124 and Tegra210 by updating the parent clock for the PWM to be the PLL_P. This commit is equivalent to Linux kernel commit: https://lore.kernel.org/all/20221010100046.6477-1-jonathanh@nvidia.com/ Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30 Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # ASUS TF201 T30 Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23ARM: tegra30: add PLLD to pll setupSvyatoslav Ryhel1-0/+41
On T30 unlike T20 dsi panels are wider used on devices and PLLD is used as DISP1 parent more often, so lets enable it as well for this cases. Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF700T T30 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X T30 Tested-by: Thierry Reding <treding@nvidia.com> # Beaver T30 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23ARM: tegra: clock: add clock_decode_pair helperSvyatoslav Ryhel2-0/+36
Get periph clock id and its parent from device tree. This works by looking up the peripheral's 'clocks' node and reading out the second and fourth cells, which are the peripheral and PLL clock numbers. Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30 Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23ARM: tegra: clock: add clk_id_to_pll_id helperSvyatoslav Ryhel6-0/+194
This function allows to convert a device tree clock ID to PLL ID. Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30 Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23ARM: t20/t30: swap host1x and disp1 clock parentsSvyatoslav Ryhel2-4/+4
According to mainline clock tables and TRM HOST1X parent is PLLC, while DISP1 usually uses PLLP as parent clock. Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30 Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30 Tested-by: Thierry Reding <treding@nvidia.com> # Beaver T30 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23tegra30: clock: add EXTPERIPHSvyatoslav Ryhel2-6/+6
This mappings were missing for some reason. Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23env: mmc: Apply GPT only on eMMC user HW partitionWIP/2023-02-23-assorted-fixesMarek Vasut1-4/+8
Apply the GPT U-Boot environment GUID type look up only on eMMC user HW partition, do not apply the look up on eMMC boot HW partitions as mmc_offset_try_partition() assumes either SD partitions or eMMC user HW partition. This fixes environment operation on systems where CONFIG_SYS_MMC_ENV_PART is non-zero and CONFIG_SYS_REDUNDAND_ENVIRONMENT is set. Fixes: 80105d8fd52 ("env: mmc: select GPT env partition by type guid") Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
2023-02-23trace: Relax test requirementsSimon Glass1-2/+3
We expect the profile and bootstage to agree on timing, but when running on slow machines there can be a larger descrepency. Increase the tolerance to fix this. Fixes: 9cea4797aeb ("trace: Add a test") Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-23x86: Pass -z execstack for EFI payload flagsTom Rini1-1/+2
To match how we link EFI executables elsewhere, and to silence a linker warning, pass -z execstack here as well. Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Tom Rini <trini@konsulko.com>
2023-02-23Makefile: Link with -z noexectackTom Rini1-0/+1
When moving to gcc-12.2 we started trying to quiet some of the new linker warnings, that are not relevant to us. However, a misunderstanding of the mechanics at play meant that I intentionally omitted passing -z noexecstack to the linker, when we do need to. Add this flag and in turn remove warnings from the linker. Fixes: 1e1c51f8ace8 ("Makefile: link with --no-warn-rwx-segments") Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-02-23fs: btrfs: limit the mapped length to the original lengthQu Wenruo1-0/+2
[BUG] There is a bug report that btrfs driver caused hang during file read: This breaks btrfs on the HiFive Unmatched. => pci enum PCIE-0: Link up (Gen1-x8, Bus0) => nvme scan => load nvme 0:2 0x8c000000 /boot/dtb/sifive/hifive-unmatched-a00.dtb [hangs] [CAUSE] The reporter provided some debug output: read_extent_data: cur=615817216, orig_len=16384, cur_len=16384 read_extent_data: btrfs_map_block: cur_len=479944704; ret=0 read_extent_data: ret=0 read_extent_data: cur=615833600, orig_len=4096, cur_len=4096 read_extent_data: btrfs_map_block: cur_len=479928320; ret=0 Note the second and the last line, the @cur_len is 450+MiB, which is almost a chunk size. And inside __btrfs_map_block(), we limits the returned value to stripe length, but that's depending on the chunk type: if (map->type & (BTRFS_BLOCK_GROUP_RAID0 | BTRFS_BLOCK_GROUP_RAID1 | BTRFS_BLOCK_GROUP_RAID1C3 | BTRFS_BLOCK_GROUP_RAID1C4 | BTRFS_BLOCK_GROUP_RAID5 | BTRFS_BLOCK_GROUP_RAID6 | BTRFS_BLOCK_GROUP_RAID10 | BTRFS_BLOCK_GROUP_DUP)) { /* we limit the length of each bio to what fits in a stripe */ *length = min_t(u64, ce->size - offset, map->stripe_len - stripe_offset); } else { *length = ce->size - offset; } This means, if the chunk is SINGLE profile, then we don't limit the returned length at all, and even for other profiles, we can still return a length much larger than the requested one. [FIX] Properly clamp the returned length, preventing it from returning a much larger range than expected. Reported-by: Andreas Schwab <schwab@linux-m68k.org> Signed-off-by: Qu Wenruo <wqu@suse.com>
2023-02-22Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-usbWIP/22Feb2023Tom Rini1-19/+19
- DWC3 bugfix
2023-02-22Merge https://source.denx.de/u-boot/custodians/u-boot-socfpgaTom Rini11-7/+47
- chameleonv3 updates
2023-02-22chameleonv3: Convert CONFIG_SPL_MAX_SIZE to KconfigPaweł Anikiel1-0/+1
This file was missed during the conversion process. Add the symbol to defconfig. Signed-off-by: Paweł Anikiel <pan@semihalf.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-02-22arm: dts: chameleonv3: Add 270-2 variantPaweł Anikiel3-0/+18
Add devicetree for chameleonv3 with the 270-2I2-D11E variant of the Mercury+ AA1 module Signed-off-by: Paweł Anikiel <pan@semihalf.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-02-22arm: dts: chameleonv3: Rename chameleonv3.dts to .dtsiPaweł Anikiel3-2/+2
This file is included by the different chameleonv3 variants. Change the name to .dtsi. Signed-off-by: Paweł Anikiel <pan@semihalf.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-02-22arm: dts: chameleonv3: Override chameleonv3 bitstream namesPaweł Anikiel2-0/+8
Set the bitstream name per Chameleon variant. This allows the same boot filesystem with all bitstream variants to be used on different boards. Signed-off-by: Paweł Anikiel <pan@semihalf.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-02-22socfpga: chameleonv3: Move environment to a text filePaweł Anikiel2-5/+17
Move the environment to an easily editable text file in the boot partition Signed-off-by: Paweł Anikiel <pan@semihalf.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-02-22socfpga: chameleonv3: Enable ext4 in SPLPaweł Anikiel1-0/+1
Allow SPL to boot from an ext4 filesystem. Signed-off-by: Paweł Anikiel <pan@semihalf.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-02-22usb: dwc3: Use the devm_gpiod_get_optional() API for reset gpioVenkatesh Yadav Abbarapu1-19/+19
As the "reset-gpios" property is optional, don't return the error and just skip the gpio reset sequence. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
2023-02-19Merge tag 'efi-2023-04-rc3' of ↵WIP/19Feb2023Tom Rini25-216/+589
https://source.denx.de/u-boot/custodians/u-boot-efi Pull request for efi-2023-04-rc3 Documentation * Add a document for the RISC-V architecture * Move gateworks and bcm7xxx documentation to HTML UEFI * measure the loaded device-tree * make CapsuleMax configurable and provide sensible default
2023-02-19doc: remove superfluous warningHeinrich Schuchardt1-4/+0
We have been using Sphinx >=3 since 2020. We don't expect issues. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-02-19efi_loader: set CapsuleMax from CONFIG_EFI_CAPSULE_MAXEtienne Carriere3-15/+48
Adds CONFIG_EFI_CAPSULE_MAX to configure the max index value used in EFI capsule reports. Prior to this change is the hard coded value was 65535 which would exceed available storage for variables. Now the default value is 15 which should work fine with most systems. Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
2023-02-19efi_loader: Measure the loaded DTBEtienne Carriere6-0/+106
Measures the DTB passed to the EFI application upon new boolean config switch CONFIG_EFI_TCG2_PROTOCOL_MEASURE_DTB. For platforms where the content of the DTB passed to the OS can change across reboots, there is not point measuring it hence the config switch to allow platform to not embed this feature. Co-developed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Tested-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2023-02-19efi_loader: fix wrong attribute check for QueryVariableInfoMasahisa Kojima1-3/+0
QueryVariableInfo with EFI_VARIABLE_HARDWARE_ERROR_RECORD is accepted, remove wrong attribute check. Fixes: 454a9442fbce ("efi_loader: update attribute check for QueryVariableInfo()") Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-02-19efi_loader: avoid buffer overrun in efi_var_mem_compareHeinrich Schuchardt1-1/+3
We should not scan beyond the end of string name. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-02-19doc: arch: Add document for RISC-V architectureYu Chien Peter Lin3-0/+83
This patch adds a brief introduction to the RISC-V architecture and the typical boot process used on a variety of RISC-V platforms. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-02-19board: gateworks: venice: move README to RSTTim Harvey7-35/+163
Move board/gateworks/venice/README to RST documentation. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2023-02-19doc: board: bcm7xxx: Convert to reStructuredText formatThomas Fitzsimmons3-156/+184
Convert the documentation for the Broadcom BCM7445 and BCM7260 boards to reStructuredText format and add the new filename to doc/board/broadcom/index.rst. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-02-19doc: devicetree: dt_qemu.rst: Fix the typo and spaceYu Chien Peter Lin1-2/+2
Fix typo and whitespace in the document. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2023-02-17Merge branch '2023-02-17-assorted-fixes'Tom Rini2-7/+8
- avb_verify bugfix, and cpsw_mdio bugfix
2023-02-17common: avb_verify: prevent opening incorrect sessionWIP/2023-02-17-assorted-fixesIvan Khoronzhuk1-4/+5
The arg->session is not valid if arg->ret != NULL, so can't be assigned, correct this. Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@globallogic.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
2023-02-17cpsw_mdio.c: Use correct reg in cpsw_mdio_get_aliveUlf Samuelsson1-3/+3
cpsw_mdio_get_alive reads the wrong register. See page 2316 in SPRUH73Q AM335x TRM Signed-off-by: Ulf Samuelsson <ulf@emagii.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
2023-02-17configs: Resync with savedefconfigTom Rini718-1775/+1572
Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2023-02-17Merge https://source.denx.de/u-boot/custodians/u-boot-riscvTom Rini32-321/+331
- binman: Add help message if opensbi is absent when building u-boot SPL - AndesTech: rename cpu and board name to 'andesv5' and 'ae350' - Clean up cache operation for Andes ae350 platform
2023-02-17riscv: binman: Add help message for missing blobsRick Chen2-0/+7
Add the 'missing-msg' for more detailed output on missing system firmware. Signed-off-by: Rick Chen <rick@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
2023-02-17riscv: ae350: Adjust the memory layout of ae350Leo Yu-Chi Liang4-12/+12
Adjust the initial stack pointer address to 0x10000000(256M) Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-17riscv: Rename Andes cpu and board namesLeo Yu-Chi Liang22-30/+30
The current ae350-related defconfigs could also support newer Andes CPU IP, so modify the names of CPU from ax25 to andesv5, and board name from ax25-ae350 to ae350. Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
generated by cgit v1.1 at 2024-08-16 02:35:44 +0000